EFuse unit structure and array thereof
By introducing power control tubes and bypass control tubes into the eFuse unit, a parallel loop is formed, which solves the programming errors and IR-Drop problems of conventional eFuse units when powered on, ensuring programming reliability and read and write functions.
Patent Information
- Application Number
- CN202411622775.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-01-10
AI Technical Summary
Conventional eFuse units may be misprogrammed due to unexpected current when powered on, and as the efuse capacity increases, the fuse programming current faces IR-Drop problems, affecting programming reliability.
The power control tube, fuse and bypass control tube are introduced into the eFuse unit structure to form a controlled parallel loop to reduce unexpected current on the fuse, ensure that the current is limited in non-read and write modes and avoid accidental programming.
It effectively reduces the unexpected current on the fuse, avoids programming errors caused by IR-Drop problems, and ensures the reliability of the read and write function of the eFuse unit.
Smart Images
Figure CN119296616A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an eFuse unit structure and an array thereof. Background Art
[0002] eFuse is based on the principle of electron migration (EM) and realizes programming function by blowing the fuse. In essence, the internal module of efuse converts the fuse resistance value into the corresponding logic value. The specific principle is to compare the fuse resistance before and after the fuse is blown with the reference resistance through a comparison circuit to generate different levels.
[0003] The conventional efuse unit consists of a fuse link and an NMOS control selection tube, such as Figure 1 shown.
[0004] An array consisting of conventional efuse units such as Figure 2 As shown, the array is composed of bit lines and word lines. During the programming operation of the conventional efuse cell array, the control signal RD=0 closes the path from all bit lines BL in the array to the SA module. One bit line control signal BLC1 in the array is 0, which opens the path from VDDQ to the bit line BL, so that the voltage of the bit line BL is VDDQ; the other bit line control signals BLC2~n are VDDQ, closing the path from VDDQ to the bit line BL. One word line WL in the array is selected, the voltage on the word line is VDDQ, and the NMOS selection tubes of all efuse cells on the row are turned on; the other word lines WL in the array are not selected, the voltage is 0, and the NMOS selection tubes of all efuse cells on the row are turned off. On the efuse cell between the bit line BL with a voltage of VDDQ and the word line WL with a voltage of VDDQ, a VDDQ-to-ground path is formed, and the programming current flows through the fuse link, programming it by blowing the fuse, and no path between VDDQ and ground is formed on other efuse cells, so they remain in a non-programmed state.
[0005] However, when the conventional efuse unit is powered on, the unexpected current passing through the fuse will cause it to be programmed, resulting in the read module outputting an erroneous logic value. In addition, as the efuse capacity increases, the efuse unit array area increases, and the bit line length increases, the programming current required for the fuse faces the problem of IR-Drop, which may seriously affect the programming reliability of the efuse. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an eFuse unit structure and an array thereof, so as to solve the problems of the prior art fuse being erroneously programmed and the programming voltage being reduced.
[0007] To achieve the above-mentioned and other related purposes, the present invention provides an eFuse unit structure, which includes: a power control tube, a fuse, a control selection tube and a bypass control tube.
[0008] The source of the power control tube is used to connect the programming power supply, the drain is connected to the anode of the fuse and is used to connect the SA module, and the gate is used to connect the bit line;
[0009] The cathode of the fuse is connected to the drain of the control selection tube;
[0010] The gate of the control selection tube is used to connect the word line, and the source thereof is used to ground;
[0011] The gate of the bypass control tube is used to receive a system chip selection signal, the drain of the bypass control tube is connected to the anode of the fuse, and the source of the bypass control tube is connected to the cathode of the fuse.
[0012] Optionally, the power control tube is a PMOS tube, and the bypass control tube and the control selection tube are NMOS tubes.
[0013] Optionally, in the layout, the power control tube, the fuse, the bypass control tube and the control selection tube are arranged closely side by side, and the finger width and channel length of the power control tube are the same as the finger width and channel length of the bypass control tube and the control selection tube.
[0014] Optionally, the drain of the bypass control tube is connected to the anode of the fuse through a first metal layer, the source thereof is connected to the cathode of the fuse through a second metal layer, the gate thereof receives the system chip select signal through a contact hole, the gate of the power control tube is connected to the word line through the contact hole, the source thereof is connected to the programming power supply through the contact hole, the drain thereof is connected to the anode of the fuse through the first metal layer, the drain of the control selection tube shares the AA layer with the source of the bypass control tube, the gate thereof is connected to the word line through the contact hole, and the source thereof is grounded through the contact hole.
[0015] Accordingly, the present invention further provides an eFuse cell array, comprising: the eFuse cell structure as described above and N read control transistors,
[0016] The eFuse unit structure and the N read control tubes form an N*N unit array, and the drain of the power control tube in the same column of the eFuse unit structure is connected to the drain of the same read control tube, the gate of each read control tube receives a control signal, and its source is connected to the SA module;
[0017] The gates of the control selection tubes in the same row are all connected to the same word line and are grounded through their respective sources;
[0018] The gates of the power control tubes of the eFuse unit structures in the same column are connected to the same bit line;
[0019] The gate of each power control tube is connected to a programming power supply;
[0020] The gate of the bypass control tube of each eFuse unit structure receives a system chip select signal;
[0021] Wherein, N is a positive integer greater than or equal to 1.
[0022] Optionally, the read control tube, the bypass control tube and the control selection tube are all NMOS tubes, and the power control tube is a PMOS tube.
[0023] Optionally, the eFuse programming array includes a programming mode, a read mode and a sleep mode.
[0024] Optionally, when the eFuse programming array is in programming mode and the eFuse unit structure in the i-th row and j-th column is programmed, the word line control signal received by the i-th word line connected to the eFuse unit structure in the i-th row is 1, and the word line control signals received by the other N-1 word lines are all 0, the bit line control signal received by the j-th bit line connected to the eFuse unit structure in the j-th column is 0, and the bit line control signals received by the other N-1 bit lines are all 1, the control signal received by each read control tube is 0, and the system chip select signal received by each bypass control tube is 0, wherein i and j are positive integers, and 1≤i, j≤N.
[0025] Optionally, when the eFuse programming array is in read mode and the i-th row is read, the word line control signal received by the i-th word line connected to the eFuse unit structure in the i-th row is 1, the word line control signals received by the other N-1 word lines are all 0, the bit line control signal received by each bit line is 1, the control signal received by each read control tube is 1, and the system chip select signal received by each bypass control tube is 0, wherein i is a positive integer and 1≤i≤N.
[0026] Optionally, when the eFuse programming array is in sleep mode, the word line control signal received by each word line is 0, the bit line control signal received by each bit line is 1, the control signal received by each read control tube is 0, and the system chip select signal received by each bypass control tube is 1.
[0027] Optionally, the number N is 2.
[0028] As described above, the eFuse unit structure and array of the present invention are used to reduce the size of the unexpected current flowing through the fuse by integrating a power control tube into the eFuse unit circuit and adding a controlled parallel loop (bypass control tube) next to the fuse to form the eFuse unit structure. In this way, all eFuse unit structures are directly connected between the programming power supply and the ground, and are no longer affected by the IR-Drop (current reduction) problem. At the same time, the eFuse unit structure array can limit the size of the current flowing through the fuse in the non-read-write working mode, thereby avoiding accidental programming. In the normal read-write working mode, the fuse working current is not affected, ensuring the read-write function of the efuse unit structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 Shown is a schematic diagram of an existing conventional eFuse unit circuit.
[0030] Figure 2 Display as Figure 1 Schematic diagram of an array composed of eFuse units shown.
[0031] Figure 3 Shown is a schematic diagram of the eFuse unit structure circuit of the present invention.
[0032] Figure 4 Shown is a schematic layout diagram of the eFuse unit structure of the present invention.
[0033] Figure 5 Shown is a schematic diagram of a 2*2 array structure composed of the eFuse unit structure of the present invention.
[0034] Figure 6 Display as Figure 5 A schematic diagram showing an array in a programming operation state.
[0035] Figure 7 Display as Figure 5 Schematic diagram of the array in read operation state.
[0036] Figure 8 Display as Figure 5 Schematic diagram of the array shown in sleep mode.
[0037] Fig. 9 Implemented as Figure 5 Schematic diagram of the layout of the first row of the array structure shown. DETAILED DESCRIPTION
[0038] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0040] Embodiment 1
[0041] like Figure 3 As shown, this embodiment provides an eFuse unit structure, which includes: a power control tube Mp, a fuse link, a control selection tube N1 and a bypass control tube N2.
[0042] The source of the power control tube Mp is used to connect the programming power supply VDDQ, the drain is connected to the anode of the fuse and is used to connect the SA module, and the gate is used to connect the bit line BL;
[0043] The cathode of the fuse link is connected to the drain of the control selection tube N1;
[0044] The gate of the control selection transistor N1 is used to connect the word line, and the source thereof is used to ground;
[0045] The gate of the bypass control tube N2 is used to receive the system chip selection signal CSB, the drain of the bypass control tube N2 is connected to the anode of the fuse, and the source of the bypass control tube N2 is connected to the cathode of the fuse.
[0046] In this embodiment, the source of the power control tube Mp serves as the programming power supply VDDQ port, the drain of the power control tube Mp serves as the SA port, and the gate of the power control tube Mp serves as the BL port; the gate of the control selection tube N1 serves as the WL port, and the source of the control selection tube N1 serves as the VSS port; the gate of the bypass control tube N2 serves as the CSB port.
[0047] Specifically, the power control tube Mp is a PMOS tube, and the bypass control tube N2 and the control selection tube N1 are NMOS tubes.
[0048] Specifically, in the layout, the power control tube Mp, the fuse link, the bypass control tube N2 and the control selection tube N1 are arranged closely side by side, and the finger width and channel length of the power control tube are the same as the finger width and channel length of the bypass control tube and the control selection tube.
[0049] In this embodiment, the power control tube is two PMOS tubes of the same size connected in series, and the two PMOS tubes share the same source. In this embodiment, the PMOS tube and NMOS tube with the same finger width and channel length are used to ensure the same size.
[0050] More specifically, the drain of the bypass control tube N2 is connected to the anode of the fuse link through the first metal layer, the source thereof is connected to the cathode of the fuse link through the second metal layer M2, the gate thereof receives the system chip select signal CSB through the contact hole CT, the gate of the power control tube Mp is connected to the word line through the contact hole CT, the source thereof is connected to the programming power supply through the contact hole CT, the drain thereof is connected to the anode of the fuse link through the first metal layer M1, the drain of the control selection tube N1 shares the AA layer with the source of the bypass control tube N2, the gate thereof is connected to the word line WL through the contact hole CT, and the source thereof is grounded through the contact hole CT.
[0051] like Figure 4 As shown, in this embodiment, the blue box indicates that the drain of the bypass control tube N2, the drain of the power control tube Mp and the anode of the fuse (represented by P+AA in the figure) in the eFuse unit structure are connected through the first metal layer (M1); the green box indicates that the source of the bypass control tube N2 is connected to the cathode of the fuse through the second metal layer (M2). Moreover, in the figure, the drain of the bypass control tube N2 and the source of the control selection tube N1 share the same active area (the area between the gate of the bypass control tube N2 and the gate of the control selection tube N1). It should be noted that some of the contact holes (green squares) of the drain of the bypass control tube N2 circled in the green box are only schematic representations of the connection relationship. In practice, all the contact holes of the drain of the bypass control tube N2 are connected to the cathode of the fuse; similarly, some of the contact holes (blue squares) of the source of the bypass control tube N2 and some of the contact holes (blue squares) of the drain of the power control tube Mp circled in the blue box are also only schematic representations of the connection relationship. In practice, the fuse is connected to all the contact holes of the source of the bypass control tube N2 and all the contact holes of the drain of the power control tube Mp.
[0052] Embodiment 2
[0053] like Figure 5As shown, this embodiment provides an eFuse unit structure array, including: the eFuse unit structure as described in the first embodiment and N read control transistors Mn,
[0054] The eFuse unit structure and the N read control tubes form an N*N unit array, and the drain of the power control tube in the same column of the eFuse unit structure is connected to the drain of the same read control tube, the gate of each read control tube receives the control signal RD, and its source is connected to the SA module;
[0055] The gates of the control selection transistors N1 in the same row are connected to the same word line WL and are grounded through their respective sources;
[0056] The gates of the power control tubes of the eFuse unit structures in the same column are connected to the same bit line BL;
[0057] The gate of each power control tube is connected to the programming power supply VDDQ;
[0058] The gate of the bypass control tube N2 of each eFuse unit structure receives the system chip select signal CSB;
[0059] Wherein, N is a positive integer greater than or equal to 1.
[0060] In this embodiment, the gates of the control selection tubes N1 in the same row are connected to the same word line WL through their respective WL ports, and are grounded through their respective sources through the VSS port. The gates of the power control tubes are connected to the programming power supply VDDQ through their respective VDDQ ports, and the gates of the bypass control tubes N2 of the eFuse unit structures receive the system chip select signal CSB through their respective CSB ports.
[0061] Specifically, the read control tube, the bypass control tube N2 and the control selection tube N1 are all NMOS tubes, and the power control tube is a PMOS tube.
[0062] Specifically, the eFuse programming array includes a programming mode, a read mode and a sleep mode.
[0063] More specifically, when the eFuse programming array is in programming mode and the eFuse unit structure in the i-th row and j-th column is programmed, the word line control signal received by the i-th word line WLi connected to the eFuse unit structure in the i-th row is 1, and the word line control signals received by the other N-1 word lines are all 0, the bit line control signal received by the j-th bit line BLj connected to the eFuse unit structure in the j-th column is 0, and the bit line control signals received by the other N-1 bit lines are all 1, the control signal RD received by each read control tube is 0, and the system chip select signal CSB received by each bypass control tube N2 is 0, wherein i and j are positive integers, and 1≤i, j≤N.
[0064] More specifically, when the eFuse programming array is in read mode and the i-th row is read, the word line control signal received by the i-th word line WLi connected to the eFuse unit structure in the i-th row is 1, the word line control signals received by the other N-1 word lines are all 0, the bit line control signals received by each bit line are all 1, the control signal RD received by each read control tube Mn is 1, and the system chip select signal CSB received by each bypass control tube N2 is 0, wherein i is a positive integer and 1≤i≤N.
[0065] More specifically, when the eFuse programming array is in sleep mode, the word line control signal received by each word line is 0, the bit line control signal received by each bit line is 1, the control signal RD received by each read control tube is 0, and the system chip select signal CSB received by each bypass control tube N2 is 1.
[0066] Specifically, the number of N is 2.
[0067] like Figure 5 As shown, in this embodiment, N takes the value of 2, forming a 2x2 eFuse programming array, which includes a first read control tube Mn1 and a second read control tube Mn2, a first word line WL1 and a second word line WL2, a first bit line BL1 and a second bit line BL2, a first SA module SA1 and a second SA module SA2, and the two power control tubes in each row are represented as Mp1 and Mp2, the source of Mp1 is connected to the first SA module SA1, and the source of Mp2 is connected to the second SA module SA2. The array has a normal working state and a fuse protection state. The normal working state refers to the eFuse unit structure being in a programming or reading working state, and the fuse protection state refers to the eFuse unit structure being in a sleep mode. In the normal working state, CSB=0, and the fuse protection tube in each unit in the array (that is, the current bypass path formed by the bypass control tube) is in an open state.
[0068] like Figure 6As shown, the array is in programming mode, BL1=0, BL2=1, power control tube Mp1 is turned on; WL1=1, WL2=0, the efuse unit structure of the first column and the first row in the array is turned on; RD=0, the path of BL1 and BL2 to SA and SA2 is turned off. The programming current flows from VDDQ through the power control tube Mp1, the fuse to the ground (arrow pointing), and the eFuse unit structure of the first row and the first column where the fuse is located is programmed.
[0069] like Figure 7 As shown, the array is in read mode, BL1 = 1, BL2 = 1, power control tubes Mp1 and Mp2 are disconnected; WL1 = 1, WL2 = 0, the efuse unit in the first row of the array is turned on; RD = 1. The read current passes through the fuses on the first row from SA1 and SA2 to the ground, and the information values of the two eFuse unit arrays in the row are read out by SA1 and SA2 respectively.
[0070] like Figure 8 As shown, the array is in sleep mode, CSB is high, that is, CSB=1, and the bypass control tube N2 is in the on state. Since it is connected in parallel with the fuse, all the unexpected current that originally passed through the fuse flows through the bypass, thereby reducing the fuse current and preventing the fuse from being accidentally programmed in the eFuse sleep mode.
[0071] Furthermore, if Fig. 9 As described above, this embodiment also provides a layout connection method for a 1x 2eFuse unit array. The blue box indicates that the bypass control tube N2, the power control tube Mp (including Mp1 and Mp2) and the fuse anode in the eFuse unit structure are connected through the first metal layer (M1) and connected to the SA port (including SA1 and SA2). The green box indicates that the bypass control tube is connected to the first metal layer through the second metal layer (M2) through the contact hole. The orange box indicates that the source of the power control tube is connected to the programming power supply VDDQ through the third metal layer (M3) or the control selection tube is connected to VSS through the third metal layer (M3). Moreover, the finger width and channel length of all MOS tubes are the same.
[0072] In summary, the eFuse unit structure and array of the present invention integrate a power control tube into the eFuse unit circuit, and add a controlled parallel loop (bypass control tube) next to the fuse to form an eFuse unit structure, so as to reduce the size of the unexpected current flowing through the fuse. In this way, all eFuse unit structures are directly connected between the programming power supply and the ground, and are no longer affected by the IR-Drop (current reduction) problem. At the same time, the eFuse unit structure array can limit the current flowing through the fuse in the non-read-write working mode, thereby avoiding accidental programming. In the normal read-write working mode, the fuse working current is not affected, ensuring the read-write function of the efuse unit structure. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0073] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. An eFuse unit structure, characterized in that: The structure includes: a power control tube, a fuse, a control selection tube and a bypass control tube. The source of the power control tube is used to connect the programming power supply, the drain is connected to the anode of the fuse and is used to connect the SA module, and the gate is used to connect the bit line; The cathode of the fuse is connected to the drain of the control selection tube; The gate of the control selection tube is used to connect the word line, and the source thereof is used to ground; The gate of the bypass control tube is used to receive a system chip selection signal, the drain of the bypass control tube is connected to the anode of the fuse, and the source of the bypass control tube is connected to the cathode of the fuse.
2. The eFuse unit structure according to claim 1, characterized in that: The power control tube is a PMOS tube, and the bypass control tube and the control selection tube are NMOS tubes.
3. The eFuse unit structure according to claim 2, characterized in that: In the layout, the power control tube, the fuse, the bypass control tube and the control selection tube are arranged closely side by side, and the finger width and channel length of the power control tube are the same as those of the bypass control tube and the control selection tube.
4. The eFuse unit structure according to claim 3, characterized in that: The drain of the bypass control tube is connected to the anode of the fuse through the first metal layer, the source of the bypass control tube is connected to the cathode of the fuse through the second metal layer, the gate of the bypass control tube receives the system chip select signal through the contact hole, the gate of the power control tube is connected to the word line through the contact hole, the source of the bypass control tube is connected to the programming power supply through the contact hole, the drain of the bypass control tube is connected to the anode of the fuse through the first metal layer, the drain of the control selection tube shares the AA layer with the source of the bypass control tube, the gate of the bypass control tube is connected to the word line through the contact hole, and the source of the bypass control tube is grounded through the contact hole.
5. An eFuse unit structure array, characterized in that: include: The eFuse unit structure and N read control transistors as claimed in claim 1, The eFuse unit structure and the N read control tubes form an N*N unit array, and the drain of the power control tube in the same column of the eFuse unit structure is connected to the drain of the same read control tube, the gate of each read control tube receives a control signal, and its source is connected to the SA module; The gates of the control selection tubes in the same row are all connected to the same word line and are grounded through their respective sources; The gates of the power control tubes of the eFuse unit structures in the same column are connected to the same bit line; The gate of each power control tube is connected to a programming power supply; The gate of the bypass control tube of each eFuse unit structure receives a system chip select signal; Wherein, N is a positive integer greater than or equal to 1.
6. The eFuse unit structure array according to claim 5, characterized in that: The read control tube, the bypass control tube and the control selection tube are all NMOS tubes, and the power control tube is a PMOS tube.
7. The eFuse unit structure array according to claim 5 or 6, characterized in that: The eFuse programming array includes a programming mode, a read mode, and a sleep mode.
8. The eFuse unit structure array according to claim 7, characterized in that: When the eFuse programming array is in programming mode and the eFuse unit structure in the i-th row and j-th column is programmed, the word line control signal received by the i-th word line connected to the eFuse unit structure in the i-th row is 1, and the word line control signals received by the other N-1 word lines are all 0, the bit line control signal received by the j-th bit line connected to the eFuse unit structure in the j-th column is 0, and the bit line control signals received by the other N-1 bit lines are all 1, the control signals received by each read control tube are all 0, and the system chip select signals received by each bypass control tube are all 0, wherein i and j are positive integers, and 1≤i, j≤N.
9. The eFuse unit structure array according to claim 7, characterized in that: When the eFuse programming array is in read mode and the i-th row is read, the word line control signal received by the i-th word line connected to the eFuse unit structure in the i-th row is 1, the word line control signals received by the other N-1 word lines are all 0, the bit line control signal received by each bit line is 1, the control signal received by each read control tube is 1, and the system chip select signal received by each bypass control tube is 0, wherein i is a positive integer and 1≤i≤N.
10. The eFuse unit structure array according to claim 7, characterized in that: When the eFuse programming array is in sleep mode, the word line control signal received by each word line is 0, the bit line control signal received by each bit line is 1, the control signal received by each read control tube is 0, and the system chip select signal received by each bypass control tube is 1.
11. The eFuse unit structure array according to claim 5, characterized in that: The number of N is 2.