Chip repairing method and device, equipment and medium

Abstract

The invention provides a chip repairing method and device, equipment and a medium, and relates to the technical field of semiconductors. The method comprises the following steps: determining a target fault storage unit in a plurality of storage blocks; determining a first storage unit column to which the target fault storage unit belongs, and determining a second storage unit column adjacent to the first storage unit column in the column direction; and adding the first storage unit column and the second storage unit column to the to-be-repaired fault column so as to pre-repair the first storage unit column and the second storage unit column when the to-be-repaired fault column is repaired. According to the embodiment of the invention, the chip yield can be improved.

Description

Background Art

[0002] During the development of semiconductor technology, factors such as the increase in chip capacity and density have led to an increase in failed memory cells on the chip, affecting the chip yield.

[0003] In order to improve the chip yield, at present, it is often necessary to repair the faulty memory cells on the chip. However, the repair methods in the related art are often unable to effectively repair the memory cells, which affects the chip yield.

[0004] Therefore, how to improve chip yield has become a technical problem that needs to be solved urgently.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The present disclosure provides a chip repair method, device, equipment and medium, which at least to a certain extent overcome the problem of low chip yield in related technologies.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a chip repair method is provided, wherein the chip includes a plurality of memory blocks, each memory block includes memory cells arranged in an array, wherein a memory cell column in each memory block corresponds to a bit line; the method includes:

[0009] determining a target failed memory cell in a plurality of memory blocks;

[0010] Determine a first storage cell column to which the target faulty storage cell belongs, and determine a second storage cell column adjacent to the first storage cell column in a column direction;

[0011] The first storage cell column and the second storage cell column are added to the fault column to be repaired, so that the first storage cell column and the second storage cell column are pre-repaired when the fault column to be repaired is repaired.

[0012] In one embodiment, determining target failed storage cells in a plurality of storage blocks includes:

[0013] determining a failed memory cell in a plurality of memory blocks;

[0014] A faulty storage unit that meets a preset pre-repair determination condition is determined as a target faulty storage unit.

[0015] In one embodiment, the preset pre-repair determination condition includes: the number of failed storage cells on the corresponding storage cell column reaches a preset number condition;

[0016] Determining a faulty storage unit that meets a preset pre-repair determination condition as a target faulty storage unit includes:

[0017] For each faulty storage unit, detecting the number of faulty storage units in the storage unit column to which each faulty storage unit belongs;

[0018] When the number of detected faulty storage units reaches a preset number condition, each faulty storage unit is determined as a target faulty storage unit.

[0019] In one embodiment, the preset pre-repair determination condition further includes that the faulty storage unit is detected during a sense amplifier test.

[0020] The method further comprises: determining a faulty storage unit that meets a preset pre-repair determination condition as a target faulty storage unit;

[0021] For each faulty storage unit, detecting whether each faulty storage unit is the first faulty storage unit detected during the sense amplifier test;

[0022] In a case where each of the failed storage units is the first failed storage unit, each of the failed storage units is determined as the target failed storage unit.

[0023] In one embodiment, after detecting whether each faulty storage unit is the first faulty storage unit detected during the sense amplifier test, the method further includes:

[0024] In the case that each faulty storage unit is not the first faulty storage unit, each faulty storage unit is repaired according to the original fault repair scheme.

[0025] In one embodiment, after determining the first storage unit column to which the target faulty storage unit belongs, the method further includes:

[0026] In the column direction, determining adjacent sense amplifiers of the first memory cell column;

[0027] The adjacent sense amplifier is added to the faulty column to be repaired, so as to pre-repair the adjacent sense amplifier when the faulty column to be repaired is repaired.

[0028] In one embodiment, adding the first storage unit column and the second storage unit column to the fault column to be repaired includes:

[0029] The position information of the first storage unit column and the position information of the second storage unit column are written into the file to be repaired, so as to perform fault repair based on the file to be repaired.

[0030] According to another aspect of the present disclosure, a chip repair device is provided, wherein the chip includes a plurality of memory blocks, each memory block includes memory cells arranged in an array, wherein a memory cell column in each memory block corresponds to a bit line; the device includes:

[0031] A faulty storage unit determination module, used to determine a target faulty storage unit in a plurality of storage blocks;

[0032] A storage cell column determination module, used to determine a first storage cell column to which a target faulty storage cell belongs, and to determine a second storage cell column adjacent to the first storage cell column in a column direction;

[0033] The module for determining the faulty column to be repaired is used to add the first storage unit column and the second storage unit column to the faulty column to be repaired, so as to pre-repair the first storage unit column and the second storage unit column when the faulty column to be repaired is repaired.

[0034] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-mentioned chip repair method by executing the executable instructions.

[0035] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned chip repair method is implemented.

[0036] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and the computer program implements the above chip repair method when executed by a processor.

[0037] The chip repair method, device, equipment and medium provided by the embodiments of the present disclosure can determine the first storage cell column to which the target faulty storage cell belongs, and determine the second storage cell column adjacent to the first storage cell column in the column direction. Since the fault of the target faulty storage cell may be caused by an abnormality in the sensing amplifier, by adding the first storage cell column and the second storage cell column to the faulty column to be repaired, the first storage cell column and the second storage cell column that have not failed can be pre-repaired in advance when the column of the faulty column to be repaired is repaired, thereby avoiding the possibility of the first storage cell column and the second storage cell column being abnormal during the later stage testing and use due to the abnormality in the sensing amplifier, thereby improving the chip yield.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0040] Figure 1 A system architecture diagram of a test system provided by an embodiment of the present disclosure is shown;

[0041] Figure 2 A schematic diagram of the structure of a chip provided by an embodiment of the present disclosure is shown;

[0042] Figure 3 A logic schematic diagram of a chip repair method provided by an embodiment of the present disclosure is shown;

[0043] Figure 4 A schematic diagram showing an exemplary chip repair method provided by an embodiment of the present disclosure;

[0044] Figure 5 A schematic diagram showing another exemplary chip repair method provided by an embodiment of the present disclosure;

[0045] Figure 6 A schematic diagram of a chip repair method provided by an embodiment of the present disclosure is shown;

[0046] Figure 7 A schematic diagram showing a flow chart of another chip repair method provided by an embodiment of the present disclosure;

[0047] Figure 8 A schematic flow chart of an exemplary chip repair method provided by an embodiment of the present disclosure is shown;

[0048] Fig. 9 A schematic diagram of a chip repair device provided by an embodiment of the present disclosure is shown;

[0049] Fig.10 A structural block diagram of an electronic device provided by an embodiment of the present disclosure is shown; and

[0050] Fig.11 A schematic diagram of a computer-readable storage medium provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0051] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0052] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0053] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0054] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0055] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0056] As chip capacity and density increase, the number of failed memory cells on the chip increases, affecting the chip yield. In order to improve the chip yield, the chip often needs to be repaired.

[0057] Therefore, how to improve chip yield through chip repair has become a technical problem that needs to be solved urgently.

[0058] For ease of understanding, before introducing the technical solution provided by the embodiments of the present disclosure, the technical terms, test system, chip structure, and chip repair method involved in the embodiments of the present disclosure are first explained.

[0059] The technical terms involved in the embodiments of the present disclosure are explained as follows.

[0060] (1) Wafer Probing (CP), which can be a process for testing the entire wafer. During wafer testing, a probe station can be used to perform probe testing on the die on the wafer. During the CP testing phase, a wafer level burn-in test (WLBI) can be performed on the chip. .

[0061] (2) Final Test (FT), referred to as FT test, is used to test the performance of the packaged chip and detect the process level of the package. In the FT test, the chip to be adjusted can be subjected to a burning process, a reflow process, an aging test process, etc. In addition, according to the data transmission rate, the FT test can include a high-speed test stage and a low-speed test stage. Among them, the high-speed test stage may include the process of high-speed operation test, such as the third FT test process FT3 and the fourth FT test process FT4. The low-speed test stage may include the process of low-speed array test, such as the first FT test process FT1 and the second FT test process FT2.

[0062] (3) Sense Amplifier (SA), which is an important component for realizing chip reading, writing and dynamic refresh. Its principle is to sense the tiny voltage changes on the target bit line through the principle of differential amplification and amplify it to convert it into a digital signal.

[0063] After introducing the technical terms, the test system involved in the embodiment of the present disclosure will be described next.

[0064] Figure 1 FIG. 1 shows a system architecture diagram of a test system provided by an embodiment of the present disclosure. Figure 1 As shown, the test system may include a test platform 10 and a plurality of chips 20 placed on the test platform 10 .

[0065] The test machine 10 can perform a fault test on the chip. When performing chip testing, multiple chips 20 can be used as a DUT. In addition, the test machine 10 can also determine the first storage unit column and the second storage unit column according to the target fault storage unit, and add the determined first storage unit column and the second storage unit column to the fault column to be repaired. Optionally, the test machine 10 can also perform fault repair on the chip.

[0066] Exemplarily, the test machine 10 may be an automatic test equipment (ATE). Exemplarily, the test machine 10 may be a machine with FT testing capability, for example, a high-speed machine.

[0067] For chip 20, illustratively, the chip in the embodiment of the present disclosure may include: dynamic random access memory (DRAM), static random access memory (SRAM) or flash memory. For example, the chip may be a dual data rate synchronous dynamic random access memory (DDR SDRAM) or a low power dual data rate synchronous dynamic random access memory (LPDDR SDRAM). For example, the chip may be DDR3, DDR4, DDR5, DDR6, LPDDR4, LPDDR5, LPDDR6, etc., and the present disclosure does not limit the chip type.

[0068] After introducing the test system, the chip structure provided by the embodiment of the present disclosure is described next.

[0069] Figure 2 FIG. 1 shows a schematic diagram of the structure of a chip provided by an embodiment of the present disclosure. Figure 2 As shown, the chip may include multiple storage blocks (Sections) and SA areas, such as Figure 2 The storage blocks 20-storage blocks 22, and the SA areas 31-SA areas 32.

[0070] Each storage block may include storage cells 11 arranged in an array. A storage cell column in each storage block corresponds to a bit line. For example, taking storage block 20 as an example, the same column of storage cells in the column direction is a storage cell column, for example, the first column of storage cells corresponds to bit line BL01, the second column of storage cells corresponds to bit line BL02, ..., and the fourth column of storage cells corresponds to bit line BL04.

[0071] And, continue to see Figure 2 , SA region 31 may include multiple sense amplifiers SA311-SA314, and SA region 32 may include multiple sense amplifiers SA321-SA324. The bit lines on the left and right sides of the same SA share the same SA. For example, taking SA11 as an example, the bit lines BL01 and BL11 on the left and right sides of SA11 share SA11.

[0072] After introducing the chip structure, the chip repair method involved in the embodiment of the present disclosure will be described next.

[0073] Figure 3 FIG. 1 is a logic diagram of a chip repair method provided by an embodiment of the present disclosure. Figure 3 As shown, a spare circuit architecture may be used to repair the memory block 21 of the chip in a row repair or column repair manner. The spare circuit architecture may include spare rows 22 and spare columns 23 .

[0074] For example, when the memory block 21 needs to be repaired, the spare row 22 can be used to replace the faulty row in the memory block 21 ( Figure 3 For another example, when a column repair is required for the storage block 22, the spare column 23 may be used to replace the faulty column in the storage block 21 ( Figure 3 ). Optionally, in order to reduce the repair cost, when a single storage unit fails, a spare storage unit may be used to replace the single failed storage unit in the storage block 21.

[0075] The inventors have found through research that SA plays a very important role in the chip. In the test process such as CP test, the chip to be tested can be used as the device under test (DUT), and the test items can be executed for the DUT, wherein the test items can include test items for SA abnormalities. In this type of test items, for the DUT with more serious SA abnormalities, conventional repair methods can be used to repair it. However, for a DUT in a marginal state, that is, a DUT whose SA function is sometimes good and sometimes bad, for example, a DUT that sometimes leaks and sometimes does not leak, after conventional repair, the probability of failure during the later stage of testing or use is very high, which not only wastes repair resources (redundancy), but also reduces the chip yield.

[0076] For example, Figure 4 FIG. 1 is a schematic diagram showing an exemplary chip repair method provided by an embodiment of the present disclosure. Figure 4 As shown in Figure 1, when the SA abnormality problem is not serious, it may cause one or more storage units connected to the SA to fail, such as Figure 4 Fault storage units B1-B3 in.

[0077] If the original fault repair method is used to repair it, for example, the row R1 where the faulty storage unit B2 is located and the row R2 where the faulty storage unit R3 is located can be repaired according to the conventional repair method. This repair method cannot effectively solve the SA abnormality problem. In the later stage test or customer use process, as the performance deteriorates, the probability of problems is very high.

[0078] Optionally, the memory cell columns A1-A5 can be repaired in rows according to the original fault repair method. For example, when the SA abnormality is serious, multiple memory cells on the bit line connected to the SA may fail, such as multiple memory cells on the memory cell column A1, which can be repaired in columns.

[0079] Based on this, the embodiments of the present disclosure provide a chip repair method, device, equipment and medium, which can be applied to chip repair scenarios. Exemplarily, it can be applied to chip repair scenarios of CP testing. Alternatively, it can be applied to chip repair scenarios of FT testing. Through the embodiments of the present disclosure, by adding the first storage cell column and the second storage cell column to the fault column to be repaired, when the column to be repaired is repaired, the first storage cell column and the second storage cell column that have not failed can be pre-repaired in advance, thereby avoiding the possibility of abnormalities in the first storage cell column and the second storage cell column due to abnormalities in the sensing amplifier during post-testing and use, thereby improving the chip yield.

[0080] For example, Figure 5 A schematic diagram of another exemplary chip repair method provided by an embodiment of the present disclosure is shown. Figure 5 and Figure 4 The difference is that, when the repair method of the embodiment of the present disclosure is used to repair the storage block 20-storage block 22, for the faulty storage cell B1, the storage cell column A4 where it is located can be determined as the first storage cell column, and the storage cell column C1 and storage cell column C6 that are adjacent to the storage cell column A4 on the left and right in the column direction can be determined as the second storage cell column. For the faulty storage cell B2, the storage cell column C3 where it is located can be determined as the first storage cell column, and the storage cell column C2 and storage cell column C4 that are adjacent to the storage cell column C3 on the left and right in the column direction can be determined as the second storage cell column. And for the faulty storage cell B3, the storage cell column C5 where it is located can be determined as the first storage cell column (if there are other storage blocks on the right side of the storage block 22, the storage cell column adjacent to the storage cell column C5 on the right side in the column direction can also be determined as the second storage cell column). Therefore, when the storage cells B1-B3 fail due to SA abnormality (such as SA leakage, etc.), the determined first storage cell columns and second storage cell columns can be pre-repaired in advance. Before the storage cells on the first storage cell column and the second storage cell column fail due to the gradual degradation of SA performance during chip use, the failures can be repaired in advance, thereby improving the chip yield.

[0081] After preliminarily introducing the technical solution of the embodiment of the present disclosure through the above content, the technical solution provided by the embodiment of the present disclosure will be specifically described in conjunction with the drawings and embodiments.

[0082] First, a chip repair method is provided in an embodiment of the present disclosure. The method can be executed by any electronic device capable of detecting a faulty memory column, such as a test machine.

[0083] Figure 6 A schematic diagram of a chip repair method provided by an embodiment of the present disclosure is shown. Figure 6 As shown, the chip repair method provided in the embodiment of the present disclosure includes the following steps S610 to S630.

[0084] S610, determining target failed storage cells in a plurality of storage blocks of a chip.

[0085] Before introducing the specific implementation of S610, the terms involved in S610 are explained first.

[0086] For a chip, it may refer to a chip that needs to be repaired.

[0087] For a storage block, it may be a storage block that needs to be repaired, for example, Figure 5 The storage block 20-storage block 22 in the embodiment. The specific content of the storage block can refer to the relevant description of the above part of the embodiment of the present disclosure, which will not be repeated here.

[0088] The target faulty storage unit may refer to a faulty storage unit that needs to be repaired.

[0089] In some embodiments, the target faulty storage unit may be a faulty storage unit that satisfies a preset pre-repair determination condition, wherein the preset pre-repair determination condition may refer to a condition that needs to be satisfied when pre-repairing the faulty storage unit is required.

[0090] In one embodiment, the preset pre-repair determination condition may include determination condition 1.

[0091] Judgment condition 1: the number of faulty storage units in the storage unit column to which the faulty storage unit belongs reaches a preset number condition. The preset number condition may refer to a number condition that needs to be met when the faulty storage unit needs to be pre-repaired. Exemplarily, the preset number condition may be determined based on the characteristics of the number of faulty storage units in the storage unit column associated with the SA with a less severe abnormality.

[0092] In one example, the preset quantity condition may include that the number of failed storage units is equal to a preset quantity threshold. Exemplarily, the preset quantity threshold may be 1. It should be noted that the preset quantity requirement may also be set to other values ​​according to actual chip requirements and specific chip scenarios, and there is no specific limitation on this.

[0093] In another example, the preset quantity requirement may include that the number of failed storage units is within a preset quantity range. For example, the quantity range [1,2) (i.e., a quantity range greater than or equal to 1 and less than 2). It should be noted that the preset quantity range may be set to other quantity ranges according to actual chip needs and specific chip requirements, and no specific limitation is made to this.

[0094] In another embodiment, in order to pre-repair potential SA abnormality problems, the target fault storage unit may refer to a fault storage unit that fails due to SA abnormality. Exemplarily, the target fault storage unit may be a fault storage unit obtained by testing when performing SA fault test. Among them, the SA fault test may be a test for detecting whether SA functions abnormally during the chip test phase, such as SA leakage test, etc., which can be determined according to the specific chip test scenario and actual chip test requirements, and no specific limitation is made to this.

[0095] Accordingly, the preset pre-repair determination condition may include determination condition 2.

[0096] Judgment condition 2: the faulty storage unit is a faulty storage unit detected during the SA fault test.

[0097] In another embodiment, the preset pre-repair determination condition may further include determination condition 1 and determination condition 2. Exemplarily, on the basis that the preset pre-repair determination condition includes determination condition 1 and determination condition 2, the target faulty storage unit needs to further meet determination condition 2 when the determination condition 1 is met.

[0098] It should be noted that other preset pre-repair determination conditions may also be set according to actual chip conditions, and no specific limitation is made to this.

[0099] After introducing the above terms, the specific implementation of S610 is described next.

[0100] In some embodiments, S610 may include step D1 and step D2.

[0101] Step D1, determining faulty storage cells in a plurality of storage blocks.

[0102] The faulty storage unit may be a faulty storage unit detected during fault detection.

[0103] Step D2, determining the faulty storage unit that meets the preset pre-repair determination condition as the target faulty storage unit. The preset pre-repair determination condition can be referred to the relevant description of the above part of the embodiment of the present disclosure, which will not be described in detail.

[0104] Through the above steps D1 and D2, a target faulty storage unit that meets the preset pre-repair judgment condition can be selected from the faulty storage units to execute the chip repair method provided by the embodiment of the present disclosure, thereby ensuring the repair accuracy and avoiding the waste of repair resources (redundancy) resources.

[0105] In one embodiment, step D2 may include step D21 and step D22.

[0106] Step D21, for each faulty memory cell, detect the number of faulty memory cells in the memory cell column to which each faulty memory cell belongs. Exemplarily, the number of faulty memory cells may refer to the number of faulty memory cells in each faulty memory cell column. For example, the number of faulty memory cells may be the number of faulty memory cells on the bit line connected to each faulty memory cell.

[0107] For example, see Figure 4 , Figure 4 Each four-pointed star in represents a faulty memory cell. The number of faulty memory cells in the memory cell column A1 is 5. The number of faulty memory cells in the memory cell column A4 is 1.

[0108] Step D22, when the detected number of faulty storage units reaches a preset number condition, each faulty storage unit is determined as a target faulty storage unit. The preset number condition can be found in the relevant description of the above part of the embodiment of the present disclosure, which will not be described in detail.

[0109] In one example, if the preset number condition is that the number of failed storage units is less than 2, Figure 4 The faulty storage units B1-B3 in are determined as target faulty storage units.

[0110] Through the above steps D21 and D22, the target faulty storage unit that meets the preset quantity condition can be selected from the faulty storage units to execute the chip repair method provided by the embodiment of the present disclosure, which can improve the repair accuracy. Further, when performing fault detection, for SAs with less severe abnormal problems, only a few storage units in the corresponding storage unit column may have faults. Therefore, when the preset quantity condition is that the target faulty storage unit is less than a specified value, for SAs with less severe abnormal problems, when no fault is detected in the first storage unit column and the second storage unit column related to the SA, it can also be accurately pre-repaired, thereby improving the repair accuracy.

[0111] In another embodiment, step D2 may include step D23 and step D24.

[0112] Step D23 , for each faulty storage unit, detecting whether each faulty storage unit is the first faulty storage unit detected during the SA test.

[0113] The SA test may be a fault test whose test result is affected by whether SA is abnormal. For example, the SA test may be an SA instability test, such as a fault test capable of detecting SA leakage test, etc., which is not specifically limited.

[0114] Step D24, in the case that each faulty storage unit is a first faulty storage unit, each faulty storage unit is determined as a target faulty storage unit.

[0115] In one example, in order to avoid wasting redundancy resources, a first faulty storage unit whose number of faulty storage units on its storage unit column reaches a preset number condition may be determined as a target faulty storage unit.

[0116] Accordingly, in this case, step D24 may specifically include: when each faulty storage unit is a first faulty storage unit, detecting the number of faulty storage units in the storage unit column to which each faulty storage unit belongs, and determining each faulty storage unit that reaches a preset number condition as a target faulty storage unit.

[0117] For example, see Figure 4 ,like Figure 4 The four-pointed star in the middle shows the first faulty storage unit, and if the preset quantity condition is that the number of faulty storage units on the corresponding storage unit column is less than 2, the faulty storage units B1-B3 can be used as target faulty storage units. In another example, in order to improve the repair accuracy, each first faulty storage unit can be used as a target faulty storage unit.

[0118] For example, see Figure 4 ,like Figure 4 The four-pointed star in the figure shows the first fault storage unit. Figure 4 All the fault storage units corresponding to the four-pointed stars are used as target fault storage units.

[0119] Through the above-mentioned steps D23 and D24, for the first faulty storage unit detected during the SA test, the corresponding SA often has an abnormal probability. By determining the target faulty storage unit in the first faulty storage unit detected during the SA test, the storage column related to the SA with an abnormal probability can be accurately identified, and the accurately identified storage column can be pre-repaired in advance, thereby avoiding the occurrence of storage column failures caused by the gradual degradation of performance of the SA during the later stage testing and use, further improving the chip yield, and avoiding the unreasonable use of repair resources.

[0120] It should be noted that step D2 may also be implemented in other specific implementations according to preset pre-repair determination conditions, which is not limited thereto.

[0121] In some other embodiments, in S610, multiple faulty storage units may be used as target faulty storage units for fault repair.

[0122] It should be noted that, other methods may be selected to determine the target fault storage unit for fault repair according to actual repair requirements and specific repair scenarios, and there is no specific limitation on this.

[0123] After introducing S610, S620 will be described next.

[0124] S620, determining a first storage cell column to which the target failed storage cell belongs, and determining a second storage cell column adjacent to the first storage cell column in a column direction.

[0125] For the first memory cell column, it may include a plurality of memory cells on the first bit line to which the target failed memory cell is connected. Figure 5 For example, if the faulty storage cell B2 is the target faulty storage cell, the storage cell column C3 may be used as the first storage cell column.

[0126] The second memory cell column may refer to a memory cell column connected to the first memory cell column in the column direction. Exemplarily, the second memory cell column may include memory cells on a second bit line, wherein the second bit line is an adjacent bit line to the first bit line in the column direction.

[0127] Exemplarily, if the first storage cell column is located in the target storage block, the storage cell column in the adjacent storage block of the target storage block and located in the same column as the first storage cell column is the second storage cell column. Figure 5 For example, if the last memory cell column C3 in the memory block 1 is used as the first memory cell column, the last memory cell column C2 in the memory block 0 and the last memory cell column C2 in the memory block 4 may be used as the second memory cell column.

[0128] In some embodiments, the second memory cell column may be a memory cell column on one side of the first memory cell column in the column direction, or memory cell columns on the left and right sides of the first memory cell column in the column direction.

[0129] In one embodiment, S820 may include step E1 and step E2.

[0130] Step E1, determining the failure type of the target failed storage unit.

[0131] Step E2: selecting a second storage cell column from adjacent storage cell columns of the first storage cell column based on the fault type.

[0132] In one example, if the fault type is a first preset fault type, the memory cell columns on the left and right sides in the column direction may be determined as second memory cell columns. For example, the first preset fault type may include an SA leakage fault.

[0133] In another example, if the fault type is a second preset fault type, the memory cell column on one side in the column direction may be determined as a second memory cell column.

[0134] Through the above steps E1 and E2, for the first preset fault type such as SA leakage, it is impossible to determine which side of the SA causes the fault of the target faulty storage unit. Since the first preset fault type may affect the storage units on the bit lines on both sides of the SA (the storage unit columns on both sides of the SA), in order to improve the repair accuracy, the storage units on the bit lines on both sides of the SA can be determined as the second storage unit column for pre-repair. For the second preset fault type, the fault is often caused by one side of the SA. In order to avoid wasting repair resources, the storage unit column on one side of the first storage unit column can be determined as the second storage unit column for pre-repair based on the preset rule.

[0135] In one embodiment, S820 may include step E3 and step E4.

[0136] Step E3, determining the corresponding repair method of the adjacent storage unit column of the first storage unit column in the original fault repair solution.

[0137] Step E4, when the repair method is row repair or single storage unit repair, the adjacent storage unit column is used as the second storage unit column. Accordingly, for the adjacent storage unit column whose corresponding repair method in the original fault repair scheme is column repair, it may not be used as the second storage unit column.

[0138] Through this embodiment, it is possible to avoid repeatedly adding the same storage unit column to the storage column to be repaired, thereby avoiding repeated repair of the storage unit column and avoiding waste of repair resources.

[0139] S630, adding the first storage cell column and the second storage cell column to the fault column to be repaired, so as to pre-repair the first storage cell column and the second storage cell column when the fault column to be repaired is repaired.

[0140] In some embodiments, S630 may include step F1, writing the position information of the first storage unit column and the position information of the second storage unit column into the file to be repaired, so as to perform fault repair based on the file to be repaired.

[0141] Exemplarily, the position information of the first storage cell column and / or the position information of the second storage cell column may include the column address of the storage cell column and the storage block information of the storage block to which the storage cell column belongs. For example, the file to be repaired may be written in the form of line[sec][Y]. Wherein, line identifies the fault column. [sec] is the storage block information of the storage block to which it belongs, such as a storage block serial number. [Y] identifies the column address of the storage cell column.

[0142] It should be noted that the location information of the storage unit column may also be other information that can uniquely identify the storage unit column in the chip, and there is no specific limitation on this.

[0143] Through the above-mentioned step F1, the position information of the first storage cell column and the position information of the second storage cell column can be written into the file to be repaired, and the first storage cell column and the second storage cell column can be added as fault columns to be repaired. This can facilitate accurate finding of the first storage cell column and the second storage cell column in multiple storage blocks based on the file to be repaired during fault repair, thereby improving the accuracy and orderliness of the repair process.

[0144] The chip repair method provided by the embodiment of the present disclosure can determine the first storage cell column to which the target faulty storage cell belongs, and determine the second storage cell column adjacent to the first storage cell column in the column direction. Since the fault of the target faulty storage cell may be caused by an abnormality in the sensing amplifier, by adding the first storage cell column and the second storage cell column to the faulty column to be repaired, the first storage cell column and the second storage cell column that have not failed can be pre-repaired in advance when the column repair is performed on the faulty column to be repaired, thereby avoiding the possibility that the first storage cell column and the second storage cell column will be abnormal during the later stage test and use due to the abnormality in the sensing amplifier, thereby improving the chip yield.

[0145] In some embodiments, after S630 , the chip repair method may further include step G1 .

[0146] Step G1: During the column repair process, the first storage unit column and the second storage unit column may be replaced by a spare column.

[0147] It should be noted that the same test machine can be used to perform column repair, or different test machines can be used to perform column repair, and there is no specific limitation on this.

[0148] In some embodiments, after S620, the chip repair method may further include: step G2 and step G3.

[0149] Step G2, in the column direction, determine the adjacent sense amplifiers of the first memory cell column. Figure 2 For example, taking the memory cell column corresponding to the bit line BL11 as the first memory cell column, the adjacent sense amplifiers of the first memory cell column may include the sense amplifier SA11 and the sense amplifier SA21 adjacent to the bit line BL11.

[0150] Step G3, adding the adjacent sense amplifier to the fault column to be repaired, so as to pre-repair the adjacent sense amplifier when repairing the fault column to be repaired.

[0151] Continuing with the previous example, the sense amplifier SA11 and the sense amplifier SA21 may be added to the fault column to be repaired.

[0152] Illustratively, during the repair process, a spare SA may be used to replace an adjacent sense amplifier.

[0153] Through the above steps G2 and G3, since the adjacent SA of the first storage unit column may cause the target faulty storage unit to fail, the adjacent SA can be pre-repaired by adding the adjacent SA to the fault column to be repaired. No matter which adjacent SA is abnormal, the abnormality can be pre-repaired, thereby further improving the chip yield.

[0154] Figure 7 The flowchart of another chip repair method provided by the embodiment of the present disclosure is shown. The embodiment of the present disclosure is optimized on the basis of the above embodiment, and the embodiment of the present disclosure can be combined with various optional solutions in one or more of the above embodiments.

[0155] like Figure 7 As shown, the chip repair method includes the following steps S710 to S760.

[0156] S710, determining failed storage units in a plurality of storage blocks.

[0157] Among them, S710 is similar to step D1, and the specific content of step D1 can be referred to, which will not be repeated here.

[0158] S720 , for each faulty memory cell, detecting whether each faulty memory cell is a first faulty memory cell detected during a sense amplifier test.

[0159] Among them, S720 is similar to step D23, and the specific content of step D23 can be referred to, which will not be repeated here.

[0160] S730: When each faulty storage unit is a first faulty storage unit, determine each faulty storage unit as a target faulty storage unit.

[0161] Among them, S730 is similar to step D24, and the specific content of step D24 can be referred to, which will not be repeated here.

[0162] S740, determining a first storage cell column to which the target failed storage cell belongs, and determining a second storage cell column adjacent to the first storage cell column in a column direction.

[0163] Among them, S740 is similar to S620, and the specific content of S620 can be referred to, which will not be repeated here.

[0164] S750: Add the first storage cell column and the second storage cell column to the fault column to be repaired, so as to perform column repair on the first storage cell column and the second storage cell column when repairing the fault column to be repaired.

[0165] Among them, S750 is similar to S630, and the specific content of S630 can be referred to, which will not be repeated here.

[0166] S760: When each faulty storage unit is not the first faulty storage unit, perform fault repair on each faulty storage unit according to an original fault repair solution.

[0167] For example, the original fault repair scheme may be a conventional repair rule. For example, it may be repaired according to the number of repair resources and repair algorithm pre-specified by the designer. For example, the redundancy analysis (RA) algorithm

[0168] The chip repair method provided by the embodiment of the present disclosure can determine the first storage cell column to which the target faulty storage cell belongs, and determine the second storage cell column adjacent to the first storage cell column in the column direction. Since the fault of the target faulty storage cell may be caused by an abnormality in the sensing amplifier, by adding the first storage cell column and the second storage cell column to the faulty column to be repaired, the first storage cell column and the second storage cell column that have not failed can be pre-repaired in advance when the column repair is performed on the faulty column to be repaired, thereby avoiding the possibility that the first storage cell column and the second storage cell column will be abnormal during the later stage test and use due to the abnormality in the sensing amplifier, thereby improving the chip yield.

[0169] Furthermore, through the embodiments of the present disclosure, the original fault repair solution and the pre-repair solution provided by the embodiments of the present disclosure can be combined to flexibly and comprehensively repair chip faults, thereby improving the chip yield.

[0170] In order to facilitate understanding of the technical solution provided by the embodiments of the present disclosure, an example is given below to illustrate it.

[0171] In one example, Figure 8 A schematic flow chart of an exemplary chip repair method provided by an embodiment of the present disclosure is shown.

[0172] like Figure 8 As shown, the chip repair method may include the following steps S801 to S818.

[0173] S801, obtaining information of a faulty storage unit of the current DUT. Exemplarily, address information of the faulty storage unit may be obtained.

[0174] Exemplarily, the failed storage unit may be a single bit failure (Single Bit fail).

[0175] S802, determine whether the number of faulty storage units of the current DUT is greater than 0. If the determination result is yes, continue to execute S803, if the determination result is no, execute S818.

[0176] S803, obtaining a faulty storage unit with a serial number of N.

[0177] S804, determine whether the faulty storage unit with serial number N is detected by the SA fault test. If the determination result is yes, continue to execute S805. If the determination result is no, decrement N and return to step S802 to determine whether other faulty storage units of the current DUT are detected by the SA fault test.

[0178] S805: Add the faulty storage unit with serial number N to the file to be repaired.

[0179] Exemplarily, the faulty storage unit may be stored in the to-be-repaired file SAF[Y][X] in the format of (column address, row address), where Y represents the column address of the faulty storage unit and X represents the row address of the faulty storage unit.

[0180] Exemplarily, failed storage cells belonging to the same storage cell column may be grouped together.

[0181] S806, determine whether N is greater than 0. If the result of the determination is yes, it indicates that the determination of whether the faulty storage unit of the current DUT is detected by the SA fault test has not been completed, and N is decremented and the process returns to step S802 to continue to determine whether other faulty storage units of the current DUT are detected by the SA fault test. If the result of the determination is no, it indicates that the determination of whether all faulty storage units of the current DUT are detected by the SA fault test has been completed, and S807 is continued.

[0182] S807, start executing the pre-repair algorithm provided by the embodiment of the present disclosure.

[0183] S808: Obtain the Mth group of information to be repaired.

[0184] Exemplarily, the information of the faulty storage units belonging to the same storage unit column can be stored in a group of information to be repaired. Accordingly, the column addresses of the faulty storage units in the same group of information to be repaired are the same. For example, the first group of information to be repaired includes: the address (Y1, X1) of the faulty storage unit 1, the address (Y1, X2) of the faulty storage unit 2, and the address (Y1, X6) of the faulty storage unit 3. The second group of information to be repaired includes: the address (Y2, X1) of the faulty storage unit 4.

[0185] S809, determine whether the number of faulty storage units in the storage unit column corresponding to the Mth group of information to be repaired has reached a preset number condition. If the judgment result is yes, continue to execute S810. If the judgment result is no, decrement M and return to step S808 to continue to determine whether the number of faulty storage units in the storage unit column corresponding to other groups of information to be repaired has reached a preset number condition. Among them, the preset number condition can refer to the relevant description of the above part of the embodiment of the present disclosure, which will not be repeated here.

[0186] The number of faulty storage units in S809 may refer to the number of faulty storage units detected by the SA fault test in the storage unit column. Exemplarily, the number of faulty storage units may be the number of information of faulty storage units in the Mth group of information to be repaired. Continuing with the previous example, the number of faulty storage units in the storage unit column corresponding to the first group of information to be repaired is 3, and the number of faulty storage units in the storage unit column corresponding to the second group of information to be repaired is 1.

[0187] S810, adding the storage unit column corresponding to the Mth group of information to be repaired as the first storage unit column to the fault column to be repaired, and adding the storage unit column adjacent to the storage unit column corresponding to the Mth group of information to be repaired in the column direction as the second storage unit column to the fault column to be repaired. Optionally, the SAs on the left and right sides of the storage unit column corresponding to the Mth group of information to be repaired may also be added to the fault column to be repaired.

[0188] Exemplarily, the first storage cell column may be represented as “line[sec0][Y]”, and the second storage cell column may be represented as “line[sec0±1][Y]”, where [sec0] represents the serial number of the storage block to which the first storage cell column belongs.

[0189] In a specific example, continuing with the previous example, when the preset quantity condition is that the number of faulty storage cells is less than 2, the storage cell column corresponding to the second group of information to be repaired (the number of faulty storage cells is 1) can be added to the fault column to be repaired. If the storage cell column corresponding to the second group of information to be repaired belongs to storage block 2, and the column address is Y2, then the storage cell column with the column address Y2 in storage block 1 and storage block 3 can be added to the fault column to be repaired. For example, it can be expressed as adding line[sec2][Y2], line[sec1][Y2], and line[sec3][Y2].

[0190] S811, determine whether M is greater than 0. If the determination result is yes, it means that the traversal process of all groups of information to be repaired has not been completed, then M can be decremented and the process returns to step S808. If the determination result is no, it means that the traversal process of all groups of information to be repaired has been completed, and S812 is continued.

[0191] S812, repairing a single faulty storage unit. For example, the faulty storage unit that has not been repaired by the line group may be repaired.

[0192] In one example, a single faulty storage unit may be repaired according to an existing fault repair method, such as row repair, column repair or storage unit repair, without specific limitation.

[0193] S813, determine whether the single faulty storage unit is repairable, if the determination result is yes, continue to execute S814; if the determination result is no, continue to execute S818.

[0194] S814, determine whether all single faulty storage units have been repaired. If the determination result is no, return to step S812 to continue repairing. If the determination result is yes, continue to execute S815.

[0195] S815, repair the fault line group (line fail). The fault line group may include a fault storage column. Optionally, the fault line group may also include a fault storage row.

[0196] S816, determine whether the faulty line group is repairable. If the determination result is yes, continue to execute S817; if the determination result is no, continue to execute S818.

[0197] S817, determine whether the repair of all DUTs is completed. If the judgment result is yes, it means that the repair of all chips to be repaired has been completed, and the repair can be ended; if the judgment result is no, it means that there are still chips to be repaired that have not been repaired, and the next chip of the current DUT can be used as the new current DUT and return to step S818.

[0198] Based on the same inventive concept, a chip repair device is also provided in the embodiments of the present disclosure, such as the following embodiments.

[0199] Fig. 9 A schematic diagram of a chip repair device provided by an embodiment of the present disclosure is shown. Fig. 9 As shown, the chip repairing device 900 includes: a faulty storage unit determining module 910, a storage unit column determining module 920 and a to-be-repaired faulty column determining module 930.

[0200] A faulty storage unit determination module 910 is used to determine a target faulty storage unit in a plurality of storage blocks;

[0201] A storage cell column determination module 920, configured to determine a first storage cell column to which a target faulty storage cell belongs, and to determine a second storage cell column adjacent to the first storage cell column in a column direction;

[0202] The module 930 for determining the faulty column to be repaired is used to add the first storage cell column and the second storage cell column to the faulty column to be repaired, so as to pre-repair the first storage cell column and the second storage cell column when the faulty column to be repaired is repaired.

[0203] In one embodiment, the fault storage unit determination module 910 includes: a first fault determination unit and a second fault determination unit.

[0204] The first fault determination unit is used to determine faulty storage cells in the plurality of storage blocks.

[0205] The second fault determination unit is used to determine a faulty storage unit that meets a preset pre-repair determination condition as a target faulty storage unit.

[0206] In one embodiment, the preset pre-repair determination condition includes: the number of faulty storage cells on the corresponding storage cell column reaches a preset number condition. The second fault determination unit includes: a first number detection subunit and a first fault determination subunit.

[0207] The first quantity detection subunit is used for detecting, for each faulty storage unit, the quantity of the faulty storage units in the storage unit column to which each faulty storage unit belongs.

[0208] The first fault determination subunit is used to determine each faulty storage unit as a target faulty storage unit when the number of faulty storage units detected reaches a preset number condition.

[0209] In one embodiment, the preset pre-repair determination condition further includes that the faulty storage unit is detected during a sense amplifier test. The second fault determination unit includes: a first quantity detection subunit and a first fault determination subunit.

[0210] A first fault detection subunit, for detecting, for each faulty storage unit, whether each faulty storage unit is a first faulty storage unit detected during a sense amplifier test;

[0211] The second fault determination subunit is used to determine each fault storage unit as a target fault storage unit when each fault storage unit is a first fault storage unit.

[0212] In one embodiment, the second fault determination unit further includes a first repair subunit.

[0213] The first repair subunit is used to repair each faulty storage unit according to an original fault repair scheme when each faulty storage unit is not the first faulty storage unit.

[0214] In one embodiment, the chip repair apparatus 900 further includes an adjacent sense amplifier determination module.

[0215] The adjacent sense amplifier determination module is used to determine adjacent sense amplifiers of the first memory cell column in the column direction.

[0216] Furthermore, the to-be-repaired fault column determining module 930 is further configured to add adjacent sense amplifiers to the to-be-repaired fault column, so as to pre-repair the adjacent sense amplifiers when the to-be-repaired fault column is column-repaired.

[0217] In one embodiment, the module 930 for determining the faulty column to be repaired includes a position information writing unit.

[0218] The position information writing unit is used to write the position information of the first storage unit column and the position information of the second storage unit column into the file to be repaired, so as to perform fault repair based on the file to be repaired.

[0219] The chip repair device provided by the embodiment of the present disclosure can determine the first storage cell column to which the target faulty storage cell belongs, and determine the second storage cell column adjacent to the first storage cell column in the column direction. Since the fault of the target faulty storage cell may be caused by an abnormality in the sensing amplifier, by adding the first storage cell column and the second storage cell column to the faulty column to be repaired, the first storage cell column and the second storage cell column that have not failed can be pre-repaired in advance when the column repair is performed on the faulty column to be repaired, thereby avoiding the possibility that the first storage cell column and the second storage cell column will be abnormal during the later stage test and use due to the abnormality in the sensing amplifier, thereby improving the chip yield.

[0220] It should be noted that Fig. 9 The chip repair device 900 shown can perform Figures 6 to 8 The various steps in the method embodiment shown in the figure are implemented Figures 6 to 8 The various processes and effects in the method embodiment shown are not described in detail here.

[0221] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods or program products. Therefore, various aspects of the present disclosure may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as "circuits", "modules" or "systems".

[0222] Refer to the following Fig.10 The electronic device 1000 according to this embodiment of the present disclosure is described. Fig.10 The electronic device 1000 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0223] like Fig.10 As shown, the electronic device 1000 is in the form of a general computing device. The components of the electronic device 1000 may include but are not limited to: the at least one processing unit 1010, the at least one storage unit 1020, and a bus 1030 connecting different system components (including the storage unit 1020 and the processing unit 1010).

[0224] The storage unit stores program codes, which can be executed by the processing unit 1010, so that the processing unit 1010 executes the steps described in the above “exemplary method” section of this specification according to various exemplary embodiments of the present disclosure.

[0225] The storage unit 1020 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 10201 and / or a cache storage unit 10202 , and may further include a read-only storage unit (ROM) 10203 .

[0226] The storage unit 1020 may also include a program / utility 10204 having a set (at least one) of program modules 10205, such program modules 10205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0227] Bus 1030 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0228] The electronic device 1000 may also communicate with one or more external devices 1040 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device 1000, and / or any device that enables the electronic device 1000 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed through an input / output (I / O) interface 1050.

[0229] Furthermore, the electronic device 1000 can also communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN) and / or a public network, such as the Internet) through the network adapter 1060 .

[0230] like Fig.10 As shown, the network adapter 1060 communicates with other modules of the electronic device 1000 via the bus 1030 .

[0231] It should be understood that although not shown in the figures, other hardware and / or software modules may be used in conjunction with the electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0232] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0233] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is further provided, which may be a readable signal medium or a readable storage medium. Fig.11 A schematic diagram of a computer-readable storage medium provided by an embodiment of the present disclosure is shown. Fig.11 As shown, the computer-readable storage medium 1100 stores a program product capable of implementing the above method of the present disclosure.

[0234] In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of various exemplary implementations of the present disclosure described in the above “Exemplary Method” section of this specification.

[0235] More specific examples of computer-readable storage media in the present disclosure may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0236] In the present disclosure, a computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, wherein a readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0237] Readable signal media may also be any readable media other than readable storage media that can send, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0238] In some examples, the program code contained on a computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0239] In specific implementations, program codes for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages, such as Java, C++, etc., and conventional procedural programming languages, such as "C" or similar programming languages. The program codes may be executed entirely on the user computing device, partially on the user computing device, as a separate software package, partially on the user computing device, partially on a remote computing device, or entirely on a remote computing device or server.

[0240] Where a remote computing device is involved, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0241] The embodiment of the present disclosure provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. The processor of the computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the chip repair method provided in various optional ways in any embodiment of the present disclosure.

[0242] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0243] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0244] Through the description of the above implementation modes, it is easy for those skilled in the art to understand that the example implementation modes described here can be implemented by software, or by combining software with necessary hardware.

[0245] Therefore, the technical solution according to the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiment of the present disclosure.

[0246] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein.

[0247] The present disclosure is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A chip repair method, characterized in that: The chip includes a plurality of memory blocks, each memory block includes memory cells arranged in an array, wherein a memory cell column in each memory block corresponds to a bit line; the method includes: determining a target failed storage unit among the plurality of storage blocks; Determine a first storage cell column to which the target failed storage cell belongs, and determine a second storage cell column adjacent to the first storage cell column in a column direction; The first storage cell column and the second storage cell column are added to a fault column to be repaired, so that the first storage cell column and the second storage cell column are pre-repaired when the fault column to be repaired is repaired.

2. The method according to claim 1, characterized in that The determining of a target failed storage unit in the plurality of storage blocks comprises: determining a failed memory cell in the plurality of memory blocks; A faulty storage unit that meets a preset pre-repair determination condition is determined as the target faulty storage unit.

3. The method according to claim 2, characterized in that The preset pre-repair determination condition includes: the number of failed storage units on the corresponding storage unit column reaches a preset number condition; The step of determining the faulty storage unit that meets the preset pre-repair determination condition as the target faulty storage unit comprises: For each faulty storage unit, detecting the number of faulty storage units in the storage unit column to which each faulty storage unit belongs; When the number of detected faulty storage units reaches a preset number condition, each of the faulty storage units is determined as the target faulty storage unit.

4. The method according to claim 2 or 3, characterized in that: The preset pre-repair determination condition also includes that the faulty storage unit is detected during the sensing amplifier test, The step of determining the faulty storage unit that meets the preset pre-repair determination condition as the target faulty storage unit further includes: For each faulty storage unit, detecting whether each faulty storage unit is a first faulty storage unit detected during a sense amplifier test; In a case where each of the failed storage units is the first failed storage unit, each of the failed storage units is determined as the target failed storage unit.

5. The method according to claim 4, characterized in that After detecting whether each of the faulty storage cells is a first faulty storage cell detected during the sense amplifier test, the method further includes: In the case that each of the faulty storage units is not the first faulty storage unit, each of the faulty storage units is repaired according to an original fault repair scheme.

6. The method according to claim 1, characterized in that The determining is located after the first storage unit column to which the target faulty storage unit belongs, the method further comprising: In the column direction, determining adjacent sense amplifiers of the first memory cell column; The adjacent sense amplifier is added to the fault column to be repaired, so as to pre-repair the adjacent sense amplifier when the fault column to be repaired is repaired.

7. The method according to claim 1, characterized in that The step of adding the first storage unit column and the second storage unit column to a fault column to be repaired comprises: The position information of the first storage unit column and the position information of the second storage unit column are written into a file to be repaired, so as to perform fault repair based on the file to be repaired.

8. A chip repair device, characterized in that: The chip includes a plurality of storage blocks, each storage block includes storage cells arranged in an array, wherein a storage cell column in each storage block corresponds to a bit line; the device includes: A faulty storage unit determination module, used to determine a target faulty storage unit in the plurality of storage blocks; a storage cell column determination module, configured to determine a first storage cell column to which the target faulty storage cell belongs, and to determine a second storage cell column adjacent to the first storage cell column in a column direction; The module for determining a fault column to be repaired is used to add the first storage unit column and the second storage unit column to the fault column to be repaired, so as to pre-repair the first storage unit column and the second storage unit column when the fault column to be repaired is repaired.

9. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the chip repair method according to any one of claims 1 to 7 by executing the executable instructions.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the chip repair method according to any one of claims 1 to 7 is implemented.

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