Failure mode analysis system and method applied to DRAM (Dynamic Random Access Memory)

Abstract

The invention discloses a failure mode analysis system and method applied to a DRAM (Dynamic Random Access Memory), and relates to the technical field of semiconductors. The method comprises the steps of obtaining test resources by preparing a test environment; carrying out a frequency reduction test on the DRAM chip and the circuit board with problems, observing whether the DRAM chip and the circuit board are improved or not, and if the DRAM chip and the circuit board are improved, carrying out adaptation through soft modification or hard modification; if the frequency reduction test is not improved, signal integrity measurement is carried out, possible signal problems are searched, and the compatibility problem is solved by adjusting time sequence parameters; performing a special configuration test, verifying the influence of the special configuration, and performing adaptation according to a test result; and carrying out compatibility adaptation through soft modification or hard modification according to the test result. According to the method, the reasons of the adaptation compatibility failure can be quickly and effectively found, the adaptation problem is improved, the verification analysis time occupied by anomaly analysis is greatly shortened, and the matching degree of compatibility adaptation of the DRAM chip and the SOC platform on the market is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a failure mode analysis system and method applied to DRAM. Background Art

[0002] With the rapid development of the semiconductor chip industry, more SOC platforms and manufacturers have sprung up. Due to the large number of SOC manufacturers on the market, it is impossible to verify the DRAM chips on every platform. Therefore, even if there is no problem with the DRAM chip itself, it is still possible that anomalies will occur on the platforms of some SOC manufacturers, especially for products of the same SOC. Coupled with the changes and designs in hardware design by different downstream customers, it will lead to compatibility problems between circuit boards and DRAM chips. At this time, it is no longer a single DRAM chip problem and circuit board problem, but a problem of the entire test environment.

[0003] When an abnormality occurs, we need to obtain the test environment and corresponding test resources. In addition to adapting to the abnormal DRAM chip, we also need to find the client to obtain the normal DRAM chip. Generally, the client will use the original chip when designing the circuit board, that is, the chips of major mainstream chip manufacturers, but such chips are often expensive, and the mainstream application scenarios themselves are not on this platform, which results in excess performance. For example, a 3200Mbps DRAM chip is mainly supplied to 3200Mbps computer motherboard manufacturers, but some mobile phone tablets or smart TV manufacturers now have products that run at only 1200Mbps or 1600Mbps. In this way, there is no need to use the original chip, but when they design the circuit board, they design it according to the standard of the original chip, which leads to abnormalities when replacing the chip.

[0004] As a separate independent system integration environment, the accuracy of the SOC platform is far from that of high-precision testers and machines, resulting in an increasing number of compatibility issues that cannot be screened out in advance through testers or machines. After compatibility issues occur on the client side, the anomaly often returns to the DRAM chip manufacturer and requires analysis by the manufacturer. At this time, the analysis is no longer simply for DRAM chips, but also for the entire test environment. General analysis methods are no longer fully applicable because compatibility only occurs in a fixed test environment and is completely normal on other platforms. Anomalies on a new platform require new analysis methods and testing methods. And through the analysis of differences and finding problem points, evaluation and improvement are carried out to complete the adaptation of the platform and DRAM chips. Summary of the invention

[0005] In order to overcome the above-mentioned shortcomings and deficiencies of the prior art, the first purpose of the present invention is to provide a failure mode analysis system applied to DRAM; the second purpose of the present invention is to provide a failure mode analysis method applied to DRAM.

[0006] The first object of the present invention adopts the following technical solution:

[0007] The failure mode analysis system applied to DRAM includes a test environment management module, a frequency reduction processing module, an SI analysis module, a special configuration test module, and a compatibility adaptation module;

[0008] Test environment management module: used to manage the test environment, including acquiring and configuring test resources, including DRAM chips, circuit boards, and system source code;

[0009] Frequency reduction processing module: used to adjust the DRAM operating rate by modifying the source code and implement frequency reduction testing to determine whether the problem is related to the operating speed;

[0010] SI analysis module: used to perform signal integrity measurements, identify signals that may cause problems, and resolve compatibility issues by adjusting timing parameters;

[0011] Special configuration test module: used to test the special configuration of DRAM and verify the impact of the special configuration;

[0012] Compatibility adaptation module: used to perform soft or hard modifications based on test results to achieve compatibility adaptation between DRAM chips and circuit boards.

[0013] Preferably, the test environment management module is also used to prepare at least two sets of test equipment and chips to cross-confirm that the problem is indeed the DRAM chip + circuit board.

[0014] Preferably, the frequency reduction processing module also includes a function for flashing the frequency-reduced system firmware / software into the DRAM chip+circuit board.

[0015] Preferably, the SI analysis module further comprises a function for performing a complete signal integrity measurement when the frequency reduction test fails.

[0016] Preferably, the special configuration test module further includes a function for setting different mode register configurations to verify the impact of the special configuration.

[0017] Preferably, the compatibility adaptation module also includes a function for determining specific steps of soft modification or hard modification according to the test results.

[0018] The second object of the present invention adopts the following technical solution:

[0019] The failure mode analysis method applied to DRAM is used to implement a failure mode analysis system applied to DRAM. The method flow is as follows:

[0020] Step 1: Obtain test resources and conduct preliminary verification;

[0021] S11, obtaining the test environment and related test resources provided by the client, the test resources including DRAM chips and system source code;

[0022] S12. Verify the problem. Use m sets of test equipment and chips to cross-verify and confirm that the compatibility failure problem is caused by the coordination between the DRAM chip and the circuit board.

[0023] S13, frequency reduction attempt, frequency reduction processing of the problematic DRAM chip and circuit board, by reducing the operating speed to relax the operating conditions of the DRAM chip to determine whether the problem is improved;

[0024] S14, timing relaxation: If the problem is improved after frequency reduction, relax the timing parameters one by one from the first timing parameter to determine which timing parameter causes the problem;

[0025] Step 2: Signal integrity measurement;

[0026] S21. If the problem still exists after frequency reduction, perform signal integrity measurement to check whether there is a margin problem during the power-on process.

[0027] S22. According to the SI measurement result, adjust the relevant timing in the source code to improve the abnormal situation. When the measurement finds that the Margin of the tCL parameter is less than the threshold, adjust the tCL value in the source code;

[0028] Step 3: Special configuration test;

[0029] S31, set different mode register configurations and test them using a high-precision tester;

[0030] S32, simulating the power-on process of the DRAM chip, and observing the difference between the normal DRAM and the abnormal DRAM;

[0031] S33, finding the difference area between the normal DRAM chip and the abnormal DRAM chip through Shmoo test, and adjusting the source code for debugging according to the difference conditions;

[0032] Step 4: Solve compatibility issues;

[0033] S41, software modification: solve the problem by modifying the parameters in the source code. If a problem is found in the setting of the tCL parameter, solve it by modifying the tCL value in the source code;

[0034] S42, hard modification: If the root cause of the problem lies in the physical design of the circuit board, redesign and adjust the circuit board. If it is found that the circuits on the circuit board are of unequal length, redesign the circuit layout;

[0035] S43. Incompatibility: If the circuit board hardware does not support it, resulting in complete incompatibility, it cannot be resolved by the above method.

[0036] Preferably, m is greater than or equal to 2.

[0037] Preferably, the first timing is the timing parameter that has the least impact on system performance.

[0038] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0039] 1. The present invention realizes the automation of the test process through modular design, reduces the need for manual intervention, and improves the test efficiency; through frequency reduction processing, SI analysis and special configuration testing, the system can quickly locate the specific cause of DRAM failure and speed up the problem solving.

[0040] 2. The present invention not only takes into account the basic operating rate adjustment, but also covers multiple aspects such as signal integrity and special configuration, ensuring the comprehensiveness of the test; through the collaborative work of multiple modules of the system, the cause of DRAM failure can be accurately diagnosed from different angles, thereby improving the accuracy of diagnosis.

[0041] 3. The present invention avoids unnecessary resource investment and reduces costs through effective testing strategies; the modular design enables the test results of each stage to be effectively utilized, avoiding the occurrence of repeated testing of the same content.

[0042] 4. The compatibility adapter module of the present invention can select a suitable solution based on the test results. Whether it is a modification at the software level or a design improvement at the hardware level, it can effectively improve the compatibility between DRAM and the circuit board; it can provide customized solutions based on specific test conditions, ensuring the stability and reliability of the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A module diagram of a failure mode analysis system for DRAM according to the present invention is shown;

[0045] Figure 2 The flowchart of the failure mode analysis method of the present invention applied to DRAM is shown. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] In addition, the described features, structures or characteristics may be combined in one or more example embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the example embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, steps, etc. may be adopted. In other cases, well-known structures, methods, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0048] Example 1

[0049] See also Figure 1 As shown, the failure mode analysis system applied to DRAM in this embodiment includes a test environment management module, a frequency reduction processing module, an SI analysis module, a special configuration test module and a compatibility adaptation module.

[0050] Test environment management module: used to manage the test environment, including acquiring and configuring test resources, including DRAM chips, circuit boards, and system source code; outputting the prepared test environment.

[0051] Down-clocking processing module: adjusts the DRAM operating rate by modifying the source code to achieve down-clocking and determine whether the problem is related to the operating speed; outputs the system firmware / software after down-clocking.

[0052] SI analysis module: used to perform signal integrity measurements, identify signals that may cause problems, and resolve compatibility issues by adjusting timing parameters; output SI measurement reports, including problem signals and their corresponding timing parameters.

[0053] Special configuration test module: used to test special configurations of DRAM (such as mode registers, ODT, etc.) and verify the impact of special configurations; output special configuration test reports, including comparison of test results under different configurations.

[0054] Compatibility adaptation module: used to perform soft or hard modifications based on test results to achieve compatibility adaptation between DRAM chips and circuit boards; output debugged and verified firmware / software update packages or circuit board design change suggestions.

[0055] The module interaction process is as follows:

[0056] The test environment management module prepares the test environment; uses the frequency reduction processing module to perform frequency reduction testing; if frequency reduction is ineffective, uses the SI analysis module to perform SI measurement; if necessary, uses the special configuration test module to perform special configuration testing; based on the test results, uses the compatibility adaptation module to perform corresponding software or hardware modifications.

[0057] The beneficial effects of this embodiment are as follows: the failure mode analysis system applied to DRAM can not only help quickly locate and solve problems through an automated, efficient and accurate testing process, but also significantly improve the quality and efficiency of testing, reduce costs, and enhance product compatibility and stability.

[0058] Example 2

[0059] See also Figure 2 As shown, the failure mode analysis method applied to DRAM in this embodiment has the following process:

[0060] Step 1: Obtain test resources and conduct preliminary verification.

[0061] S101. Acquire test resources.

[0062] Obtain the test environment and related test resources provided by the client, including DRAM chips and system source code, to facilitate development and debugging.

[0063] S102. Verification issues.

[0064] Use m sets of test equipment and DRAM chip samples to cross-validate and confirm that the problem is caused by the coordination between the DRAM chip and the circuit board; where m ≥ 2; the DRAM chip samples include suspected problematic chips and normal chips for comparison, which are from different batches or suppliers to rule out problems with specific batches or suppliers; and m identical circuit boards to enable test comparison on the same hardware platform.

[0065] Set up the test environment to ensure that all test equipment operates under the same or similar environmental conditions, including temperature, humidity, power supply stability, etc.

[0066] Each test device and circuit board is pre-tested to ensure that they function properly without the DRAM chips.

[0067] Cross-validation is performed by combining each circuit board with different DRAM chips and testing them on different test equipment. The performance of each combination in the test is recorded, including key data such as performance indicators, stability, and error rate.

[0068] If there is a DRAM chip that behaves abnormally when combined with all circuit boards, or there is a circuit board that behaves abnormally when combined with all DRAM chips, it can be preliminarily determined that the problem may be with the DRAM chip or circuit board;

[0069] If the anomaly only occurs in a specific DRAM chip and circuit board combination, it can be further confirmed that the problem is caused by the coordination of the DRAM chip and the circuit board.

[0070] S103: Attempt to reduce the frequency.

[0071] The DRAM chips and circuit boards that are abnormal after the processing in step S102 are down-clocked, and the operating conditions of the DRAM chips are relaxed by reducing the operating speed. For example, if the original speed of the DRAM chip used in the circuit board is 1600Mbps, a lower speed is selected as the down-clocking target according to the technical specifications of the DRAM chip and the support of the motherboard, such as 1333Mbps or 1200Mbps; after the system runs the new speed setting, sufficient testing is carried out (such as running memory testing software, performing high-load operations, etc.), and the operation of the DRAM chip after the frequency reduction is observed to determine whether the problem has been improved.

[0072] S104, timing relaxation.

[0073] If the problem is improved after frequency reduction, start from the first timing (tCL-tRCD-tRP-tRAS, etc.), relax them one by one to determine which timing parameter causes the problem, and then improve the value.

[0074] DRAM timing parameters, such as tCL (CAS latency), tRCD (RAS to CAS latency), tRP (precharge time), tRAS (active to precharge time), etc.

[0075] Start with timing parameters that have relatively little impact on system performance, such as tCL, and then gradually relax other parameters.

[0076] Implementation relaxation: In the BIOS setup or related hardware management software, increase the values ​​of the timing parameters one by one.

[0077] Testing and Observation: After each relaxation, system testing is required to observe whether the problem is further improved and to evaluate the impact on system performance.

[0078] Locating problematic parameters: By gradually relaxing and testing, the specific timing parameters that cause the problem can eventually be located.

[0079] Optimization and Adjustment: Make more detailed adjustments to the identified problem parameters to find the best balance between stability and performance.

[0080] Step 2: Signal integrity (SI) measurement.

[0081] S201, SI measurement.

[0082] If the problem still exists after frequency reduction, set measurement points on the key signal path between the DRAM chip and the circuit board, use an oscilloscope, network analyzer, etc. to capture the signal waveform during the power-on process and normal operation, perform signal integrity measurement, analyze the signal amplitude, phase and timing Margin (that is, the safe distance between the signal and the threshold), and determine whether there is a Margin problem during the power-on process. A margin that is too small may mean that the signal is prone to errors under extreme conditions (such as temperature changes and voltage fluctuations).

[0083] S202: Timing adjustment.

[0084] According to the SI measurement results, adjust the related timing in the source code to improve the abnormal situation. For example, if the measurement finds that the margin of the tCL parameter is small, it can be improved by adjusting the tCL value in the source code.

[0085] Identify the problem parameters: Based on the SI measurement results, determine which timing parameters (such as tCL, tRCD, tRP, tRAS, etc.) have a smaller margin and are the key factors causing the problem.

[0086] Modify the source code: Find the portion of the source code that controls these timing parameters (it could be a BIOS setup, firmware code, or some configuration in a driver) and modify it.

[0087] Adjust parameter values: According to the results of SI measurement and the technical specifications of the DRAM chip, appropriately increase the value of the problematic parameter (i.e. relax the timing) to improve the Margin.

[0088] Retest: After modifying the source code, re-perform SI measurements and system testing to verify whether the problem has been improved.

[0089] Optimization and verification: If the problem is improved, but the performance is too degraded, it may be necessary to further fine-tune the timing parameters to find the best balance between stability and performance. At the same time, ensure that all modifications are fully verified to ensure the stability and reliability of the system.

[0090] Step 3: Special configuration test.

[0091] S301, mode register configuration.

[0092] Set different mode register configurations (such as MR0, MR1, MR2) and test them with a high-precision tester.

[0093] Understanding the Mode Register:

[0094] DDR (such as DDR3, DDR4, etc.) DRAM chips usually contain multiple mode registers (such as MR0, MR1, MR2, etc.), each register controls different operating parameters, such as CAS latency (CL), burst length (BL), burst type (BurstType), etc.

[0095] Consult the data sheet of the DRAM chip to understand the specific functions and configurable parameters of each mode register.

[0096] To set different mode register configurations:

[0097] Use a high-precision tester (such as a signal generator, oscilloscope, etc.) or dedicated DRAM test equipment to program the DRAM chip and set different mode register configurations.

[0098] Make sure to change only one or a few parameters at a time to accurately assess the impact of each parameter on DRAM performance.

[0099] To test:

[0100] After setting the mode register configuration, use a high-precision tester to perform read and write tests, timing tests, etc. on the DRAM chip to evaluate its performance.

[0101] Record the test results, including key indicators such as read and write speed, timing margin, error rate, etc.

[0102] Analyze the test results:

[0103] Compare test results for different mode register configurations to identify the configuration with the best performance or the most prominent problems.

[0104] If you find performance issues under a certain configuration, try adjusting other related parameters for further optimization.

[0105] S302, simulate power-on test.

[0106] Simulate the power-on process of a DRAM chip and observe the differences between a normal DRAM chip and an abnormal DRAM chip.

[0107] Prepare the test environment:

[0108] Use dedicated DRAM test equipment or high-precision testers to simulate the power-on process of DRAM chips.

[0109] Ensure that the test environment is stable and avoid external interference affecting the power-on process.

[0110] Simulate power-on:

[0111] According to the power-on timing and voltage requirements specified in the DRAM chip's data sheet, use test equipment to simulate the power-on process of the DRAM chip.

[0112] Observe and record the behavior of the DRAM chip during the power-on process, such as the initialization process, timing margin, etc.

[0113] Comparing normal and abnormal DRAM chips:

[0114] If you have normal and abnormal DRAM chip samples, you can perform simulated power-on tests on them at the same time.

[0115] Compare the differences in their behaviors during the power-on process to identify possible problems with the abnormal DRAM chip.

[0116] S303, Shmoo test.

[0117] The Shmoo test is used to find out the difference areas between normal DRAM and abnormal DRAM, and the source code is adjusted for debugging according to the difference conditions.

[0118] Prepare the test environment:

[0119] Use dedicated DRAM test equipment or a high-precision tester to perform Shmoo testing.

[0120] Ensure that the test environment is stable and can accurately control the timing parameters of DRAM chips.

[0121] To perform a Shmoo test:

[0122] Select one or more key timing parameters (such as CAS latency, RAS to CAS latency, etc.) as test variables.

[0123] Change the values ​​of these timing parameters within a certain range and observe the performance of the DRAM chip (such as read and write speed, error rate, etc.).

[0124] Record the test results at each timing parameter value and draw them into a chart (i.e., Shmoo chart) for analysis.

[0125] Analyze the Shmoo Chart:

[0126] Observe the performance differences under different timing parameter values ​​in the Shmoo diagram.

[0127] Identify areas where performance is optimal or where problems are most prominent (i.e., “sweet spots” or “problem areas”).

[0128] Adjust the relevant timing parameter settings in the source code based on the analysis results to optimize the performance of the DRAM chip or solve potential problems.

[0129] Step 4: Solve compatibility issues

[0130] S401, soft modification.

[0131] Solve the problem by modifying the parameters in the source code. For example, if you find a problem with the setting of the tCL parameter, you can solve it by modifying the tCL value in the source code.

[0132] Problem location:

[0133] First, it is necessary to identify the problem, such as improper timing parameter settings, incorrect voltage configuration, or other compatibility issues at the software level.

[0134] Parameter adjustment:

[0135] According to the problem location, modify the relevant parameter settings in the source code. For example, if it is found that the tCL (CAS latency) parameter setting is improper and causes performance problems, adjust the corresponding tCL value in the source code.

[0136] When adjusting parameters, you need to refer to the DRAM chip data sheet and the circuit board design specifications to ensure that the parameter values ​​are within a reasonable range.

[0137] Test verification:

[0138] After modifying the source code, recompile and load it into the target system for testing.

[0139] Use professional testing tools or software to perform read and write tests, timing tests, etc. on the DRAM chip to verify whether the problem is resolved.

[0140] Optimization adjustments:

[0141] If the problem is still not completely solved, it may be necessary to further adjust other related parameters and perform multiple iterative tests until the optimal parameter configuration is found.

[0142] S402, hard modification.

[0143] If the problem is caused by the physical design of the board, the board needs to be redesigned or adjusted. For example, if it is found that the lines on the board are not of equal length, the line layout needs to be redesigned.

[0144] Problem Analysis:

[0145] Carefully analyze the design drawings and wiring of the circuit board to identify physical factors that may cause compatibility issues, such as unequal line lengths, signal interference, etc.

[0146] Design tweaks:

[0147] Based on the problem analysis results, redesign or adjust the circuit layout, signal shielding, etc. of the circuit board.

[0148] It may be necessary to modify the board stackup structure, add signal isolation measures, or adjust component layout.

[0149] Production verification:

[0150] Prototype new circuit boards and assemble and test them.

[0151] Use professional testing equipment to jointly test DRAM chips and circuit boards to verify whether the design adjustments have effectively solved the compatibility issues.

[0152] Mass production:

[0153] If the verification is successful, mass production of the new circuit boards can begin and replace the old circuit boards with compatibility issues.

[0154] S403, incompatibility.

[0155] If the board hardware is obviously not supported, resulting in complete incompatibility, it cannot be solved by the above method.

[0156] Replace DRAM chip:

[0157] Select a DRAM chip that is compatible with the board for replacement.

[0158] When choosing a new chip, you need to carefully check the chip's technical specifications and the circuit board's compatibility requirements.

[0159] Replacement of circuit board:

[0160] If you cannot find a board that is compatible with your existing DRAM chips, or if the cost of replacing the DRAM chips is prohibitive, you may want to consider replacing the entire board.

[0161] When choosing a new circuit board, you need to make sure it is compatible with the DRAM chips as well as other system components.

[0162] Upgrade System:

[0163] In some cases, upgrading the entire system (including circuit boards, DRAM chips, and other key components) may be the best solution to compatibility issues.

[0164] When upgrading your system, you need to consider factors such as cost, performance, availability, and future scalability.

[0165] The beneficial effects of this embodiment are as follows: the present invention can not only help to quickly locate and solve problems through a series of automated testing and analysis methods, but also significantly improve the quality and efficiency of testing, reduce costs, and enhance product compatibility and stability.

[0166] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

[0167] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to only specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A failure mode analysis system for DRAM, characterized in that: It includes test environment management module, frequency reduction processing module, SI analysis module, special configuration test module and compatibility adaptation module; Test environment management module: used to manage the test environment, including acquiring and configuring test resources, including DRAM chips, circuit boards, and system source code; Frequency reduction processing module: used to adjust the DRAM operating rate by modifying the source code and implement frequency reduction testing to determine whether the problem is related to the operating speed; SI analysis module: used to perform signal integrity measurements, identify signals that may cause problems, and resolve compatibility issues by adjusting timing parameters; Special configuration test module: used to test the special configuration of DRAM and verify the impact of the special configuration; Compatibility adaptation module: used to perform soft or hard modifications based on test results to achieve compatibility adaptation between DRAM chips and circuit boards.

2. The failure mode analysis system for DRAM according to claim 1, characterized in that: The test environment management module is also used to prepare at least two sets of test equipment and chips to cross-confirm that the problem is indeed the DRAM chip + circuit board.

3. The failure mode analysis system for DRAM according to claim 1, characterized in that: The frequency reduction processing module also includes a function for flashing the frequency-reduced system firmware / software into the DRAM chip+circuit board.

4. The failure mode analysis system for DRAM according to claim 1, characterized in that: The SI analysis module also includes functionality for performing complete signal integrity measurements in the event that the downclocking test fails.

5. The failure mode analysis system for DRAM according to claim 1, characterized in that: The special configuration test module also includes functionality for setting different mode register configurations to verify the impact of special configurations.

6. The failure mode analysis system for DRAM according to claim 1, characterized in that: The compatibility adaptation module also includes a function for determining specific steps of soft modification or hard modification according to the test results.

7. A failure mode analysis method applied to DRAM, used to implement the failure mode analysis system applied to DRAM as claimed in claim 1, characterized in that: The method flow is as follows: Step 1: Obtain test resources and conduct preliminary verification; S11, obtaining a test environment and related test resources provided by a client, wherein the test resources include a DRAM chip and a system source code; S12. Verify the problem. Use m sets of test equipment and chips to cross-verify and confirm that the compatibility failure problem is caused by the coordination between the DRAM chip and the circuit board. S13, frequency reduction attempt, frequency reduction processing of the problematic DRAM chip and circuit board, by reducing the operating speed to relax the operating conditions of the DRAM chip to determine whether the problem is improved; S14, timing relaxation: If the problem is improved after frequency reduction, relax the timing parameters one by one from the first timing parameter to determine which timing parameter causes the problem; Step 2: Signal integrity measurement; S21. If the problem still exists after frequency reduction, perform signal integrity measurement to check whether there is a margin problem during the power-on process. S22. According to the SI measurement result, adjust the relevant timing in the source code to improve the abnormal situation. When the measurement finds that the Margin of the tCL parameter is less than the threshold, adjust the tCL value in the source code; Step 3: Special configuration test; S31, set different mode register configurations and test them using a high-precision tester; S32, simulating the power-on process of the DRAM chip, and observing the difference between the normal DRAM and the abnormal DRAM; S33, finding the difference area between the normal DRAM chip and the abnormal DRAM chip through Shmoo test, and adjusting the source code for debugging according to the difference conditions; Step 4: Solve compatibility issues; S41, software modification: solve the problem by modifying the parameters in the source code. If a problem is found in the setting of the tCL parameter, solve it by modifying the tCL value in the source code; S42, hard modification: If the root cause of the problem lies in the physical design of the circuit board, redesign and adjust the circuit board. If it is found that the circuits on the circuit board are of unequal length, redesign the circuit layout; S43. Incompatibility: If the circuit board hardware does not support it, resulting in complete incompatibility, it cannot be resolved by the above method.

8. The failure mode analysis method for DRAM according to claim 7, characterized in that: The m is greater than or equal to 2.

9. The failure mode analysis method for DRAM according to claim 7, characterized in that: The first timing is a timing parameter that has the smallest impact on system performance.

Images