Semiconductor packaging structure

Abstract

The invention provides a semiconductor packaging structure. The semiconductor packaging structure comprises a first substrate; the processor module is arranged on the first plane of the first substrate and is connected with the first substrate; the chip stacking structure is arranged on the first plane of the first substrate and connected with the first substrate, and the first substrate is used for transmitting a first type of signals between the processor module and the chip stacking structure; the signal adapter plate is connected with the processor module and the chip stacking structure, and the signal adapter plate is used for transmitting a second type signal between the processor module and the chip stacking structure; the second substrate is parallel to the first substrate and connected with the second plane of the first substrate, and the second plane of the first substrate is parallel to and opposite to the first plane of the first substrate. According to the embodiment of the invention, the semiconductor packaging cost can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor packaging structure. Background Art

[0002] HBM (High Bandwidth Memory) technology is a high-bandwidth memory technology that uses 3D stacking technology to stack multiple DRAM chips vertically together and connect them through silicon vias to form a high-density, high-bandwidth memory module.

[0003] As the process level advances, the size of highly integrated HBM is getting larger and larger. Correspondingly, the size of processors such as GPUs (Graphics Processing Units) connected to HBM is also increasing, and the chip size of the silicon interposer used to connect HBM and processors is also increasing. The increase in the size of the silicon substrate brings about a significant increase in production difficulty and production cost.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] An object of the present disclosure is to provide a semiconductor packaging structure for reducing semiconductor packaging costs.

[0006] According to a first aspect of the present disclosure, a semiconductor packaging structure is provided, comprising: a first substrate; a processor module, arranged on a first plane of the first substrate and connected to the first substrate; a chip stacking structure, arranged on a first plane of the first substrate and connected to the first substrate, the first substrate being used to transmit a first type of signal between the processor module and the chip stacking structure; a signal adapter board, connecting the processor module and the chip stacking structure, the signal adapter board being used to transmit a second type of signal between the processor module and the chip stacking structure; a second substrate, arranged parallel to the first substrate and connected to a second plane of the first substrate, the second plane of the first substrate being parallel to and opposite to the first plane of the first substrate.

[0007] In an exemplary embodiment of the present disclosure, the first type of signal includes a power signal, and the second type of signal includes an input / output signal.

[0008] In an exemplary embodiment of the present disclosure, a chip stacking structure includes: a first semiconductor chip, which is arranged parallel to a first substrate and connected to a first plane of the first substrate; a second semiconductor chip stacking structure, which is located on the first semiconductor chip and includes a plurality of second semiconductor chips stacked in sequence, each of which is arranged parallel to the first substrate, and the plurality of second semiconductor chips stacked in sequence realize signal connection through a silicon through-hole structure perpendicular to the first substrate.

[0009] In an exemplary embodiment of the present disclosure, a first preset number of through silicon via structures of the second semiconductor chip stacking structure are used to transmit a first type of signal to achieve communication of the first type of signal between the first semiconductor chip and the signal transfer board.

[0010] In an exemplary embodiment of the present disclosure, a first wireless communication module is provided on a first semiconductor chip, and a second wireless communication module is provided on a signal adapter board. The first semiconductor chip is used to communicate with the second wireless communication module through the first wireless communication module to realize control of the signal transmission process of the signal adapter board.

[0011] In an exemplary embodiment of the present disclosure, the signal transfer board is arranged in parallel with the first substrate.

[0012] In an exemplary embodiment of the present disclosure, the chip stacking structure has a plurality of through silicon via structures perpendicular to the first substrate, the chip stacking structure is provided with a first signal pin connected to the through silicon via structure on a side away from the first substrate, the processor module is provided with a second signal pin on a side away from the first substrate, the first plane of the signal adapter board connects the first signal pin and the second signal pin, and the first signal pin and the second signal pin are both used to transmit a first type of signal.

[0013] In an exemplary embodiment of the present disclosure, the first signal pin is disposed on a side of the chip stacking structure close to the processor module, and the second signal pin is disposed on a side of the processor module close to the chip stacking structure.

[0014] In an exemplary embodiment of the present disclosure, the signal transfer board is vertically arranged to the first substrate.

[0015] In an exemplary embodiment of the present disclosure, a signal adapter board is arranged between a processor module and a chip stacking structure, a first plane of the signal adapter board is connected to a side of the processor close to the chip stacking structure, a second plane of the signal adapter board is connected to a side of the chip stacking structure close to the processor, and the first plane and the second plane of the signal adapter board are relative and parallel.

[0016] In an exemplary embodiment of the present disclosure, a chip stacking structure includes a first semiconductor chip vertically arranged with a first substrate and a plurality of second semiconductor chips stacked in parallel on the first semiconductor chip, the first semiconductor chip is provided with a third signal pin on a side close to the processor module, the processor module is provided with a fourth signal pin on a side close to the chip stacking structure, the first plane of the signal adapter board is connected to the third signal pin, and the second plane of the signal adapter board is connected to the fourth signal pin.

[0017] In an exemplary embodiment of the present disclosure, a signal shielding layer is disposed on the first surface and / or the second surface of the signal adapter board, and the first surface and the second surface are disposed opposite to each other.

[0018] In an exemplary embodiment of the present disclosure, the signal wiring in the first substrate is completed by a redistribution layer process.

[0019] In an exemplary embodiment of the present disclosure, the first semiconductor chip includes a logic chip, and the second semiconductor chip stack structure includes a DRAM chip.

[0020] In an exemplary embodiment of the present disclosure, it also includes: a packaging compound structure, located on the second substrate, used to wrap the first substrate, the signal transfer board, the processor module, and the chip stacking structure.

[0021] The disclosed embodiment uses a signal transfer board and a first substrate to jointly complete signal transmission between a processor module and a chip stacking structure, and sets the first substrate to transmit only a first type of signal, which can greatly reduce the manufacturing cost of the first substrate (silicon substrate) and reduce the overall packaging cost.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 Schematic diagram of a semiconductor package structure in an exemplary embodiment of the present disclosure.

[0025] Figure 2 It is a schematic diagram of a chip stacking structure in one embodiment of the present disclosure.

[0026] Figure 3It is a schematic diagram of a signal adapter board in one embodiment of the present disclosure.

[0027] Figure 4 It is a schematic diagram of a signal adapter board in another embodiment of the present disclosure.

[0028] Figure 5 It is a schematic diagram of a signal adapter board in another embodiment of the present disclosure.

[0029] Figure 6 is a schematic diagram of a semiconductor packaging structure in another embodiment of the present disclosure.

[0030] Figure 7 is a schematic diagram of a semiconductor packaging structure in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0032] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0033] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0034] Figure 1 Schematic diagram of a semiconductor package structure in an exemplary embodiment of the present disclosure.

[0035] refer to Figure 1 , the semiconductor package structure 100 may include:

[0036] A first substrate 1;

[0037] The processor module 2 is arranged on the first plane of the first substrate 1 and connected to the first substrate 1;

[0038] The chip stacking structure 3 is disposed on a first plane of the first substrate 1 and connected to the first substrate 1. The first substrate 1 is used to transmit a first type of signal between the processor module 2 and the chip stacking structure 3.

[0039] A signal adapter board 4, connected to the processor module 2 and the chip stacking structure 3, the signal adapter board 4 is used to transmit a second type of signal between the processor module 2 and the chip stacking structure 3;

[0040] The second substrate 5 is arranged in parallel with the first substrate 1 and connected to the second plane of the first substrate 1 . The second plane of the first substrate 1 is parallel to and opposite to the first plane of the first substrate 1 .

[0041] In the embodiment of the present disclosure, the chip stacking structure 3 is, for example, HBM (High Bandwidth Memory). The technical solution of the embodiment of the present disclosure can be applied to the 2.5D packaging of HBM and controller. The 2.5D packaging of HBM and controller refers to the separate manufacturing of the controller and HBM chips, and then connecting them together through a silicon substrate (silicon interposer, i.e., the first substrate 1). This packaging technology can improve the chip's performance such as bandwidth and memory capacity, as well as power efficiency, while reducing the chip's size, weight, and power consumption. Since the controller and HBM chips are manufactured separately, different processes and materials can be used to obtain better performance and power efficiency.

[0042] In one embodiment, the first substrate 1 may be a printed circuit board (PCB) or a silicon substrate (silicon interposer). The first substrate 1 may include a first base (not shown) and a first upper insulating dielectric layer (not shown) and a first lower insulating dielectric layer (not shown) respectively located on the upper surface and the lower surface of the first substrate. The first substrate may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. It may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), or a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc. The first upper insulating dielectric layer and the first lower insulating dielectric layer may be solder resist layers, for example, the materials of the first upper insulating dielectric layer and the first lower insulating dielectric layer may be green paint. In the embodiment disclosed herein, the surface corresponding to the first upper insulating dielectric layer is referred to as the first plane ( Figure 1 The surface corresponding to the first lower insulating dielectric layer is called the second plane of the first substrate 1 ( Figure 1 the lower surface in the middle).

[0043] The first substrate 1 connects the processor module 2 and the chip stacking structure 3 at the same time, and provides a path for signal communication between the processor module 2 and the chip stacking structure 3. Due to the position and function of the first substrate 1, the manufacturing cost of the first substrate 1 is relatively high. As the requirements for storage performance and processing performance increase, the sizes of the processor module 2 and the chip stacking structure 3 increase, and the size of the first substrate 1 also increases, and the difficulty and cost of manufacturing production increase significantly.

[0044] In the 2.5D package of HBM and controller, the signals transmitted between HBM and controller mainly include input and output signals (IO signals) and power signals, which are usually transmitted through the PHY (Physical Layer) on the silicon substrate. There are many IO signals, the transmission lines are dense, and the pitch is small, so silicon-metal connection is required, which has high process requirements; there are fewer power signals, the transmission lines are thicker, and the pitch is larger.

[0045] In the embodiment of the present disclosure, the first substrate 1 is configured to transmit only the first type of signal, so as to reduce the area of ​​the first substrate 1 and reduce the requirements for the manufacturing process of the first substrate 1. The first type of signal can be a signal with a small number and a large wiring width. In one embodiment, the first type of signal is a power signal. The number of power signals is small and the wiring width is large. When the first substrate 1 is only used to transmit the power signal, the area of ​​the first substrate 1 will be greatly reduced, and the processing cost of the first substrate 1 will also be reduced accordingly, thereby reducing the manufacturing cost of the semiconductor package structure 100.

[0046] In one embodiment, the signal wiring in the first substrate 1 can be completed using an RDL (Redistribution Layer) process, without providing a traditional silicon-metal wiring in the first substrate 1 , so as to reduce the manufacturing cost of the first substrate 1 . The cost of wiring using RDL (Redistribution Layer) technology is lower than that of silicon-metal wiring because RDL technology can add a layer of metal lines on the wafer, thereby achieving higher line density and more complex wiring structure, while silicon-metal wiring requires etching metal lines on the wafer, which has a higher manufacturing cost; in addition, RDL technology can use thinner metal layers, thereby reducing the amount and cost of metal used, while silicon-metal wiring requires using thicker metal layers, which has a higher cost; thirdly, RDL technology can achieve higher manufacturing efficiency and shorter manufacturing cycle because it can complete the wiring of multiple chips on the wafer at one time, while silicon-metal wiring requires etching and wiring on each chip separately, which has a longer manufacturing cycle; finally, RDL technology can achieve higher reliability and lower failure rate because it can reduce the distance and intersection between metal lines, thereby reducing interference and failure rate between lines, while silicon-metal wiring is prone to interference and failure between lines.

[0047] Therefore, the cost of wiring using RDL technology is lower than that of silicon-metal wiring, and higher line density, more complex wiring structure, higher manufacturing efficiency and lower failure rate can be achieved. Only wiring on the first substrate 1 through the RDL process can greatly reduce the manufacturing cost of the first substrate 1, thereby reducing the overall manufacturing cost of the semiconductor packaging structure 100. Only the first substrate 1 is set to transmit the first type of signal, which also provides a prerequisite for completing the wiring through the RDL process, because the signal line wiring of the second type of signal cannot be completed through the RDL process.

[0048] It can be understood that although the above-mentioned embodiment takes the first type of signal as a power signal and the second type of signal as an input and output signal as an example, in other embodiments of the present disclosure, any signal that can meet the wiring requirements through the RDL wiring process can be called a first type of signal, and other signals except the first type of signal transmitted between the processor module 2 and the chip stacking structure 3 can be collectively referred to as second type of signals. The present disclosure does not limit the specific signal names involved in the first type of signal and the second type of signal.

[0049] Continue to refer Figure 1 The first substrate 1 realizes signal connection with the processor module 2 through the processor connection bump 11, realizes signal connection with the chip stacking structure 3 through the stacking structure connection bump 12, and realizes signal connection with the second substrate 5 through the substrate connection bump 13.

[0050] A substrate connection bump 13 is formed on the second plane of the first substrate 1. The substrate connection bump 13 can electrically connect the first substrate 1 to the second substrate 5. The second substrate 5 is used to connect to the mainboard of the electronic device through the mainboard connection structure 51. Therefore, while providing a signal path for the processor module 2 and the chip stacking structure 3, the first substrate 1 can also receive at least one of the data to be processed, the power signal and the ground signal from the mainboard from the second substrate 5, or provide the control command and data signal issued by the processor module 2 to the second substrate 5, and then to the mainboard.

[0051] The substrate connection bump 13 includes a conductive material. In the embodiment of the present disclosure, the substrate connection bump 13 is a solder ball. It can be understood that the shape of the substrate connection bump provided in the embodiment of the present disclosure is only a lower-level, feasible specific implementation in the embodiment of the present disclosure, and does not constitute a limitation to the present disclosure. The substrate connection bump may also be other shapes and structures. The number, spacing and position of the substrate connection bumps are not limited to any specific arrangement, and various modifications can be made.

[0052] The processor module 2 disposed on the first plane of the first substrate 1 has an independent package, and the processor module 2 is connected to the first plane of the first substrate 1 through the processor connection bump 11. The processor module 2 is responsible for performing various computing tasks, such as logical operations, arithmetic operations, control flow, etc. It can be a single integrated circuit (SOC, System on a Chip, system on chip), or it can be a complex system composed of multiple functional units. In one embodiment, the processor module 2 can be a GPU (Graphics Processing Unit, graphics processor).

[0053] The chip stacking structure 3 disposed on the first plane of the first substrate 1 includes a first semiconductor chip 31 and a second semiconductor chip stacking structure 32. In one embodiment, a stacking structure connection bump 12 for connecting to the first substrate 1 is formed on one surface of the first semiconductor chip 31. The first semiconductor chip 31 is electrically connected to the first substrate 1 through the stacking structure connection bump 12, and the first substrate 1 supplies power to the first semiconductor chip 31 and exchanges signals in a wired manner.

[0054] The material of the processor connection bump 11 and the stacking structure connection bump 12 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold. In some other embodiments, the first substrate 1 and the processor module 2 and the chip stacking structure 3 may also be connected by welding, pins, etc., and the present disclosure does not impose any special restrictions on this. However, since the first substrate 1 is configured to transmit only the first type of signal, the connection method of the first substrate 1 and the processor module 2 and the chip stacking structure 3 can adopt the method with the lowest process requirements among the available connection methods (such as welding) to further reduce costs.

[0055] In one embodiment, when the first semiconductor chip 31 in the chip stack structure 3 is disposed on the first substrate 1, as shown in FIG. Figure 1 As shown, the process is simple, and there is a gap between the first semiconductor chip 31 and the first substrate 1, which can increase the heat dissipation effect of the first semiconductor chip 31. At this time, the stacked structure connection bumps 12 and the processor connection bumps 11 are horizontal in the first direction.

[0056] In another embodiment, the stacking structure connection bump 12 may also be disposed in a groove (not shown) on the first substrate 1 to improve structural stability and reduce the packaging height of the semiconductor packaging structure. In addition, the first semiconductor chip 31 in the chip stacking structure 3 may also be partially disposed in the groove to achieve the effect of partially embedding the chip stacking structure 3 in the first substrate 1, further improving structural stability and reducing the packaging height of the semiconductor packaging structure. At this time, the stacking structure connection bump 12 is lower than the processor connection bump 11 in the first direction.

[0057] In another embodiment, the chip stacking structure 3 and the processor module 2 may both have corresponding grooves (not shown) on the first substrate 1, and the stacking structure connection bumps 12 and the processor connection bumps 11 are both arranged in the corresponding grooves to improve the structural stability and reduce the packaging height of the semiconductor packaging structure. In addition, the chip stacking structure 3 and the processor module 2 may also be partially arranged in the corresponding grooves to achieve the effect that the chip stacking structure 3 and the processor module 2 are both partially embedded in the first substrate 1, further improving the structural stability and reducing the packaging height of the semiconductor packaging structure. In this case, the stacking structure connection bumps 12 and the processor connection bumps 11 are still horizontal in the first direction.

[0058] Regardless of the relative positional relationship, the stacked structure connection bumps 12 and the processor connection bumps 11 transmit the first type of signal through the first substrate 1. In addition, the stacked structure connection bumps 12 and the processor connection bumps 11 can also be connected to the substrate connection bumps 13 through the leads (not shown) in the first substrate 1, so that the first semiconductor chip 31 and the processor module 2 can exchange information with the third substrate 3 and the mainboard through the substrate connection bumps 13.

[0059] The signal transfer board 4 connects the processor module 2 and the chip stacking structure 3, and is used to transmit the second type of signal between the two. The signal transfer board 4 can be implemented, for example, by a bridge chip (Bridge Die) or other medium entities (such as PCB boards) that can realize signal transmission. The signal transfer board 4 connects the processor module 2 and the chip stacking structure 3 at the same time, and establishes a bridge between the processor module 2 and the chip stacking structure 3, so that they can communicate with each other and exchange data.

[0060] The signal transfer board 4 has a plurality of transistors and other electronic components to amplify, filter, convert, and process two or more input signals, and then output them to the processor module 2 or the chip stacking structure 3. In addition, the signal transfer board 4 has two interfaces, which are respectively connected to the processor module 2 and the chip stacking structure 3, and each interface can be used to receive and send data. That is, in the signal transfer board 4, at least two interfaces for connecting the processor module 2 and the chip stacking structure 3, a path for transmitting data, and a signal processing circuit for amplifying, filtering, converting, and other processing of the input signal are provided.

[0061] Among the signals transmitted between the processor module 2 and the chip stacking structure 3, the signals with higher signal line manufacturing requirements can be called second-category signals, such as various signals that need to be transmitted using a silicon-metal connection. Since the cost of implementing silicon-metal connection in the bridge chip is low and the area is small, setting the silicon-metal connection in the bridge chip (signal adapter board 4) instead of the first substrate 1 can effectively reduce the manufacturing cost of the overall packaging structure.

[0062] In one embodiment, the signal adapter board 4 can realize bidirectional communication between the processor module 2 and the chip stacking structure 3, and can transmit data to the processor module 2 as well as to the chip stacking structure 3. In another embodiment, the signal adapter board 4 has only a unidirectional transmission function, and is used to transmit data from the processor module 2 to the chip stacking structure 3, or to transmit data from the chip stacking structure 3 to the processor module 2.

[0063] Whether it is unidirectional transmission or bidirectional transmission, in the embodiment of the present disclosure, the signal adapter board 4 is only used to transmit the second type of signal. Unlike the first type of signal, the second type of signal can be a signal with a large number, a small line width, dense wiring, and high requirements for the manufacturing process. In one embodiment of the present disclosure, the second type of signal includes input and output signals, and the data signal includes but is not limited to a control address signal (Commond / Address, CA signal), a data queue signal (DataQueue, DQ) and other auxiliary control signals, such as a clock signal (CLK), various enable signals (Enable), etc. When the signal adapter board 4 is implemented by a bridge chip, it can be processed more finely and can be used to undertake the transmission of signals with high requirements for the manufacturing process. Since the signal adapter board 4 only undertakes the transmission of part of the signal and has a limited area, the use of the signal adapter board 4 to transmit the second type of signal with a higher cost can effectively reduce the manufacturing cost of the packaging structure compared to transmitting all signals through the high-cost first substrate 1.

[0064] It should be noted that in the embodiment of the present disclosure, the sum of the first type of signal and the second type of signal is all the signals transmitted between the processor module 2 and the chip stacking structure 3. By distinguishing the signals transmitted between the processor module 2 and the chip stacking structure 3 into the first type of signal and the second type of signal, and using the first substrate 1 with a higher cost and the signal transfer board 4 with a lower cost to transmit the first type of signal with a lower process requirement and a smaller number and the second type of signal with a higher process requirement and a larger number, respectively, the signal interconnection cost between the processor module 2 and the chip stacking structure 3 can be greatly reduced, and the cost of the overall semiconductor packaging structure 100 can be reduced.

[0065] In one embodiment, the transmission path of the second type of signal can be made using a small chip, which is used as a bridge chip to connect the processor module 2 and the chip stacking structure 3 during assembly. Other connections are led out using the FO process to make a packaged whole (cube) composed of the processor module 2 and the chip stacking structure 3, and then substrate packaging is performed (the first substrate 1 and the second substrate 5 are used to complete the packaging). The FO process refers to the fiber optic manufacturing process, which uses photolithography technology to manufacture tiny optical elements on silicon wafers, and then couples the optical elements with optical fibers to achieve transmission and processing of optical signals.

[0066] The disclosed embodiment can effectively reduce the production and cost pressure of the silicon substrate (first substrate 1) by implementing the signal transmission function and the power supply function using the signal transfer board 4 and the first substrate 1 respectively, and using different processes to manufacture the signal transfer board 4 and the first substrate 1. In addition, since the bridge chip (signal transfer board 4) for signal connection can be made very small, the DPW (dies per wafer, the number of chips that can be produced per wafer) is high, which can effectively reduce the cost of signal interconnection between the processor module 2 and the chip stacking structure 3.

[0067] Figure 2 It is a schematic diagram of a chip stacking structure in one embodiment of the present disclosure.

[0068] refer to Figure 2 , the chip stacking structure 3 may include:

[0069] A first semiconductor chip 31 is arranged parallel to the first substrate 1 and connected to a first plane of the first substrate 1;

[0070] The second semiconductor chip stacking structure 32 is located on the first semiconductor chip 31, and includes a plurality of second semiconductor chips 321 stacked in sequence, each of which is arranged parallel to the first substrate 1, and the plurality of second semiconductor chips 321 stacked in sequence realize signal connection through a through silicon via structure TSV perpendicular to the first substrate 1.

[0071] In an exemplary embodiment of the present disclosure, the first semiconductor chip 31 is, for example, a logic chip (Logic Die, also called a basic chip), and the second semiconductor chip stacking structure 32 includes a DRAM chip (also called a core chip).

[0072] The second semiconductor chip stacking structure 32 is, for example, HBM (High Band width Memory). HBM technology is the main representative product of the development of DRAM from traditional 2D to 3D, opening the road to DRAM three-dimensionalization. It mainly uses through silicon via (TSV) technology to stack chips to increase throughput and overcome the bandwidth limitations in a single package. Several DRAM dies are stacked vertically, and the dies are connected with TVS technology. From a technical point of view, HBM makes full use of space and reduces area, which is in line with the development trend of miniaturization and integration in the semiconductor industry, and breaks through the bottleneck of memory capacity and bandwidth. It is regarded as a new generation of DRAM solutions. In the second semiconductor chip stacking structure 32, each second semiconductor chip 321 is a DRAM chip.

[0073] exist Figure 2In the illustrated embodiment, the second semiconductor chips 321 are sequentially stacked in parallel (P-Stack) on the first semiconductor chip 31, and a plurality of second semiconductor chips 321 are connected to each other by a plurality of through silicon via structures TSV perpendicular to the first substrate 1 to achieve signal connection. At least one through silicon via structure TSV runs through all the second semiconductor chips 321 to achieve data transmission between the plurality of second semiconductor chips 321. The setting position and setting number of the through silicon via structure TSV for data transmission between the second semiconductor chips 321 can be determined according to the design of the second semiconductor chip 321.

[0074] In some embodiments, the second semiconductor chip 321 and the first semiconductor chip 31 can also communicate through a through silicon via structure TSV. In other embodiments, the first semiconductor chip 31 and the second semiconductor chip stacking structure 32 can also communicate wirelessly. For example, a wireless coil (not shown) is set in each DRAM in the second semiconductor chip stacking structure 32, and correspondingly, a corresponding wireless coil is set at a corresponding position of the above coil on the first semiconductor chip 31. Wireless communication between the first semiconductor chip 31 and the second semiconductor chip stacking structure 32 can effectively solve the difficulties in communication caused by the increase in the number of stacking layers of the second semiconductor chip 321, while reducing the number of through silicon via structures TSV (used to transmit signals) and reducing the difficulty of the process.

[0075] In addition to Figure 2 As shown, the second semiconductor chips 321 are sequentially stacked in parallel (P-Stack) on the first semiconductor chip 31. In one embodiment, the plurality of second semiconductor chips 321 in the second semiconductor chip stacking structure 32 can also be stacked vertically (V-Stack) in parallel on the first semiconductor chip 31. In this way, the first semiconductor chip 31 and the second semiconductor chip 321 can communicate wirelessly, effectively solving the communication difficulties caused by the increase in the number of stacking layers of the second semiconductor chips 321 when the plurality of second semiconductor chips are sequentially stacked in parallel (P-Stack) on the first semiconductor chip 31. That is, by setting the stacking direction of the second semiconductor chip stacking structure 32 to be perpendicular to the surface of the first semiconductor chip 31, each second semiconductor chip 321 can have the same communication distance with the first semiconductor chip 31, thereby overcoming the communication delay caused by multi-layer stacking.

[0076] In one embodiment, a first wireless communication module 311 is provided on the first semiconductor chip 31, and a second wireless communication module 312 is provided on the signal adapter board 4. The first semiconductor chip 31 is used to communicate with the second wireless communication module 312 through the first wireless communication module 311 to control the signal transmission process of the signal adapter board 4. The communication method between the first wireless communication module 311 and the second wireless communication module 312 is, for example, WIFI.

[0077] The first semiconductor chip 31 can communicate wirelessly with each of the second semiconductor chips 321 and the signal transfer board 4 .

[0078] The first semiconductor chip 31 can control the signal transfer board 4 through wireless communication to receive or stop receiving the second type of signal, start or stop processing the second type of signal, send or stop sending the second type of signal, and can control the signal transfer board 4 to process part or all of the second type of signal, and can also control the signal transfer board 4 to process the second type of signal using part or all of the processing methods. At the same time, the first semiconductor chip 31 can control each second semiconductor chip 321 to receive data transmitted by the signal transfer board 4, process the data transmitted by the signal transfer board 4, or control each second semiconductor chip 321 to process data and send the processed data to the chip stacking structure 3 through the signal transfer board 4.

[0079] Figure 3 It is a schematic diagram of a signal adapter board in one embodiment of the present disclosure.

[0080] refer to Figure 3 In one embodiment, the signal transfer board 4 is arranged parallel to the first substrate 1 .

[0081] At this time, a signal transfer board 4 may be provided to connect a side of the processor module 2 away from the first substrate 1 and a side of the chip stacking structure 3 away from the first substrate 1. Figure 3 That is, the signal transfer board 4 is arranged on the top layer of the processor module 2 and the chip stacking structure 3 , and the first substrate 1 is arranged on the bottom layer of the processor module 2 and the chip stacking structure 3 .

[0082] Since the signal transfer board 4 is used to transmit the more precise second type of signal, placing the signal transfer board 4 on the top layer can reduce the crosstalk and noise impact of the wiring of the bottom first substrate 1 on the second type of signal, thereby reducing signal interference. In addition, placing the signal transfer board 4 on the top layer is conducive to heat dissipation. At this time, when the RDL process is used in the bottom first substrate 1, the FO process can be used, and the cost will be relatively low.

[0083] exist Figure 3In the illustrated embodiment, the chip stacking structure 3 has a plurality of through silicon via structures TSV perpendicular to the first substrate 1, and the chip stacking structure 3 is provided with a first signal pin 41 connected to the through silicon via structure TSV on a side away from the first substrate 1, and the processor module 2 is provided with a second signal pin 42 on a side away from the first substrate 1, and the first plane of the signal adapter board 4 connects the first signal pin 41 and the second signal pin 42, and both the first signal pin 41 and the second signal pin 42 are used to transmit a first type of signal.

[0084] In one embodiment, the first signal pin 41 is arranged on a side of the chip stacking structure 3 close to the processor module 2, and the second signal pin 42 is arranged on a side of the processor module 2 close to the chip stacking structure 3, so that the area of ​​the signal transfer board 4 is as small as possible.

[0085] At this time, the first preset value of through silicon via structures TSV of the second semiconductor chip stacking structure 32 can be used to realize signal transmission communication between the first semiconductor chip 31 and the signal adapter board 4. Correspondingly, when the first signal pin 41 is set on the side of the chip stacking structure 3 close to the processor module 2, in the chip stacking structure 3, the first preset value of through silicon via structures TSV connected to the first signal pin 41 and used to transmit the second type of signal are set close to the processor module 2. In other embodiments of the present disclosure, the first preset value of through silicon via structures TSV and the first signal pin 41 can also have other position schemes. In special cases, the signal adapter board 4 can be expanded to connect the first preset value of through silicon via structures TSV located in the middle or other parts of the second semiconductor chip stacking structure 32. Those skilled in the art can determine the pins and size of the signal adapter board 4 according to the actual TSV setting, and the present disclosure does not impose any special restrictions on this.

[0086] Similarly, a first wireless communication module 311 may be provided on the first semiconductor chip 31, and a second wireless communication module 312 may be provided on the signal adapter board 4. The first semiconductor chip 31 communicates with the second wireless communication module 312 through the first wireless communication module 311 to control the signal transmission process of the signal adapter board 4.

[0087] That is, in Figure 3 In the illustrated embodiment, the communication between the signal transfer board 4 and the first semiconductor chip 31 may be only wired (via TSV communication) or a combination of wired and wireless communication.

[0088] When the signal transfer board 4 and the first semiconductor chip 31 communicate only by wired means or by a combination of wired and wireless means, since the first preset value of through silicon via structures TSV for transmitting signals penetrates multiple second semiconductor chips 321, each second semiconductor chip 321 can directly receive the second type of signal transmitted by the signal transfer board 4 from the first preset value of through silicon via structures TSV according to the control instruction of the first semiconductor chip 31, or directly send the second type of signal to the signal transfer board 4 based on the first preset value of through silicon via structures TSV. At this time, the signal transfer board 4 can be controlled by the first semiconductor chip 31, or it can be controlled by the processor module 2 at the same time as the first semiconductor chip 31.

[0089] In another embodiment, each second semiconductor chip 321 may not directly exchange signals with the signal transfer board 4, and the first preset number of through silicon via structures TSV may be used only to transmit signals between the signal transfer board 4 and the first semiconductor chip 31. At this time, the first semiconductor chip 31 uniformly receives the second type of signal from the signal transfer board 4 through the first preset number of through silicon via structures TSV, and then transmits data to the second semiconductor chip 321 through other through silicon via structures; or, uniformly receives data from each second semiconductor chip 321, and then sends the data to the signal transfer board 4 through the first preset number of through silicon via structures TSV.

[0090] The specific signal transmission control scheme can be set according to actual needs, and the present disclosure does not impose any special restrictions on this.

[0091] When performing substrate packaging, the connection between the first substrate 1 and the processor module 2 and the chip stacking structure 3 can be completed first, and then the connection between the processor module 2, the signal transfer board 4, and the chip stacking structure 3 can be completed, and finally the connection between the first substrate 1 and the second substrate 5 can be completed.

[0092] Figure 4 It is a schematic diagram of a signal adapter board in another embodiment of the present disclosure.

[0093] refer to Figure 4 In another embodiment, the signal transfer board 4 is vertically arranged to the first substrate 1 .

[0094] exist Figure 4 In the illustrated embodiment, the signal adapter board 4 is disposed between the processor module 2 and the chip stacking structure 3, the first plane of the signal adapter board 4 is connected to a side of the processor module 2 close to the chip stacking structure 3, the second plane of the signal adapter board 4 is connected to a side of the chip stacking structure 3 close to the processor module 2, and the first plane and the second plane of the signal adapter board 4 are opposite and parallel.

[0095] At this time, the chip stacking structure 3 includes a first semiconductor chip 31 arranged vertically to the first substrate 1 and a plurality of second semiconductor chips 321 stacked in parallel on the first semiconductor chip 31. The first semiconductor chip 31 is provided with a third signal pin 43 on a side close to the processor module 2, and the processor module 2 is provided with a fourth signal pin 44 on a side close to the chip stacking structure 3. The first plane of the signal adapter board 4 is connected to the third signal pin 43, and the second plane of the signal adapter board 4 is connected to the fourth signal pin 44.

[0096] When the stacking direction of the chip stacking structure 3 is parallel to the first substrate 1, the first semiconductor chip 31 is perpendicular to the first substrate 1 and close to the processor module 2. Thus, the signal transfer board 4 perpendicular to the first substrate 1 and parallel to the first semiconductor chip 31 can realize signal transmission between the processor module 2 and the first semiconductor chip 31 through the third signal pin 43 and the fourth signal pin 44. At this time, the chip stacking structure 3 also includes an adhesive film layer 33. The adhesive film layer 33 is located between the first semiconductor chip 31 and the second semiconductor chip stacking structure 32, and is used to bond the first semiconductor chip 31 and the second semiconductor chip stacking structure 32 to enhance the adhesion between them, thereby improving the firmness of the semiconductor packaging structure. The adhesive film layer 33 is realized, for example, by a die-bonding adhesive film.

[0097] It should be noted that in this embodiment, when performing substrate packaging, it is necessary to first complete the connection between the processor module 2, the signal transfer board 4, and the chip stacking structure 3, then complete the connection between the first substrate 1 and the processor module 2, the chip stacking structure 3, and finally complete the connection between the first substrate 1 and the second substrate 5.

[0098] Figure 5 It is a schematic diagram of a signal adapter board in another embodiment of the present disclosure.

[0099] refer to Figure 5 In any embodiment of the present disclosure, the first surface and / or the second surface of the signal adapter board 4 may be provided with a signal shielding layer 40, and the first surface and the second surface are arranged opposite to each other.

[0100] The signal shielding layer 40 is, for example, an anti-signal interference coating or a signal shielding coating, so as to prevent the signal adapter board 4 from external signal interference and better protect the second type of signal.

[0101] Figure 6 is a schematic diagram of a semiconductor packaging structure in another embodiment of the present disclosure.

[0102] refer to Figure 6In the embodiment of the present disclosure, the number of processor modules 2 disposed on the first substrate 1 may be one or more, and the number of chip stacking structures 3 may be one or more. When the number of chip stacking structures 3 is multiple, they may be disposed around one or more processor modules 2. In this case, the first substrate 1 connects multiple chip stacking structures 3 and processor modules 2, and has a larger area.

[0103] At this time, a signal transfer board 4 can be provided between each chip stacking structure 3 and the processor module 2 to transmit the second type of signal, and the signal line wiring of the first type of signal is completed only by using the RDL process in the first substrate 1, thereby reducing the manufacturing cost of the first substrate 1. Figure 6 It can be seen from the illustrated embodiment that when the area of ​​the first substrate 1 is relatively large, lowering the process requirements for the first substrate 1 can greatly reduce the packaging cost.

[0104] Figure 7 is a schematic diagram of a semiconductor packaging structure in yet another embodiment of the present disclosure.

[0105] refer to Figure 7 In yet another embodiment, the semiconductor packaging structure further includes a packaging compound structure 6 located on the second substrate 5 and used to encapsulate the first substrate 1, the signal transfer board 4, the processor module 2, and the chip stacking structure 3.

[0106] In some embodiments, after completing the connection of the first substrate 1, the signal transfer board 4, the processor module 2, the chip stacking structure 3, and the second substrate 5, a packaging compound structure 6 can also be formed to package the semiconductor packaging structure 100 as a whole.

[0107] The packaging compound structure 6 includes a silicon-containing compound. The silicon-containing compound may be a spin-on glass (SOG), a silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials. By forming the packaging compound structure 6, and the material of the packaging compound structure 6 includes a silicon-containing compound, the warping problem of the second semiconductor chip stacking structure 32 can be reduced, and the semiconductor packaging structure 100 can also be packaged as a whole to improve the overall structural strength.

[0108] The embodiment of the present disclosure uses the signal adapter board 4 to transmit the second type of signal with higher process requirements, thereby reducing the manufacturing requirements for the first substrate 1 and reducing the cost of the overall packaging structure.

[0109] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0110] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: a first substrate; A processor module is disposed on a first plane of the first substrate and connected to the first substrate; A chip stacking structure, disposed on a first plane of the first substrate and connected to the first substrate, wherein the first substrate is used to transmit a first type of signal between the processor module and the chip stacking structure; A signal adapter board, connecting the processor module and the chip stacking structure, and the signal adapter board is used to transmit a second type of signal between the processor module and the chip stacking structure; The second substrate is arranged in parallel with the first substrate and connected to the second plane of the first substrate. The second plane of the first substrate is parallel to and opposite to the first plane of the first substrate.

2. The semiconductor package structure according to claim 1, wherein: The first type of signal includes a power signal, and the second type of signal includes an input / output signal.

3. The semiconductor package structure according to claim 1, wherein: The chip stacking structure comprises: A first semiconductor chip is arranged parallel to the first substrate and connected to a first plane of the first substrate; The second semiconductor chip stacking structure is located on the first semiconductor chip, and includes a plurality of second semiconductor chips stacked in sequence, each of the second semiconductor chips is arranged parallel to the first substrate, and the plurality of second semiconductor chips stacked in sequence realize signal connection through a silicon through-hole structure perpendicular to the first substrate.

4. The semiconductor package structure according to claim 3, wherein: The first preset number of through silicon via structures of the second semiconductor chip stacking structure are used to implement signal transmission between the first semiconductor chip and the signal transfer board.

5. The semiconductor package structure according to claim 3 or 4, characterized in that: A first wireless communication module is arranged on the first semiconductor chip, and a second wireless communication module is arranged on the signal adapter board. The first semiconductor chip is used to communicate with the second wireless communication module through the first wireless communication module to realize control of the signal transmission process of the signal adapter board.

6. The semiconductor package structure according to claim 1, wherein: The signal transfer board is arranged in parallel with the first substrate, and the signal transfer board connects a side of the processor module away from the first substrate and a side of the chip stacking structure away from the first substrate.

7. The semiconductor package structure according to claim 6, wherein: The chip stacking structure has a plurality of through silicon via structures perpendicular to the first substrate. The chip stacking structure is provided with a first signal pin connected to the through silicon via structure on a side away from the first substrate. The processor module is provided with a second signal pin on a side away from the first substrate. The first plane of the signal adapter board connects the first signal pin and the second signal pin, and the first signal pin and the second signal pin are both used to transmit the first type of signal.

8. The semiconductor package structure according to claim 7, wherein: The first signal pin is arranged at a side of the chip stacking structure close to the processor module, and the second signal pin is arranged at a side of the processor module close to the chip stacking structure.

9. The semiconductor package structure according to claim 1, wherein: The signal transfer board is arranged vertically to the first substrate.

10. The semiconductor package structure according to claim 9, wherein: The signal transfer board is arranged between the processor module and the chip stacking structure, the first plane of the signal transfer board is connected to the side of the processor module close to the chip stacking structure, the second plane of the signal transfer board is connected to the side of the chip stacking structure close to the processor module, and the first plane and the second plane of the signal transfer board are opposite and parallel.

11. The semiconductor structure according to claim 10, characterized in that The chip stacking structure includes a first semiconductor chip vertically arranged with respect to the first substrate and a plurality of second semiconductor chips stacked in parallel with the first semiconductor chip. The first semiconductor chip is provided with a third signal pin on a side close to the processor module, and the processor module is provided with a fourth signal pin on a side close to the chip stacking structure. The first plane of the signal adapter board is connected to the third signal pin, and the second plane of the signal adapter board is connected to the fourth signal pin.

12. The semiconductor package structure according to claim 1, wherein: A signal shielding layer is disposed on the first surface and / or the second surface of the signal adapter board, and the first surface and the second surface are disposed opposite to each other.

13. The semiconductor package structure according to claim 1, wherein: The signal wiring in the first substrate is completed by a redistribution layer process.

14. The semiconductor package structure according to claim 3, wherein: The first semiconductor chip includes a logic chip, and the second semiconductor chip stacking structure includes a DRAM chip.

15. The semiconductor package structure according to claim 1, wherein: Also includes: The packaging compound structure is located on the second substrate and is used to wrap the first substrate, the signal transfer board, the processor module, and the chip stacking structure.

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