TVS structure and manufacturing method thereof
By forming trench and insulating dielectric layers in the TVS structure, using undoped silicon glass protective layer and rapid annealing treatment, the problem of prone to cracking of the insulating dielectric layers is solved, and yield and manufacturing stability are improved.
Patent Information
- Application Number
- CN202411382841.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-01-10
AI Technical Summary
In the existing TVS structure with deep groove isolation structure, the insulating dielectric layer is prone to cracking, resulting in failure of the isolation structure and low yield.
A trench that penetrates the epitaxial layer and extends into the substrate at the bottom is formed and covered with the protective layer. Stress difference is reduced by rapid annealing treatment, and undoped silicon glass is used as the protective layer to prevent cracking of the insulating dielectric layer.
It effectively improves the yield of the TVS structure, reduces the side leakage of the PN junction, reduces the chip size, reduces the stress difference of the insulating dielectric layer on the top of the trench, and meets the strict requirements of advanced manufacturing.
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Figure CN119300368A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a TVS structure and a manufacturing method thereof. Background Art
[0002] The TVS (Transient voltage suppression) structure with deep trench isolation structure has N-type doped and P-type doped regions on the epitaxial layer isolated by deep trenches, and an insulating medium is formed inside and on the top of the deep trenches. The quality of the insulating medium is the key to ensuring the isolation performance and reliability of the device. The insulating medium of the current TVS structure with deep trench isolation structure often uses a single medium TEOS (tetraethoxysilane). Since TEOS is a loose material and the TVS structure often has large CO holes (holes formed during the manufacturing process), the top of the TEOS will crack due to stress after the entire front process is completed. Figure 1-Figure 3 As shown in the figure, they are the structural diagram of TVS structure, Figure 1 Partial schematic diagram of TVS structure and Figure 2 The SEM image of the TVS structure includes a semiconductor substrate 01, a substrate 011, an epitaxial layer 012, a first doped layer 013, a second doped layer 014, a groove 02, an insulating dielectric layer 03, a contact hole 04, a front lead electrode 05, a buffer layer 051, a metal electrode 052, a passivation layer 06, a first passivation layer 061, a second passivation layer 062, a lead hole 063 and a back lead electrode 07. The deep trench TEOS close to the P-type doping is subjected to greater stress due to the CO holes on both sides, so the cracking will be more serious. This problem will cause the isolation structure to fail, resulting in a reduction in yield.
[0003] In view of this, there is an urgent need for a method for manufacturing a TVS structure that can effectively improve the cracking problem of the insulating dielectric layer at the top of the deep trench in the TVS structure and improve the yield of the TVS structure. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a TVS structure and a manufacturing method thereof, so as to solve the problem that the insulating dielectric layer at the top of the deep trench in the TVS structure in the prior art is prone to cracking, resulting in low yield of the TVS structure.
[0005] To achieve the above object and other related objects, the present invention provides a method for manufacturing a TVS structure, comprising the following steps:
[0006] A semiconductor substrate is provided, wherein the semiconductor substrate comprises a first conductive type substrate, a second conductive type epitaxial layer located on an upper surface of the substrate, a first conductive type first doped layer and a second conductive type second doped layer located on an upper surface of the epitaxial layer, wherein the first doped layer and the second doped layer are arranged at intervals;
[0007] forming a trench penetrating the epitaxial layer and extending the bottom thereof into the substrate, wherein the trench is located between the first doped layer and the second doped layer;
[0008] Forming an insulating dielectric layer filling the trench and covering the upper surface of the epitaxial layer and forming a protective layer covering the upper surface of the insulating dielectric layer, and performing furnace tube reflow at a first preset temperature;
[0009] Contact holes are formed in the insulating dielectric layer and the protective layer, the bottoms of which respectively expose the first doped layer and the second doped layer, a front lead-out electrode is formed to fill the contact hole and cover the upper surface of the protective layer, and a rapid annealing treatment is performed at a second preset temperature.
[0010] Optionally, the material of the insulating dielectric layer includes tetraethyl orthosilicate.
[0011] Optionally, the first preset temperature ranges from 800°C to 880°C.
[0012] Optionally, a method of forming the protective layer includes chemical vapor deposition and physical vapor deposition.
[0013] Optionally, the material of the protective layer includes undoped silicon glass.
[0014] Optionally, the second preset temperature ranges from 450°C to 550°C.
[0015] Optionally, the front lead-out electrode includes a buffer layer and a lead-out electrode stacked in sequence, the buffer layer fills the contact hole and covers the upper surface of the protection layer, and the lead-out electrode covers the upper surface of the buffer layer.
[0016] Optionally, after the rapid annealing treatment, the method further includes forming a passivation layer covering the exposed surface of the front lead-out electrode, forming a lead-out hole in the passivation layer with the bottom exposing the upper surface of the front lead-out electrode, and forming a back lead-out electrode at the bottom of the substrate.
[0017] Optionally, the passivation layer includes the first passivation layer and the second passivation layer stacked in sequence, and the lead-out hole penetrates the first passivation layer and the second passivation layer.
[0018] The present invention also provides a TVS structure, which is manufactured by using any one of the above-mentioned methods for manufacturing the TVS structure.
[0019] As described above, the TVS structure and the manufacturing method thereof of the present invention have the following beneficial effects: by forming the groove penetrating the epitaxial layer and extending the bottom to the substrate, the first doped layer and the second doped layer are isolated by deep trench isolation, which reduces the side leakage of the PN junction while occupying a small area, and can greatly reduce the size of the chip; by forming the insulating dielectric layer in the groove and on the upper surface of the epitaxial layer, forming the protective layer above the insulating dielectric layer, and using undoped silicon glass as the protective layer, the protective layer has good thermal stability and compactness, and is easy to be formed in the subsequent process. In the method, the morphology of the upper surface of the insulating dielectric layer can be protected, and the subsequent stress difference can be prevented from causing the insulating dielectric layer to crack, thereby effectively improving the yield of the TVS structure; by performing rapid annealing at the second preset temperature, compared with the traditional high-temperature treatment, the reaction degree between the protective layer and the front lead-out electrode is reduced, and the stress difference of the insulating dielectric layer at the top of the groove is further reduced, thereby protecting the insulating dielectric layer at the top of the groove from cracking, solving the potential leakage and low-yield problem, and meeting the strict requirements of advanced TVS structure manufacturing through precise control of the temperature of the rapid annealing treatment. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic structural diagram of a TVS structure in the prior art.
[0021] Figure 2 Display as Figure 1 A partial schematic diagram of the TVS structure in FIG.
[0022] Figure 3 Display as Figure 2 SEM image of the TVS structure in.
[0023] Figure 4 Shown is a schematic diagram of the manufacturing process of the TVS structure of the present invention.
[0024] Figure 5 Shown is a schematic structural diagram of the TVS structure of the present invention.
[0025] Figure 6 Display as Figure 5 SEM image of the TVS structure.
[0026] Component number description
[0027] 01 Semiconductor substrate
[0028] 011 Substrate
[0029] 012 Epitaxial layer
[0030] 013 First doping layer
[0031] 014 Second doping layer
[0032] 02 Groove
[0033] 03 Insulation dielectric layer
[0034] 04 Contact hole
[0035] 05 Front lead electrode
[0036] 051 Buffer layer
[0037] 052 Metal Electrode
[0038] 06 Passivation layer
[0039] 061 First passivation layer
[0040] 062 Second passivation layer
[0041] 063 Lead-out hole
[0042] 07 Back side lead electrode
[0043] 1 Semiconductor substrate
[0044] 11 Substrate
[0045] 12 Epitaxial layer
[0046] 13. First doping layer
[0047] 14 Second doping layer
[0048] 2 Grooves
[0049] 3 Insulation dielectric layer
[0050] 4. Protective layer
[0051] 5 Contact holes
[0052] 6. Front lead electrode
[0053] 61 Buffer layer
[0054] 62 Metal Electrode
[0055] 7 Passivation layer
[0056] 71 First passivation layer
[0057] 72 Second passivation layer
[0058] 73 Lead-out hole
[0059] 8 Back lead electrode DETAILED DESCRIPTION
[0060] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0061] See also Figures 4 to 6 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.
[0062] Embodiment 1
[0063] This embodiment provides a method for manufacturing a TVS structure. Figure 4 As shown, it is a schematic diagram of the production process of the TVS structure, which includes the following steps:
[0064] S1: providing a semiconductor substrate, the semiconductor substrate comprising a first conductive type substrate, a second conductive type epitaxial layer located on an upper surface of the substrate, a first conductive type first doped layer located on an upper surface of the epitaxial layer, and a second conductive type second doped layer, wherein the first doped layer and the second doped layer are arranged at intervals;
[0065] S2: forming a trench penetrating the epitaxial layer and extending the bottom thereof into the substrate, wherein the trench is located between the first doped layer and the second doped layer;
[0066] S3: forming an insulating dielectric layer filling the trench and covering the upper surface of the epitaxial layer, and forming a protective layer covering the upper surface of the insulating dielectric layer, and performing furnace tube reflow at a first preset temperature;
[0067] S4: forming contact holes in the insulating dielectric layer and the protective layer, the bottoms of which respectively expose the first doped layer and the second doped layer, forming a front lead-out electrode filling the contact hole and covering the upper surface of the protective layer, and performing a rapid annealing process at a second preset temperature.
[0068] Specifically, steps S1-S2 are performed to provide a semiconductor substrate 1, wherein the semiconductor substrate 1 includes a first conductive type substrate 11, a second conductive type epitaxial layer 12 located on the upper surface of the substrate 11, a first conductive type first doped layer 13 and a second conductive type second doped layer 14 located on the upper surface of the epitaxial layer 12, wherein the first doped layer 13 and the second doped layer 14 are arranged at intervals; a groove 2 is formed that penetrates the epitaxial layer 12 and extends to the bottom of the substrate 11, and the groove 2 is located between the first doped layer 13 and the second doped layer 14.
[0069] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.
[0070] Specifically, the material of the substrate 11 includes silicon, silicon germanium, silicon carbide, gallium nitride or other suitable materials.
[0071] Specifically, under the condition that the performance of the TVS structure is met, the size and shape of the substrate 11 can be selected according to actual conditions and are not limited here.
[0072] Specifically, the material of the epitaxial layer 12 includes silicon or other suitable materials.
[0073] Specifically, the method of forming the first doping layer 13 includes ion implantation or other suitable methods; the method of forming the second doping layer 14 includes ion implantation or other suitable methods.
[0074] Specifically, the method of forming the trench 2 includes wet etching, dry etching or other suitable methods.
[0075] Specifically, the aspect ratio of the trench 2 is in the range of 10:1 to 20:1.
[0076] Specifically, under the condition that the performance of the TVS structure is met, the depth and width of the groove 2 can be selected according to the actual situation, and no limitation is made here. The depth here refers to the vertical distance between the groove opening and the groove bottom.
[0077] Specifically, step S3 is performed to form an insulating dielectric layer 3 filling the trench 2 and covering the upper surface of the epitaxial layer 12 and a protective layer 4 covering the upper surface of the insulating dielectric layer 3, and furnace reflow is performed at a first preset temperature.
[0078] Specifically, the method of forming the insulating dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0079] Specifically, the method of forming the insulating dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0080] As an example, the material of the insulating dielectric layer 3 includes tetraethyl orthosilicate or other suitable materials.
[0081] Specifically, by forming an insulating dielectric layer 3 that fills the groove 2 and covers the upper surfaces of the first doped layer 13 and the second doped layer 14, the side leakage of the PN junction is reduced, and the first doped layer 13 and the second doped layer 14 are isolated by deep trench isolation, which occupies a small area and can greatly reduce the size of the chip.
[0082] Specifically, the method for forming the protective layer 4 includes chemical vapor deposition, physical vapor deposition or other suitable methods. In this embodiment, the method for forming the protective layer 4 is chemical vapor deposition.
[0083] As an example, the material of the protection layer 4 includes undoped silica glass or other suitable materials.
[0084] Specifically, by forming a protective layer 4 on the insulating dielectric layer 3 and using undoped silicon glass as the protective layer, the protective layer 4 has good thermal stability and density. In the subsequent process, it can protect the morphology on the insulating dielectric layer 3 and prevent the subsequent stress difference from causing cracks in the insulating dielectric layer 3, thereby effectively improving the yield of the TVS structure.
[0085] As an example, the first preset temperature ranges from 800° C. to 880° C. In this embodiment, the first preset temperature is 850° C.
[0086] Specifically, the insulating dielectric layer 3 and the protective layer 4 are furnace-reflowed at a first preset temperature, and the insulating dielectric layer 3 is densified, thereby reducing defects in the insulating dielectric layer 3 and the protective layer 4, ensuring the filling quality of the groove 2, reducing stress problems in the insulating dielectric layer 3 and the protective layer 4, and improving the stability and reliability of the TVS structure.
[0087] For details, please refer to Figure 5-Figure 6 , execute step S4, form a contact hole 5 in the insulating dielectric layer 3 and the protective layer 4, the bottom of which exposes the first doping layer 13 and the second doping layer 14 respectively, form a front lead-out electrode 6 filling the contact hole 5 and covering the upper surface of the protective layer 4, and perform a rapid annealing treatment at a second preset temperature.
[0088] Specifically, the method of forming the contact hole 5 includes dry etching, wet etching or other suitable methods.
[0089] Specifically, a contact hole 5 is formed in the insulating dielectric layer 3 and the protective layer 4, the bottom of which exposes the first doped layer 13 and the second doped layer 14 respectively, and a front lead-out electrode 6 is formed in the contact hole 5 to fill the contact hole 5 and cover the upper surface of the protective layer 4, thereby ensuring that the current of the TVS structure is smoothly led out.
[0090] As an example, the front lead-out electrode 6 includes a buffer layer 61 and a metal electrode 62 stacked in sequence. The buffer layer 61 fills the contact hole 5 and covers the upper surface of the protection layer 4 , and the metal electrode 62 covers the upper surface of the buffer layer 61 .
[0091] Specifically, the material of the buffer layer 61 includes at least one of Ti and TiN or other suitable materials; the material of the metal electrode 62 includes at least one of Al, Si, Cu or other suitable conductive materials.
[0092] Specifically, the method of forming the buffer layer 61 includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method of forming the metal electrode 62 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0093] Specifically, by forming the buffer layer 61 filling the contact hole 5 and covering the upper surface of the protection layer 4 , the metal ions in the metal electrode 62 are prevented from diffusing into the first doping layer 13 and the second doping layer 14 , thereby improving the stability of the TVS structure.
[0094] As an example, the second preset temperature ranges from 450° C. to 550° C. In this embodiment, the second preset temperature is 480° C.
[0095] Specifically, by performing a rapid annealing treatment on the contact interface between the front lead-out electrode 6 and the protective layer 4 at a second preset temperature, compared with the traditional high-temperature treatment, the reaction degree between the protective layer 4 and the front lead-out electrode 6 is reduced, and the stress difference of the insulating dielectric layer 3 at the top of the groove 2 is reduced, and the insulating dielectric layer 3 at the top of the groove 2 is protected from cracking, thereby solving the potential leakage problem. Moreover, by precisely controlling the temperature of the rapid annealing treatment, the strict requirements for advanced TVS structure manufacturing are met.
[0096] As an example, Figure 5 As shown, it is a schematic diagram of the structure of the TVS structure. After the rapid annealing treatment, it also includes the steps of forming a passivation layer 7 covering the exposed surface of the front lead-out electrode 6, and forming a lead-out hole 73 in the passivation layer 7 with the bottom exposing the upper surface of the front lead-out electrode 6, and forming a back lead-out electrode 8 at the bottom of the substrate 11.
[0097] As an example, the passivation layer 7 includes a first passivation layer 71 and a second passivation layer 72 stacked in sequence, and the lead-out hole 73 penetrates the first passivation layer 71 and the second passivation layer 72 .
[0098] Specifically, the material of the first passivation layer 71 includes undoped silicon glass or other suitable materials; the material of the second passivation layer 72 includes silicon nitride or other suitable materials.
[0099] Specifically, the method of forming the first passivation layer 71 includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method of forming the second passivation layer 72 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0100] Specifically, the method of forming the lead-out hole 73 includes dry etching, wet etching or other suitable methods.
[0101] Specifically, the lead-out hole 73 is formed in the passivation layer 7 , and the bottom of the lead-out hole 63 exposes the upper surface of the front lead-out electrode 6 , which is convenient for subsequent testing and packaging wiring.
[0102] Specifically, the material of the back lead-out electrode 8 includes at least one of Al, Si, and Cu or other suitable conductive materials.
[0103] Specifically, the method of forming the back-side lead-out electrode 8 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0104] Specifically, Figure 6 As shown, Figure 5 In the SEM image of the TVS structure, the insulating dielectric layer 3 above the groove 2 is not cracked. Therefore, a protective layer 4 is formed above the insulating dielectric layer 3 to prevent the insulating dielectric layer 3 from cracking due to subsequent stress difference, thereby effectively improving the yield of the TVS structure.
[0105] The manufacturing method of the TVS structure of the present embodiment forms a trench 2 penetrating the epitaxial layer 12 and extending the bottom to the substrate 11, and isolates the first doped layer 13 and the second doped layer 14 by deep trench isolation, thereby reducing the side leakage of the PN junction and occupying a small area, which can greatly reduce the size of the chip; by forming a protective layer 4 on the insulating dielectric layer 3, and using undoped silicon glass as the protective layer 4, the protective layer 4 has good thermal stability and density, and can protect the top morphology of the insulating dielectric layer 3 in the subsequent process manufacturing, prevent the subsequent stress difference from causing the insulating dielectric layer 3 to crack, and effectively improve the yield of the TVS structure; by performing a rapid annealing treatment on the contact interface between the front lead-out electrode 6 and the protective layer 4 at a second preset temperature, compared with the traditional high-temperature treatment, the reaction degree between the protective layer 4 and the front lead-out electrode 6 is reduced, and the stress difference of the insulating dielectric layer 3 at the top of the trench 2 is further reduced, and the insulating dielectric layer 3 at the top of the trench 2 is protected from cracking, thereby solving the potential leakage problem, and by accurately controlling the temperature of the rapid annealing treatment, the strict requirements of advanced TVS structure manufacturing are met.
[0106] Embodiment 2
[0107] The present embodiment provides a TVS structure, which is manufactured by the manufacturing method of the TVS structure described in the first embodiment, and includes: a semiconductor substrate 1, a groove 2, an insulating dielectric layer 3, a protective layer 4, a contact hole 5 and a front lead-out electrode 6, wherein the semiconductor substrate 1 includes a first conductive type substrate 11, a second conductive type epitaxial layer 12 located on the upper surface of the substrate 11, a first conductive type first doped layer 13 located on the upper surface of the epitaxial layer 12, and a second conductive type second doped layer 14, wherein the first doped layer 13 and the second doped layer 14 are arranged alternately; the groove 2 penetrates the epitaxial layer 12 and the bottom extends into the substrate 11, and the groove 2 is located between the first doped layer 13 and the second doped layer 14; the insulating dielectric layer 3 fills the groove 2 and covers the upper surface of the epitaxial layer 12, and the protective layer 4 covers the upper surface of the insulating dielectric layer 3; the contact hole 5 is located in the insulating dielectric layer 3 and the protective layer 4, and the bottom exposes the first doped layer 13 and the second doped layer 14, respectively, and the front lead-out electrode 6 fills the first contact hole 5 and covers the upper surface of the protective layer 4.
[0108] Specifically, the front lead-out electrode 6 includes a buffer layer 61 and a metal electrode 62 which are stacked in sequence. The buffer layer 61 fills the contact hole 5 and covers the upper surface of the protection layer 4 , and the metal electrode 62 covers the upper surface of the buffer layer 61 .
[0109] Specifically, a passivation layer 7 is formed on the exposed surface of the front lead-out electrode 6 , and a lead-out hole 73 is formed in the passivation layer 7 , the bottom of which exposes the upper surface of the front lead-out electrode 6 . A back lead-out electrode 8 is also formed on the bottom of the substrate 11 .
[0110] Specifically, the passivation layer 7 includes a first passivation layer 71 and a second passivation layer 72 stacked in sequence, and the lead-out hole 73 penetrates the first passivation layer 71 and the second passivation layer 72 .
[0111] The TVS structure of this embodiment protects the morphology of the upper surface of the insulating dielectric layer 6 by providing a protective layer 4 covering the upper surface of the insulating dielectric layer 3, thereby preventing the insulating dielectric layer 6 from cracking due to subsequent stress difference, thereby effectively improving the yield of the TVS structure.
[0112] In summary, the TVS structure and its manufacturing method of the present invention form a groove that penetrates the epitaxial layer and extends to the substrate at the bottom, and isolates the first doped layer and the second doped layer by deep trench isolation, thereby reducing the side leakage of the PN junction while occupying a small area, which can greatly reduce the size of the chip; by forming a protective layer above the insulating dielectric layer, and using undoped silicon glass as the protective layer, the protective layer has good thermal stability and compactness, and in the subsequent process manufacturing, it can protect the top morphology of the insulating dielectric layer, prevent the subsequent stress difference from causing the insulating dielectric layer to crack, and effectively improve the yield of the TVS structure; by performing a rapid annealing treatment on the contact interface between the front lead-out electrode and the protective layer at a second preset temperature, compared with the traditional high-temperature treatment, the reaction degree between the protective layer and the front lead-out electrode is reduced, and the stress difference of the insulating dielectric layer at the top of the groove is further reduced, and the insulating dielectric layer at the top of the groove is protected from cracking, solving the potential leakage problem, and by accurately controlling the temperature of the rapid annealing treatment, the strict requirements of advanced TVS structure manufacturing are met. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0113] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a TVS structure, characterized in that: The following steps are involved: A semiconductor substrate is provided, wherein the semiconductor substrate comprises a first conductive type substrate, a second conductive type epitaxial layer located on an upper surface of the substrate, a first conductive type first doped layer and a second conductive type second doped layer located on an upper surface of the epitaxial layer, wherein the first doped layer and the second doped layer are arranged at intervals; forming a trench penetrating the epitaxial layer and extending the bottom thereof into the substrate, wherein the trench is located between the first doped layer and the second doped layer; Forming an insulating dielectric layer filling the trench and covering the upper surface of the epitaxial layer and forming a protective layer covering the upper surface of the insulating dielectric layer, and performing furnace tube reflow at a first preset temperature; Contact holes are formed in the insulating dielectric layer and the protective layer, the bottoms of which respectively expose the first doped layer and the second doped layer, a front lead-out electrode is formed to fill the contact hole and cover the upper surface of the protective layer, and a rapid annealing treatment is performed at a second preset temperature.
2. The method for manufacturing a TVS structure according to claim 1, characterized in that: The material of the insulating dielectric layer includes tetraethyl orthosilicate.
3. The method for manufacturing a TVS structure according to claim 1, characterized in that: The first preset temperature ranges from 800°C to 880°C.
4. The method for manufacturing a TVS structure according to claim 1, characterized in that: Methods for forming the protective layer include chemical vapor deposition and physical vapor deposition.
5. The method for manufacturing a TVS structure according to claim 1, characterized in that: The material of the protective layer includes undoped silica glass.
6. The method for manufacturing a TVS structure according to claim 1, characterized in that: The second preset temperature ranges from 450°C to 550°C.
7. The method for manufacturing a TVS structure according to claim 1, characterized in that: The front lead-out electrode includes a buffer layer and a lead-out electrode stacked in sequence, the buffer layer fills the contact hole and covers the upper surface of the protection layer, and the lead-out electrode covers the upper surface of the buffer layer.
8. The method for manufacturing a TVS structure according to claim 1, characterized in that: After the rapid annealing treatment, the method further includes forming a passivation layer covering the exposed surface of the front lead-out electrode, forming a lead-out hole in the passivation layer with the bottom exposing the upper surface of the front lead-out electrode, and forming a back lead-out electrode at the bottom of the substrate.
9. The method for manufacturing a TVS structure according to claim 8, characterized in that: The passivation layer includes the first passivation layer and the second passivation layer stacked in sequence, and the lead-out hole penetrates the first passivation layer and the second passivation layer.
10. A TVS structure, characterized in that: The TVS structure is manufactured by using the method for manufacturing a TVS structure according to any one of claims 1 to 9.