Solar cell and preparation method thereof

Abstract

The invention discloses a preparation method of a solar cell. The preparation method comprises the steps of providing a silicon substrate; forming a first tunneling oxide layer on the first surface of the silicon substrate; forming a first conductive type semiconductor layer on the first tunneling oxide layer; forming a first transparent conductive layer on the first conductive type semiconductor layer; forming a first metal electrode layer on the first transparent conductive layer, and forming ohmic contact between a first metal electrode in the first metal electrode layer and the first transparent conductive layer; forming a second tunneling oxide layer on the second surface of the silicon substrate; forming a second conductive type semiconductor layer on the second tunneling oxide layer; forming a second transparent conductive layer on the second conductive type semiconductor layer; and forming a second metal electrode layer on the second transparent conductive layer, and forming ohmic contact between a second metal electrode in the second metal electrode layer and the second transparent conductive layer. The invention also discloses a solar cell.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a method for preparing the solar cell. Background Art

[0002] In the process of preparing solar cells, factors such as dopants, process impurities and crystal defects of the film layer may cause abnormal recombination of electrons, holes and other carriers in various forms, thus seriously reducing the power generation efficiency of solar cells. At present, one of the important means to reduce carrier recombination is to achieve interface passivation by setting a passivation contact film structure.

[0003] However, for different types of solar cells, the structure setting mode, film material and preparation method of the passivation contact film used are significantly different, and cannot be directly converted and used. For example, the tunnel oxide passivated contact solar cell (TOPCon) requires the use of materials and equipment that can withstand high temperatures to prepare the passivation film; while the heterojunction solar cell (HJT) requires the use of materials and equipment that can withstand lower temperatures to prepare the passivation film.

[0004] How to provide a photovoltaic cell with a new structure that can make full use of the mature structure and manufacturing production line of existing photovoltaic cells, while enhancing and improving the passivation contact effect and reasonably controlling the preparation cost, has positive significance for further improving the market competitiveness of photovoltaic cells. Summary of the invention

[0005] The present application aims to solve one of the technical problems in the related art to a certain extent. To this end, the present application provides a solar cell and a method for preparing the solar cell.

[0006] In order to achieve the above object, the present application provides a method for preparing a solar cell, wherein the preparation method comprises:

[0007] Providing a silicon substrate, the silicon substrate having a first surface and a second surface, the first surface and the second surface being opposite to each other;

[0008] forming a first tunneling oxide layer on the first surface of the silicon substrate;

[0009] forming a first conductivity type semiconductor layer on the first tunneling oxide layer, wherein the first conductivity type is selected from one of a p-type and an n-type;

[0010] forming a first transparent conductive layer on the first conductive type semiconductor layer;

[0011] forming a first metal electrode layer on the first transparent conductive layer, and forming an ohmic contact between a first metal electrode in the first metal electrode layer and the first transparent conductive layer;

[0012] forming a second tunneling oxide layer on the second surface of the silicon substrate;

[0013] forming a second conductivity type semiconductor layer on the second tunneling oxide layer, wherein the second conductivity type is selected from the other of a p-type and an n-type;

[0014] forming a second transparent conductive layer on the second conductive type semiconductor layer;

[0015] A second metal electrode layer is formed on the second transparent conductive layer, and an ohmic contact is formed between a second metal electrode in the second metal electrode layer and the second transparent conductive layer.

[0016] Optionally, forming a first tunneling oxide layer on the first surface of the silicon substrate includes:

[0017] forming a first initial tunneling oxide layer on a first surface of the silicon substrate;

[0018] The first initial tunneling oxide layer is annealed to obtain the first tunneling oxide layer; the thickness of the first tunneling oxide layer is 1 nm to 5 nm.

[0019] Optionally, the process temperature for forming the first initial tunneling oxide layer on the first surface of the silicon substrate includes: 200° C. to 1050° C., and the first initial tunneling oxide layer is formed by any one of the following processes:

[0020] Atomic layer deposition process, thermal oxidation process, plasma enhanced chemical vapor deposition process, low pressure chemical vapor deposition and low temperature wet oxidation process;

[0021] The annealing temperature for annealing the first initial tunneling oxide layer includes 200°C to 800°C.

[0022] Optionally, forming a second tunneling oxide layer on the second surface of the silicon substrate comprises:

[0023] forming a second initial tunneling oxide layer on the second surface of the silicon substrate;

[0024] The second initial tunneling oxide layer is annealed to obtain the second tunneling oxide layer; the thickness of the second tunneling oxide layer is 1 nm to 5 nm.

[0025] Optionally, the process temperature for forming the second initial tunneling oxide layer on the second surface of the silicon substrate includes: 200° C. to 1050° C., and the second initial tunneling oxide layer is formed by any one of the following processes:

[0026] Atomic layer deposition process, thermal oxidation process, plasma enhanced chemical vapor deposition process, low pressure chemical vapor deposition and low temperature wet oxidation process;

[0027] The annealing temperature for annealing the second initial tunnel oxide layer includes 200° C. to 800° C.

[0028] Optionally, the first conductive type semiconductor layer is an n-type semiconductor layer, and forming the first conductive type semiconductor layer on the first tunneling oxide layer includes:

[0029] Phosphorus atoms, hydrogen atoms, and oxygen atoms are doped into the silicon thin film by using a set deposition process to obtain an n-type doped oxygen-containing amorphous silicon layer, wherein the set deposition process is selected from any one of a tubular plasma enhanced chemical vapor deposition process, a plate plasma enhanced chemical vapor deposition process, and a low-pressure chemical vapor deposition process;

[0030] Annealing and crystallizing the n-type doped oxygen-containing amorphous silicon layer to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductive type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer is 10 nm to 60 nm; wherein the process temperature of the deposition process is set to be 200° C. to 800° C.;

[0031] or,

[0032] Forming a first conductive type semiconductor layer on the first tunneling oxide layer, comprising:

[0033] A silicon film is deposited by a low-temperature atomic layer deposition process while phosphorus atoms, hydrogen atoms, and oxygen atoms are doped to obtain an n-type doped oxygen-containing amorphous silicon layer;

[0034] The n-type doped oxygen-containing amorphous silicon layer is annealed and crystallized to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductive type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer includes: 10nm to 60nm; wherein the process temperature of the low-temperature atomic layer deposition process includes: 100°C to 300°C.

[0035] Optionally, the second conductive type semiconductor layer is an n-type semiconductor layer, and forming the second conductive type semiconductor layer on the second tunneling oxide layer includes:

[0036] Phosphorus atoms, hydrogen atoms, and oxygen atoms are doped into the silicon thin film by using a set deposition process to obtain an n-type doped oxygen-containing amorphous silicon layer, wherein the set deposition process is selected from any one of a tubular plasma enhanced chemical vapor deposition process, a plate plasma enhanced chemical vapor deposition process, and a low-pressure chemical vapor deposition process;

[0037] Annealing and crystallizing the n-type doped oxygen-containing amorphous silicon layer to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductive type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer is 10 nm to 60 nm; wherein the process temperature of the deposition process is set to be 200° C. to 800° C.;

[0038] or,

[0039] Forming a second conductive type semiconductor layer on the second tunneling oxide layer, comprising:

[0040] A silicon film is deposited by a low-temperature atomic layer deposition process while phosphorus atoms, hydrogen atoms, and oxygen atoms are doped to obtain an n-type doped oxygen-containing amorphous silicon layer;

[0041] The n-type doped oxygen-containing amorphous silicon layer is annealed and crystallized to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the second conductive type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer includes: 10nm to 60nm; wherein the process temperature of the low-temperature atomic layer deposition process includes: 100°C to 300°C.

[0042] Optionally, forming a first metal electrode layer on the first transparent conductive layer includes:

[0043] Providing a metal paste, wherein the metal paste is selected from at least one of a low-temperature silver paste, a low-temperature copper paste, and a low-temperature silver-copper paste;

[0044] forming an initial first metal electrode layer on the first transparent conductive layer by a printing process;

[0045] A sintering and curing process is performed on the initial first metal electrode layer to form a first metal electrode layer including a first metal electrode, and the first metal electrode portion penetrates below the surface of the first transparent conductive layer to form an ohmic contact; wherein the process temperature of the sintering and curing process includes: 100°C to 200°C; the mass proportion of copper in the silver-copper paste includes (0%, 80%).

[0046] Optionally, forming a first metal electrode layer on the first transparent conductive layer includes:

[0047] forming a first copper seed layer on the first transparent conductive layer; the first copper seed layer partially penetrates below the surface of the first transparent conductive layer to form an ohmic contact;

[0048] forming a first patterned mask layer on the first copper seed layer, wherein the first patterned mask layer has a first opening pattern, and the first opening pattern matches the first metal electrode layer;

[0049] forming a copper material layer partially filling the first opening pattern;

[0050] forming a silver material layer covering the copper material layer and filling the first opening pattern;

[0051] The first patterned mask layer and the first copper seed layer not covered by the copper material layer are removed; the retained first copper seed layer, copper material layer and silver material layer together constitute the first metal electrode layer.

[0052] Optionally, forming a second metal electrode layer on the second transparent conductive layer includes:

[0053] Providing a metal paste, wherein the metal paste is selected from at least one of a low-temperature silver paste, a low-temperature copper paste, and a low-temperature silver-copper paste;

[0054] forming an initial second metal electrode layer on the second transparent conductive layer by a printing process;

[0055] A sintering and curing process is performed on the initial second metal electrode layer to form a second metal electrode layer including a second metal electrode, and the second metal electrode portion penetrates below the surface of the second transparent conductive layer to form an ohmic contact; wherein, in the silver-copper paste, the mass proportion of copper includes: (0%, 80%]; the process temperature of the sintering and curing process includes: 100°C to 200°C.

[0056] Optionally, forming a second metal electrode layer on the second transparent conductive layer includes:

[0057] forming a second copper seed layer on the second transparent conductive layer; the second copper seed layer partially penetrates below the surface of the second transparent conductive layer to form an ohmic contact;

[0058] forming a second patterned mask layer on the second copper seed layer, wherein the second patterned mask layer has a second opening pattern, and the second opening pattern matches the second metal electrode layer;

[0059] forming a copper material layer partially filling the second opening pattern;

[0060] forming a silver material layer covering the copper material layer and filling the second opening pattern;

[0061] The second patterned mask layer and the second copper seed layer not covered by the copper material layer are removed; the retained second copper seed layer, copper material layer and silver material layer together constitute the second metal electrode layer.

[0062] As a second aspect of the present application, a solar cell is provided, the solar cell comprising a silicon substrate, the silicon substrate having a first surface and a second surface opposite to each other; wherein the solar cell further comprises:

[0063] A first film layer group structure is arranged on the first surface side of the silicon substrate; the first film layer group structure includes a first tunneling oxide layer, a first conductive type semiconductor layer, a first transparent conductive layer and a first metal electrode layer;

[0064] The second film layer group structure is arranged on the second surface side of the silicon substrate, and the second film layer group structure includes a second tunneling oxide layer, a second conductive type semiconductor layer, a second transparent conductive layer and a second metal electrode layer.

[0065] The first tunneling oxide layer is arranged above the first surface, the first conductive type semiconductor layer is arranged above the surface of the first tunneling oxide layer away from the silicon substrate, the first transparent conductive layer is arranged above the surface of the first conductive type semiconductor layer away from the silicon substrate, and the first metal electrode layer is arranged above the surface of the first transparent conductive layer away from the first conductive type semiconductor layer; an ohmic contact is formed between the first metal electrode in the first metal electrode layer and the first transparent conductive layer;

[0066] The second tunneling oxide layer is arranged below the second surface, the second conductive type semiconductor layer is arranged on a side of the second tunneling oxide layer away from the second surface, the second transparent conductive layer is arranged on a side of the second conductive type semiconductor layer away from the second tunneling oxide layer, and the second metal electrode layer is arranged above a surface of the second transparent conductive layer away from the second conductive type semiconductor layer; an ohmic contact is formed between the second metal electrode in the second metal electrode layer and the second transparent conductive layer; the first conductive type is selected from one of p-type and n-type, and the second conductive type is selected from the other of p-type and n-type.

[0067] Optionally, the material of the first metal electrode forming the first metal electrode layer includes: at least one of low-temperature silver paste, low-temperature copper paste and low-temperature silver-copper paste;

[0068] The material of the second metal electrode forming the second metal electrode layer includes: at least one of low-temperature silver paste, low-temperature copper paste and low-temperature silver-copper paste;

[0069] The material of the first tunnel oxide layer and the material of the second tunnel oxide layer both include silicon dioxide, and the thickness of the first tunnel oxide layer and the thickness of the second tunnel oxide layer both include: 1 nm to 5 nm.

[0070] In the solar cell provided in the embodiment of the present application, the first tunneling oxide layer forms a passivation contact structure with the first conductive type semiconductor layer, and the first tunneling oxide layer reduces the interface state density between the silicon substrate and the first conductive type semiconductor layer by chemical passivation, and the high concentration of majority carriers (majority carriers) pass through in the form of quantum tunneling and block minority carriers (minority carriers), thereby reducing the probability of electron-hole recombination and increasing the conductivity, thereby forming a selective contact of majority carriers. Therefore, the passivation contact structure formed by the first tunneling oxide layer and the first conductive type semiconductor layer enables the solar cell to have good passivation capability and further improve the electrical performance of the solar cell (e.g., better open circuit voltage and fill factor).

[0071] Similarly, the second tunneling oxide layer forms a passivation contact structure with the second conductive type semiconductor layer. The second tunneling oxide layer reduces the interface state density between the silicon substrate and the second conductive type semiconductor layer by chemical passivation. The high concentration of majority carriers (majority carriers) pass through in the form of quantum tunneling and block minority carriers (minority carriers), thereby reducing the probability of electron-hole recombination and increasing the resistivity, thereby forming a selective contact of majority carriers. Therefore, the passivation contact structure formed by the second tunneling oxide layer and the second conductive type semiconductor layer enables the solar cell to have good passivation capability.

[0072] When preparing the first film layer group structure of the solar cell, the first transparent conductive layer is formed first, and then the first metal electrode layer is formed. The first transparent conductive layer has better carrier transport performance, so it only needs to burn through the surface layer of the first transparent conductive layer, that is, a good ohmic contact can be achieved between the first metal electrode in the first metal electrode layer and the first transparent conductive layer, without the need to use a higher sintering temperature to burn through the film layers located on the silicon substrate as a whole as in the related art to achieve direct electrical contact between the metal electrode and the silicon substrate. Accordingly, the degree of oxidation caused to the conductive paste forming the first metal electrode layer in the process method provided in the present application is also low, so that the first metal electrode of the first metal electrode layer finally obtained can have a lower resistivity, thereby improving the power generation efficiency of the solar cell. In addition, based on the low temperature of this step, relatively low-cost electrode materials such as low-temperature silver-copper paste can also be used to further reduce the preparation cost of solar cells.

[0073] Similarly, when preparing the second film layer group structure of the solar cell, the second transparent conductive layer is formed first, and then the second metal electrode layer is formed. Similarly, the second transparent conductive layer has better carrier transport performance, so it is only necessary to burn through the surface layer of the second transparent conductive layer, that is, to achieve good ohmic contact between the second metal electrode in the second metal electrode layer and the second transparent conductive layer, without the need to use a higher sintering temperature to burn through the film layers located on the silicon substrate as a whole, as in the related art, to achieve direct electrical contact between the metal electrode and the silicon substrate. Correspondingly, the degree of oxidation caused to the conductive paste forming the second metal electrode layer in the process method provided in the present application is also low, so that the second metal electrode of the second metal electrode layer finally obtained has a lower resistivity, and ultimately improves the power generation efficiency of the solar cell. In addition, based on the low temperature of this step, relatively low-cost electrode materials such as low-temperature silver-copper paste can also be used to further reduce the preparation cost of solar cells.

[0074] These features and advantages of the present application will be disclosed in detail in the following specific embodiments and drawings. The best embodiments or means of the present application will be described in detail in conjunction with the drawings, but they are not intended to limit the technical solutions of the present application. In addition, there are multiple features, elements, and components that appear in each of the following texts and drawings, and different symbols or numbers are marked for convenience, but they all represent components with the same or similar structures or functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] The present application is further described below in conjunction with the accompanying drawings:

[0076] Figure 1 A flow chart of an embodiment of the preparation method provided in this application;

[0077] Figure 2 is a flowchart of an implementation of step S120;

[0078] Figure 3 is a flowchart of an implementation of step S160;

[0079] Figure 4 is a flowchart of an implementation of step S130;

[0080] Figure 5 is a flowchart of another implementation of step S130;

[0081] Figure 6 is a flowchart of an implementation of step S150;

[0082] Figure 7 is a flowchart of another implementation of step S150;

[0083] Figure 8 is a flowchart of an implementation of step S190;

[0084] Fig. 9 is a flowchart of another implementation of step S190;

[0085] Fig.10 A schematic structural diagram of an implementation of a solar cell provided in the present application.

[0086] Description of Reference Numerals

[0087] 100: first film layer group structure 110: first tunneling oxide layer

[0088] 120: first conductive type semiconductor layer 130: first transparent conductive layer

[0089] 140: first metal electrode layer 141: first metal electrode

[0090] 200: second film layer group structure 210: second tunneling oxide layer

[0091] 220: second conductive type semiconductor layer 230: second transparent conductive layer

[0092] 240: second metal electrode layer 241: second metal electrode

[0093] 300: Silicon substrate DETAILED DESCRIPTION

[0094] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments based on the embodiments are intended to be used to explain the present application and cannot be understood as limiting the present application.

[0095] References in this specification to "one embodiment" or "an example" or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment itself may be included in at least one embodiment of the present patent disclosure. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily refer to the same embodiment.

[0096] As a first aspect of the present application, a method for preparing a solar cell is provided, wherein: Figure 1 As shown, the preparation method comprises:

[0097] In step S110, a silicon substrate is provided, wherein the silicon substrate has a first surface and a second surface, wherein the first surface and the second surface are opposite to each other;

[0098] In step S120, a first tunneling oxide layer is formed on the first surface of the silicon substrate;

[0099] In step S130, a first conductive type semiconductor layer is formed on the first tunneling oxide layer, and the first conductive type is selected from one of a p-type and an n-type;

[0100] In step S140, a first transparent conductive layer is formed on the first conductive type semiconductor layer;

[0101] In step S150, a first metal electrode layer is formed on the first transparent conductive layer, and an ohmic contact is formed between a first metal electrode in the first metal electrode layer and the first transparent conductive layer;

[0102] In step S160, a second tunneling oxide layer is formed on the second surface of the silicon substrate;

[0103] In step S170, a second conductivity type semiconductor layer is formed on the second tunneling oxide layer, wherein the second conductivity type is selected from the other of p-type and n-type;

[0104] In step S180, a second transparent conductive layer is formed on the second conductive type semiconductor layer;

[0105] In step S190, a second metal electrode layer is formed on the second transparent conductive layer, and an ohmic contact is formed between a second metal electrode in the second metal electrode layer and the second transparent conductive layer.

[0106] In the solar cell prepared in the embodiment of the present application, the first tunneling oxide layer forms a passivation contact structure with the first conductive type semiconductor layer, and the first tunneling oxide layer reduces the interface state density between the silicon substrate and the first conductive type semiconductor layer by chemical passivation, and the high concentration of majority carriers (majority carriers) pass through in the form of quantum tunneling and block minority carriers (minority carriers), thereby reducing the probability of electron-hole recombination and increasing the resistivity, thereby forming a selective contact of majority carriers. Therefore, the passivation contact structure formed by the second tunneling oxide layer and the first conductive type semiconductor layer can enable the solar cell to have good passivation capability.

[0107] Similarly, the second tunneling oxide layer forms a passivation contact structure with the second conductive type semiconductor layer. The second tunneling oxide layer reduces the interface state density between the silicon substrate and the second conductive type semiconductor layer by chemical passivation. The high concentration of majority carriers (majority carriers) pass through in the form of quantum tunneling and block minority carriers (minority carriers), thereby reducing the probability of electron-hole recombination and increasing the resistivity, thereby forming a selective contact of majority carriers. Therefore, the passivation contact structure formed by the second tunneling oxide layer and the second conductive type semiconductor layer enables the solar cell to have good passivation capability.

[0108] For the convenience of description, the film layer structure located on the first surface side of the silicon substrate is referred to as the "first film layer group structure", and the film layer structure located on the second surface side of the silicon substrate is referred to as the "second film layer group structure". It should be noted that the above names of "first film layer group structure" and "second film layer group structure" are only set for the convenience of description in the specification, and are not for type classification of the functional realization, preparation sequence, preparation process, etc. of the relevant film layers. For example, the first film layer group structure can be formed first, and then the second film layer group structure can be formed, or the second film layer group structure can be formed first, and then the first film layer group structure can be formed; alternatively, individual film layers in the first film layer group structure and individual film layers in the second film layer group structure can also be prepared simultaneously using the same preparation process.

[0109] When preparing the first film layer group structure of the solar cell, the first transparent conductive layer is formed first, and then the first metal electrode layer is formed. The first transparent conductive layer has better carrier transport performance, so it only needs to burn through the surface layer of the first transparent conductive layer, that is, a good ohmic contact can be achieved between the first metal electrode in the first metal electrode layer and the first transparent conductive layer, without the need to use a higher sintering temperature to burn through the film layers on the silicon substrate as a whole, as in the related art, to achieve direct electrical contact between the metal electrode and the silicon substrate, which means that the process temperature of step S150 is relatively low, and accordingly, the degree of oxidation caused to the conductive paste forming the first metal electrode layer during the process is also low, so that the first metal electrode of the first metal electrode layer finally obtained has a lower resistivity, thereby improving the power generation efficiency of the solar cell. In addition, based on the low temperature of this step, relatively low-cost electrode materials such as low-temperature silver-copper paste can also be used to further reduce the preparation cost of solar cells.

[0110] Similarly, when preparing the second film layer group structure of the solar cell, the second transparent conductive layer is formed first, and then the second metal electrode layer is formed. Similarly, the second transparent conductive layer has better carrier transport performance, so it is only necessary to burn through the surface layer of the second transparent conductive layer, that is, to achieve good ohmic contact between the second metal electrode in the second metal electrode layer and the second transparent conductive layer, without the need to use a higher sintering temperature to burn through the film layers located on the silicon substrate as a whole, as in the related art, to achieve direct electrical contact between the metal electrode and the silicon substrate. This means that the process temperature of step S190 is relatively low, and accordingly, the degree of oxidation caused by the conductive paste forming the second metal electrode layer during the process is also relatively low, so that the second metal electrode of the second metal electrode layer finally obtained has a lower resistivity, and ultimately improves the power generation efficiency of the solar cell. In addition, based on the low temperature of this step, relatively low-cost electrode materials such as low-temperature silver-copper paste can also be used to further reduce the preparation cost of solar cells.

[0111] In the embodiment of the present application, the specific structure of the silicon substrate is not particularly limited. For example, at least one of the first surface of the silicon substrate and the second surface of the silicon substrate may have a velvet structure. That is, in the step of providing the silicon substrate, the silicon substrate may be subjected to single-sided velveting or double-sided velveting.

[0112] In the embodiment of the present application, the first tunneling oxide layer is a silicon dioxide layer (ie, SiO2). As an optional implementation, Figure 2 As shown, forming a first tunneling oxide layer on the first surface of the silicon substrate includes:

[0113] In step S121, a first initial tunneling oxide layer is formed on a first surface of the silicon substrate;

[0114] In step S122, the first initial tunneling oxide layer is annealed to obtain the first tunneling oxide layer.

[0115] Optionally, the thickness of the first tunnel oxide layer is 1 nm to 5 nm.

[0116] It should be noted that the material of the first initial tunneling oxide layer includes silicon dioxide. In the embodiment of the present application, there is no special limitation on how to form the first initial tunneling oxide layer on the first surface of the silicon substrate. For example, a first initial tunneling oxide layer can be formed on the surface of the silicon substrate by chemical vapor deposition, and then the first tunneling oxide layer with a target thickness is finally obtained by annealing in step S122. In addition, the annealing process of the first initial tunneling oxide layer can remove some impurities (for example, remove iron elements) to a certain extent, so that the first tunneling oxide layer finally obtained has a higher purity and a denser and more uniform organization, thereby ensuring the tunneling effect.

[0117] As an optional embodiment, the process temperature for forming the first initial tunneling oxide layer on the first surface of the silicon substrate is between 200°C and 1050°C, and the first initial tunneling oxide layer can be formed by any one of the following processes: atomic layer deposition (ALD, Atomic Layer Deposition) process, thermal oxidation process, plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical VaporDeposition) process, low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical VaporDeposition) process, low temperature wet oxidation process, etc.

[0118] In the embodiment of the present application, there is no special limitation on the duration of step S122, as long as it can ensure that the first initial tunneling oxide layer with a thickness between 1 nm and 5 nm is obtained.

[0119] In an embodiment in which plasma enhanced chemical vapor deposition is used to prepare the first initial tunneling oxide layer, the grain size of the obtained first tunneling oxide layer reaches the micron level (for example, 50nm to 200nm) by annealing the first initial tunneling oxide layer. Compared with the related art, the grain size of the first tunneling oxide layer prepared in the present application is larger. Accordingly, the first tunneling oxide layer has a better light transmittance effect, and thus improves the short-wave response of the solar cell, thereby improving the light utilization rate of the solar cell.

[0120] In some embodiments, in step S122 , the annealing temperature for annealing the first initial tunneling oxide layer is between 200° C. and 800° C. By way of example, the annealing temperature includes: 200° C., 300° C., 400° C., 500° C., 600° C., 700° C., or 800° C.

[0121] In the embodiment of the present application, the organization and structure of the second tunneling oxide layer are the same. That is, the material of the second tunneling oxide layer is also silicon oxide (e.g., SiO2), and similar to the preparation of the first tunneling oxide layer, forming the second tunneling oxide layer on the second surface of the silicon substrate may include:

[0122] In step S161, a second initial tunneling oxide layer is formed on the second surface of the silicon substrate;

[0123] In step S162, the second initial tunneling oxide layer is annealed to obtain the second tunneling oxide layer; the thickness of the second tunneling oxide layer is 1 nm to 5 nm.

[0124] Optionally, the process temperature for forming the second initial tunneling oxide layer on the second surface of the silicon substrate includes: 200° C. to 1050° C., and the second initial tunneling oxide layer is formed by any one of the following processes:

[0125] Atomic layer deposition process, thermal oxidation process, plasma enhanced chemical vapor deposition process, low pressure chemical vapor deposition and low temperature wet oxidation process;

[0126] The annealing temperature for annealing the second initial tunnel oxide layer includes 200° C. to 800° C.

[0127] As described above, since the first conductivity type is selected from one of n-type and p-type, as an optional embodiment, the first conductivity type semiconductor layer is an n-type semiconductor layer. In addition, the present application also makes technical improvements to the preparation process of the first conductivity type semiconductor layer to improve its light transmittance, thereby ensuring and improving the power generation efficiency of the solar cell. For example, Figure 4 As shown, forming a first conductive type semiconductor layer on the first tunneling oxide layer includes:

[0128] In step S131, a silicon thin film is deposited by adopting a set deposition process while doping phosphorus atoms, hydrogen atoms, and oxygen atoms to obtain an n-type doped oxygen-containing amorphous silicon layer, wherein the set deposition process is selected from any one of a tubular plasma enhanced chemical vapor deposition process, a plate plasma enhanced chemical vapor deposition process, and a low pressure chemical vapor deposition process;

[0129] In step S132, the n-type doped oxygen-containing amorphous silicon layer is subjected to annealing and crystallization treatment to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductive type semiconductor layer.

[0130] In step S131, the doping elements include oxygen (O) atoms, and therefore, a small amount of silicon oxide will be formed in step S131. Therefore, the n-type doped oxygen-containing polycrystalline silicon layer obtained in step S132 will also form a small amount of silicon oxide. Accordingly, compared with the n-type doped polycrystalline silicon that does not contain oxygen, the n-type doped oxygen-containing polycrystalline silicon layer in the embodiment of the present application has a wider optical band gap and a higher light transmittance. Therefore, the n-type doped oxygen-containing polycrystalline silicon layer obtained by using steps S131 and S132 provided in the embodiment of the present application has a higher light transmittance, thereby being able to improve the power generation efficiency of the solar cell finally obtained.

[0131] In the embodiment of the present application, there is no special limitation on the process temperature of step S131. Optionally, the process temperature of the deposition process is set between 200°C and 800°C.

[0132] It is worth noting that the "low pressure chemical vapor deposition process" referred to in this step is a common term familiar to those skilled in the art, and is used to distinguish related processes according to the gas pressure range. For example, the gas pressure used in the low pressure chemical vapor deposition process is between 30Pa and 130Pa, such as 30Pa, 50Pa, 70Pa, 80Pa, 100Pa, 120Pa or 130Pa.

[0133] Optionally, the thickness of the first conductive type semiconductor layer is between 10 nm and 60 nm. In the embodiment of the present application, the duration of step S131 is not particularly limited, as long as the thickness of the obtained n-type doped oxygen-containing polysilicon layer is between 10 nm and 60 nm.

[0134] As another optional implementation, Figure 5 As shown, forming a first conductive type semiconductor layer on the first tunneling oxide layer includes:

[0135] In step S133, a silicon thin film is deposited by a low temperature atomic layer deposition process while phosphorus atoms, hydrogen atoms, and oxygen atoms are doped to obtain an n-type doped oxygen-containing amorphous silicon layer;

[0136] In step S134, the n-type doped oxygen-containing amorphous silicon layer is subjected to annealing and crystallization treatment to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductive type semiconductor layer.

[0137] Similarly, in step S133, the doping elements include oxygen (O) atoms, and a small amount of silicon oxide will be formed in step S133. Therefore, the n-type doped oxygen-containing polycrystalline silicon layer obtained in step S134 will also form a small amount of silicon oxide, making the optical band gap of the n-type doped oxygen-containing polycrystalline silicon layer wider, thereby obtaining a higher light transmittance.

[0138] It is worth noting that the "low temperature atomic layer deposition process" referred to in this step is a common term familiar to those skilled in the art, and is used to distinguish related processes according to the temperature range. For example, in step S133, the process temperature of the low temperature atomic layer deposition process is between 100°C and 300°C, for example, 100°C, 150°C, 200°C, 250°C or 300°C.

[0139] In the above embodiment, the thickness of the n-type doped oxygen-containing polysilicon layer obtained in step S134 ranges from 10 nm to 60 nm.

[0140] As an optional implementation, in step S180, a second conductive type semiconductor layer may be prepared by a second plate-type PECVD process. Specifically, step S170 is performed as follows:

[0141] The second conductive type semiconductor layer is obtained by depositing a silicon film while doping boron atoms, hydrogen atoms and oxygen atoms using a second type plate-type plasma enhanced chemical vapor deposition process.

[0142] That is, hydrogen (H) atoms, boron (B) atoms, and oxygen (O) atoms are doped during the process of depositing a microcrystalline silicon film or a nanocrystalline silicon film.

[0143] Optionally, the deposition temperature range of the second type plate-type plasma enhanced chemical vapor deposition process includes: 100° C. to 200° C. The thickness of the second conductive type semiconductor layer is between 5 nm and 30 nm.

[0144] As an optional implementation, Figure 6 As shown, a first metal electrode layer is formed on the first transparent conductive layer, comprising:

[0145] In step S151, a metal paste is provided, wherein the metal paste is selected from at least one of a low-temperature silver paste, a low-temperature copper paste, and a low-temperature silver-copper paste;

[0146] Here, the "low temperature" slurry is a general term familiar to those skilled in the art, and is used to distinguish metal slurries with different sintering temperature ranges. For example, the sintering temperature of low temperature slurry is generally below 200°C; the sintering temperature of high temperature slurry is generally greater than 500°C.

[0147] In step S152, an initial first metal electrode layer is formed on the first transparent conductive layer by a printing process;

[0148] In step S153, a sintering and curing process is performed on the initial first metal electrode layer to form a first metal electrode layer including a first metal electrode, and the first metal electrode portion penetrates below the surface of the first transparent conductive layer to form an ohmic contact; wherein the process temperature of the sintering and curing process includes: 100°C to 200°C; the mass proportion of copper in the silver-copper paste includes: (0%, 80%], that is, the mass proportion of copper in the silver-copper paste falls within the range of 0% to 80%, and does not include 0%.

[0149] In this step, by controlling parameters such as the sintering temperature and sintering time, it can be ensured that the first metal electrode only partially penetrates below the surface of the first transparent conductive layer without burning through the entire first transparent conductive layer.

[0150] As another optional implementation, Figure 7 As shown, a first metal electrode layer is formed on the first transparent conductive layer, comprising:

[0151] In step S154, a first copper seed layer is formed on the first transparent conductive layer; the first copper seed layer partially intrudes below the surface of the first transparent conductive layer to form an ohmic contact;

[0152] In this step, by controlling the deposition depth of the first copper seed layer, it can be ensured that the first copper seed layer only partially intrudes below the surface of the first transparent conductive layer.

[0153] In step S155, a first patterned mask layer is formed on the first copper seed layer, wherein the first patterned mask layer has a first opening pattern, and the first opening pattern matches the first metal electrode layer;

[0154] In step S156, a copper material layer partially filling the first opening pattern is formed;

[0155] In step S157, a silver material layer is formed to cover the copper material layer and fill the first opening pattern;

[0156] In step S158, the first patterned mask layer and the first copper seed layer not covered by the copper material layer are removed; the retained first copper seed layer, copper material layer and silver material layer together constitute the first metal electrode layer.

[0157] Similarly, if Figure 8 As shown, forming a second metal electrode layer on the second transparent conductive layer includes:

[0158] In step S191, a metal paste is provided, wherein the metal paste is selected from at least one of a low-temperature silver paste, a low-temperature copper paste, and a low-temperature silver-copper paste;

[0159] Here, the "low temperature" slurry is a common sense term familiar to those skilled in the art, used to distinguish metal slurries with different sintering temperature ranges. For example, the sintering temperature of low temperature slurry is usually below 200°C, while the sintering temperature of high temperature slurry is generally greater than 500°C.

[0160] In step S192, an initial second metal electrode layer is formed on the second transparent conductive layer by a printing process;

[0161] In step S193, the initial second metal electrode layer is subjected to a sintering and curing process to form the second metal electrode layer including the second metal electrode, and the second metal electrode partially intrudes below the surface of the second transparent conductive layer to form an ohmic contact. In the silver-copper paste, the mass proportion of copper includes: (0%, 80%], that is, the mass proportion of copper in the silver-copper paste falls within the range of 0% to 80%, and does not include 0%; the process temperature of the sintering and curing process includes: 100°C to 200°C.

[0162] In this step, by controlling parameters such as the sintering temperature and sintering time, it can be ensured that the second metal electrode only partially penetrates below the surface of the second transparent conductive layer without burning through the entire second transparent conductive layer.

[0163] As another optional implementation, Fig. 9 As shown, forming a second metal electrode layer on the second transparent conductive layer includes:

[0164] In step S194, a second copper seed layer is formed on the second transparent conductive layer; the second copper seed layer partially intrudes below the surface of the second transparent conductive layer to form an ohmic contact;

[0165] In this step, by controlling the deposition depth of the first copper seed layer, it can be ensured that the first copper seed layer only partially intrudes below the surface of the first transparent conductive layer.

[0166] In step S195, a second patterned mask layer is formed on the second copper seed layer, wherein the second patterned mask layer has a second opening pattern, and the second opening pattern matches the second metal electrode layer;

[0167] In step S196, a copper material layer partially filling the second opening pattern is formed;

[0168] In step S197, a silver material layer is formed to cover the copper material layer and fill the second opening pattern;

[0169] In step S198, the second patterned mask layer and the second copper seed layer not covered by the copper material layer are removed; the retained second copper seed layer, copper material layer and silver material layer together constitute the second metal electrode layer.

[0170] By using the photovoltaic cell and photovoltaic cell preparation method provided in the embodiments of the present application, the precision requirements for the equipment to deposit thin films are reduced when preparing the tunnel oxide layer and the first conductive type semiconductor layer, and the tubular PECVD equipment currently in the field of Topcon cell preparation can be fully utilized to effectively reduce the preparation cost. Through calculations: 50% of TOPCon cell manufacturing equipment and 50% of HJT cell manufacturing equipment can be used, and the equipment investment cost is RMB 200 million / GW. In comparison, the equipment investment cost of traditional HJT cells is RMB 300 million / GW.

[0171] In addition, since the solar cell provided in the embodiment of the present application uses grains with a larger micron grain size than those prepared by PECVD in conventional HJT to form a tunneling oxide layer (e.g., a first tunneling oxide layer and a second tunneling oxide layer), it can provide a conductive performance that is superior to that of conventional HJT cells. Furthermore, since the front surface of the solar cell uses oxygen-containing polysilicon to passivate the front surface electrode, it can also provide a passivation effect that is superior to that of the emitter prepared by the diffusion method on the front surface of a conventional Topcon cell.

[0172] Traditional HJT cells use an intrinsic amorphous silicon layer for passivation on the light-entering surface of the silicon wafer (i.e., the first surface referred to in this application), and its silicon-hydrogen bond is weak, which will break under ultraviolet light irradiation, resulting in ultraviolet light attenuation. In this application, a tunneling oxide layer (such as an n-type silicon oxide layer) is used to passivate the front surface, effectively reflecting ultraviolet light and maintaining its own performance stability, thereby effectively improving the anti-ultraviolet light attenuation performance of the solar cell.

[0173] As a second aspect of the present application, a solar cell is provided, such as Fig.10 As shown, the solar cell includes a silicon substrate 300, a first film layer group structure 100 disposed on a first surface of the silicon substrate 300, and a second film layer group structure 200 disposed on a second surface of the silicon substrate 100, wherein the first surface and the second surface are opposite to each other.

[0174] The first film layer group structure 100 includes a first tunneling oxide layer 110, a first conductive type semiconductor layer 120, a first transparent conductive layer 130 and a first metal electrode layer 140, wherein the first tunneling oxide layer 110 is disposed on the first surface of the silicon substrate 300, the first conductive type semiconductor layer 120 is disposed on the surface of the first tunneling oxide layer 110 away from the silicon substrate 300, the first transparent conductive layer 130 is disposed on the surface of the first conductive type semiconductor layer 120 away from the first tunneling oxide layer 110, the first metal electrode layer 140 is disposed on the surface of the first transparent conductive layer 130 away from the first conductive type semiconductor layer 120, and an ohmic contact is formed between the first metal electrode in the first metal electrode layer 140 and the first transparent conductive layer 130. It should be noted that the "first conductive type" mentioned above is selected from one of p-type and n-type.

[0175] The second film layer group structure 200 may include a second tunneling oxide layer 210 , a second conductive type semiconductor layer, a second transparent conductive layer 230 , and a second metal electrode layer 240 .

[0176] The second tunneling oxide layer 210 is disposed below the second surface of the silicon substrate 300, the second conductive type semiconductor layer 220 is disposed on the side of the second tunneling oxide layer 210 away from the silicon substrate 300, the second transparent conductive layer 230 is disposed on the side of the second conductive type semiconductor layer 220 away from the second tunneling oxide layer 210, the second metal electrode layer 240 is disposed above the surface of the second transparent conductive layer 230 away from the second conductive type semiconductor layer 220, and an ohmic contact is formed between the second metal electrode in the second metal electrode layer 240 and the second transparent conductive layer 230. Wherein, the "second conductive type" is selected from the other of the p-type and the n-type. For example, the first conductive type is set to be the p-type and the second conductive type is the n-type.

[0177] In the solar cell provided in the embodiment of the present application, the first tunneling oxide layer 110 forms a passivation contact structure with the first conductive type semiconductor layer 120. The first tunneling oxide layer 110 reduces the interface state density between the silicon substrate 300 and the first conductive type semiconductor layer 120 by chemical passivation. The high concentration of majority carriers (majority carriers) passes through in the form of quantum tunneling and blocks minority carriers (minority carriers), thereby reducing the probability of electron-hole recombination and increasing the conductivity, thereby forming a selective contact of majority carriers. Therefore, the passivation contact structure formed by the first tunneling oxide layer 110 and the first conductive type semiconductor layer 120 enables the solar cell to have good passivation capability.

[0178] When preparing the first film layer group structure of the solar cell, the first transparent conductive layer 130 is formed first, and then the first metal electrode layer 140 is formed. When preparing the first metal electrode layer 140, it is only necessary to melt the electrode paste and burn through the surface layer of the first transparent conductive layer 130 to achieve ohmic contact between the first metal electrode 141 in the first metal electrode layer 140 and the first transparent conductive layer 130. The temperature required to burn through the surface layer of the first transparent conductive layer 130 is relatively low, that is, the process temperature for forming the first metal electrode layer 140 is relatively low, so that the degree of oxidation caused by the conductive paste for forming the first metal electrode layer 140 is also relatively low, so that the first metal electrode of the first metal electrode layer 140 finally obtained has a lower resistivity, thereby improving the power generation efficiency of the solar cell. In addition, based on the low temperature for forming the first metal electrode layer 140, relatively low-cost electrode materials such as low-temperature silver-copper paste can also be used to further reduce the preparation cost of the solar cell.

[0179] Similarly, the second tunneling oxide layer 210 forms a passivation contact structure with the second conductive type semiconductor layer 220. The second tunneling oxide layer 210 reduces the interface state density between the silicon substrate 300 and the second conductive type semiconductor layer 220 by chemical passivation. The high concentration of majority carriers (majority carriers) pass through in the form of quantum tunneling and block minority carriers (minority carriers), thereby reducing the probability of electron-hole recombination and increasing the conductivity, thereby forming a selective contact of majority carriers. Therefore, the passivation contact structure formed by the second tunneling oxide layer 210 and the second conductive type semiconductor layer 220 enables the solar cell to have good passivation capability.

[0180] When preparing the second film layer group structure of the solar cell, the second transparent conductive layer 230 is formed first, and then the second metal electrode layer 240 is formed. When preparing the second metal electrode layer 240, it is only necessary to melt the electrode paste and burn through the surface layer of the second transparent conductive layer 230 instead of burning through the entire second transparent conductive layer 230, so as to achieve ohmic contact between the second metal electrode 241 in the second metal electrode layer 240 and the second transparent conductive layer 230. The temperature required to burn through the surface layer of the second transparent conductive layer 230 is relatively low, that is, the process temperature for forming the second metal electrode layer 240 is relatively low, so that the degree of oxidation caused by the conductive paste for forming the second metal electrode layer 240 is also relatively low, so that the second metal electrode 241 of the second metal electrode layer 240 finally obtained has a lower resistivity, thereby improving the power generation efficiency of the solar cell. In addition, based on the low temperature for forming the second metal electrode layer 240, relatively low-cost electrode materials such as low-temperature silver-copper paste can also be used to further reduce the preparation cost of the solar cell.

[0181] That is to say, the present application can use tubular PECVD, ALD equipment, etc. to prepare the relevant film layers in the first film layer group structure of the solar cell (including at least the first tunneling oxide layer 110 and the first conductive type semiconductor layer 120), which can bring better cost advantages compared to the plate PECVD equipment used in the HJT process. Through calculation, the present application can continue to use 50% of TOPCon battery manufacturing equipment and 50% of HJT battery manufacturing equipment, with an equipment investment cost of 200 million yuan / GW. In comparison, the equipment investment cost of traditional HJT batteries is 300 million yuan / GW.

[0182] As an optional implementation, the first transparent conductive layer 130 may be made of a TCO material (eg, ITO or AZO).

[0183] Accordingly, the first metal electrode layer 140 includes a plurality of first metal electrodes 141. To reduce the cost, the material of the first metal electrode 141 may be silver and / or copper. In other words, the first metal electrode layer 140 may be prepared by using at least one of low-temperature silver paste, low-temperature silver-copper paste, and low-temperature copper paste, thereby reducing the material cost of the metal electrode.

[0184] The second metal electrode layer 240 includes a plurality of second metal electrodes 242. To reduce the cost, the material of the second metal electrode 242 may be silver and / or copper. In other words, the second metal electrode layer 240 may be prepared by using at least one of low-temperature silver paste, low-temperature silver-copper paste, and low-temperature copper paste, thereby reducing the material cost of the metal electrode.

[0185] In the above embodiments, the "low temperature" slurry is a common sense term familiar to those skilled in the art, and is used to distinguish metal slurries with different sintering temperature ranges. For example, the sintering temperature of the low temperature slurry is usually below 200°C, while the sintering temperature of the high temperature slurry is generally greater than 500°C.

[0186] In the embodiment of the present application, the silicon substrate 300 may be an n-type silicon substrate, and accordingly, the first conductive type semiconductor layer 120 may be an n-type oxygen-containing polycrystalline silicon layer. In other words, the first metal electrode layer 240 may be prepared by using at least one of a low-temperature silver paste, a low-temperature silver-copper paste, and a low-temperature copper paste, thereby reducing the material cost of the metal electrode.

[0187] Optionally, the thickness of the first conductive type semiconductor layer is between 10 nm and 60 nm.

[0188] Optionally, the material of the first tunnel oxide layer 110 is silicon dioxide, and the thickness of the first tunnel oxide layer 110 is between 1 nm and 5 nm.

[0189] In an optional embodiment, the first tunneling oxide layer 110 and the second tunneling oxide layer 210 are both composed of a silicon dioxide layer, which has a denser film structure and a higher tolerance to ultraviolet light (for example, having a more stable chemical property under ultraviolet radiation). Therefore, both the first surface and the second surface of the silicon substrate 300 can be the light incident surface of the solar cell, thereby reducing the ultraviolet attenuation characteristics of the solar cell and improving the light utilization rate of the solar cell.

[0190] As an optional embodiment, the first conductive type semiconductor layer 120 is an n-type polycrystalline silicon layer (ie, n-μc-Si:H layer), and the second conductive type semiconductor layer 220 is a p-type microcrystalline silicon layer (ie, p-μc-Si:H layer).

[0191] Optionally, the thickness of the second conductive type semiconductor layer 220 is between 5 nm and 30 nm.

[0192] Of course, the present invention is not limited thereto. For example, the first conductive type semiconductor layer 120 may be a p-type polysilicon layer (ie, a p-Poly-Si layer), and the second conductive type semiconductor layer 220 may be an n-type polysilicon layer (ie, an n-Poly-Si layer).

[0193] In the embodiment of the present application, the specific form of the silicon substrate 300 is not particularly limited. For example, at least one of the first surface and the second surface of the silicon substrate 300 may have a suede structure.

[0194] The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Those skilled in the art should understand that the present application includes but is not limited to the contents described in the drawings and the above specific embodiments. Any modification that does not deviate from the functional and structural principles of the present application will be included in the scope of the claims.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises: Providing a silicon substrate, the silicon substrate having a first surface and a second surface, the first surface and the second surface being opposite to each other; forming a first tunneling oxide layer on the first surface of the silicon substrate; forming a first conductivity type semiconductor layer on the first tunneling oxide layer, wherein the first conductivity type is selected from one of a p-type and an n-type; forming a first transparent conductive layer on the first conductive type semiconductor layer; forming a first metal electrode layer on the first transparent conductive layer, and forming an ohmic contact between a first metal electrode in the first metal electrode layer and the first transparent conductive layer; forming a second tunneling oxide layer on the second surface of the silicon substrate; forming a second conductivity type semiconductor layer on the second tunneling oxide layer, wherein the second conductivity type is selected from the other of a p-type and an n-type; forming a second transparent conductive layer on the second conductive type semiconductor layer; A second metal electrode layer is formed on the second transparent conductive layer, and an ohmic contact is formed between a second metal electrode in the second metal electrode layer and the second transparent conductive layer.

2. The preparation method according to claim 1, characterized in that: Forming a first tunneling oxide layer on the first surface of the silicon substrate comprises: forming a first initial tunneling oxide layer on a first surface of the silicon substrate; The first initial tunneling oxide layer is annealed to obtain the first tunneling oxide layer; the thickness of the first tunneling oxide layer is 1 nm to 5 nm.

3. The preparation method according to claim 2, characterized in that: The process temperature for forming the first initial tunneling oxide layer on the first surface of the silicon substrate includes: 200° C. to 1050° C., and the first initial tunneling oxide layer is formed by any one of the following processes: Atomic layer deposition process, thermal oxidation process, plasma enhanced chemical vapor deposition process, low pressure chemical vapor deposition and low temperature wet oxidation process; The annealing temperature for annealing the first initial tunnel oxide layer includes 200° C. to 800° C.

4. The preparation method according to claim 1, characterized in that: Forming a second tunneling oxide layer on the second surface of the silicon substrate comprises: forming a second initial tunneling oxide layer on the second surface of the silicon substrate; The second initial tunneling oxide layer is annealed to obtain the second tunneling oxide layer; the thickness of the second tunneling oxide layer is 1 nm to 5 nm.

5. The preparation method according to claim 4, characterized in that: The process temperature for forming the second initial tunneling oxide layer on the second surface of the silicon substrate includes: 200° C. to 1050° C., and the second initial tunneling oxide layer is formed by any one of the following processes: atomic layer deposition process, thermal oxidation process, plasma enhanced chemical vapor deposition process, low pressure chemical vapor deposition process and low temperature wet oxidation process; The annealing temperature for annealing the second initial tunnel oxide layer includes 200° C. to 800° C.

6. The preparation method according to claim 1, characterized in that: The first conductive type semiconductor layer is an n-type semiconductor layer, and the first conductive type semiconductor layer is formed on the first tunneling oxide layer, comprising: Phosphorus atoms, hydrogen atoms, and oxygen atoms are doped into the silicon thin film by using a set deposition process to obtain an n-type doped oxygen-containing amorphous silicon layer, wherein the set deposition process is selected from any one of a tubular plasma enhanced chemical vapor deposition process, a plate plasma enhanced chemical vapor deposition process, and a low-pressure chemical vapor deposition process; Annealing and crystallizing the n-type doped oxygen-containing amorphous silicon layer to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductive type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer is 10 nm to 60 nm; wherein the process temperature of the deposition process is set to be 200° C. to 800° C.; or, Forming a first conductive type semiconductor layer on the first tunneling oxide layer, comprising: A silicon film is deposited by a low-temperature atomic layer deposition process while phosphorus atoms, hydrogen atoms, and oxygen atoms are doped to obtain an n-type doped oxygen-containing amorphous silicon layer; The n-type doped oxygen-containing amorphous silicon layer is annealed and crystallized to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductive type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer includes: 10nm to 60nm; wherein the process temperature of the low-temperature atomic layer deposition process includes: 100°C to 300°C.

7. The preparation method according to any one of claims 1 to 6, characterized in that: Forming a first metal electrode layer on the first transparent conductive layer, comprising: Providing a metal paste, wherein the metal paste is selected from at least one of a low-temperature silver paste, a low-temperature copper paste, and a low-temperature silver-copper paste; forming an initial first metal electrode layer on the first transparent conductive layer by a printing process; The initial first metal electrode layer is subjected to a sintering and curing process to form a first metal electrode layer including a first metal electrode, and the first metal electrode portion is caused to intrude below the surface of the first transparent conductive layer to form an ohmic contact; wherein the process temperature of the sintering and curing process includes: 100° C. to 200° C.; the mass proportion of copper in the silver-copper paste includes (0% to 80%]; or, Forming a first metal electrode layer on the first transparent conductive layer, comprising: forming a first copper seed layer on the first transparent conductive layer; the first copper seed layer partially penetrates below the surface of the first transparent conductive layer to form an ohmic contact; forming a first patterned mask layer on the first copper seed layer, wherein the first patterned mask layer has a first opening pattern, and the first opening pattern matches the first metal electrode layer; forming a copper material layer partially filling the first opening pattern; forming a silver material layer covering the copper material layer and filling the first opening pattern; The first patterned mask layer and the first copper seed layer not covered by the copper material layer are removed; the retained first copper seed layer, copper material layer and silver material layer together constitute the first metal electrode layer.

8. The preparation method according to any one of claims 1 to 6, characterized in that: Forming a second metal electrode layer on the second transparent conductive layer, comprising: Providing a metal paste, wherein the metal paste is selected from at least one of a low-temperature silver paste, a low-temperature copper paste, and a low-temperature silver-copper paste; forming an initial second metal electrode layer on the second transparent conductive layer by a printing process; The initial second metal electrode layer is subjected to a sintering and curing process to form a second metal electrode layer including a second metal electrode, and the second metal electrode partially intrudes below the surface of the second transparent conductive layer to form an ohmic contact; wherein the mass proportion of copper in the silver-copper paste includes: (0% to 80%); the process temperature of the sintering and curing process includes: 100° C. to 200° C.; or, Forming a second metal electrode layer on the second transparent conductive layer, comprising: forming a second copper seed layer on the second transparent conductive layer; the second copper seed layer partially penetrates below the surface of the second transparent conductive layer to form an ohmic contact; forming a second patterned mask layer on the second copper seed layer, wherein the second patterned mask layer has a second opening pattern, and the second opening pattern matches the second metal electrode layer; forming a copper material layer partially filling the second opening pattern; forming a silver material layer covering the copper material layer and filling the second opening pattern; The second patterned mask layer and the second copper seed layer not covered by the copper material layer are removed; the retained second copper seed layer, copper material layer and silver material layer together constitute the second metal electrode layer.

9. A solar cell, comprising a silicon substrate, wherein the silicon substrate has a first surface and a second surface opposite to each other; characterized in that: Also includes: A first film layer group structure is arranged on the first surface side of the silicon substrate; The first film layer group structure includes a first tunneling oxide layer, a first conductive type semiconductor layer, a first transparent conductive layer and a first metal electrode layer; A second film layer group structure is arranged on the second surface side of the silicon substrate, the second film layer group structure comprising a second tunneling oxide layer, a second conductive type semiconductor layer, a second transparent conductive layer and a second metal electrode layer; in, The first tunneling oxide layer is arranged above the first surface, the first conductive type semiconductor layer is arranged above the surface of the first tunneling oxide layer away from the silicon substrate, the first transparent conductive layer is arranged above the surface of the first conductive type semiconductor layer away from the silicon substrate, and the first metal electrode layer is arranged above the surface of the first transparent conductive layer away from the first conductive type semiconductor layer; an ohmic contact is formed between the first metal electrode in the first metal electrode layer and the first transparent conductive layer; The second tunneling oxide layer is arranged below the second surface, the second conductive type semiconductor layer is arranged on a side of the second tunneling oxide layer away from the second surface, the second transparent conductive layer is arranged on a side of the second conductive type semiconductor layer away from the second tunneling oxide layer, and the second metal electrode layer is arranged above a surface of the second transparent conductive layer away from the second conductive type semiconductor layer; an ohmic contact is formed between the second metal electrode in the second metal electrode layer and the second transparent conductive layer; the first conductive type is selected from one of p-type and n-type, and the second conductive type is selected from the other of p-type and n-type.

10. The solar cell according to claim 9, characterized in that: The material of the first metal electrode forming the first metal electrode layer includes: at least one of low-temperature silver paste, low-temperature copper paste and low-temperature silver-copper paste; The material of the second metal electrode forming the second metal electrode layer includes: at least one of low-temperature silver paste, low-temperature copper paste and low-temperature silver-copper paste; The material of the first tunnel oxide layer and the material of the second tunnel oxide layer both include silicon dioxide, and the thickness of the first tunnel oxide layer and the thickness of the second tunnel oxide layer both include: 1 nm to 5 nm.

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