Array substrate, display panel and display panel mother board

Abstract

The invention relates to an array substrate, a display panel and a display panel mother board. The array substrate comprises a substrate, a scanning line, a gate drive circuit, a gate test pad and an intermediate redundant gate test pad. The substrate has a display area and a non-display area. The non-display area is arranged around the display area and comprises a binding area. The binding area is located on one side of the display area in the first direction. The binding area comprises two outer binding areas and a middle binding area. In the second direction, the middle binding area is located between the two outer binding areas. The first direction intersects the second direction. The scanning lines are located on the substrate of the display area. The gate drive circuit is connected with the scanning line. The gate test pad is located in the non-display area, is adjacent to at least one outer binding area, and is connected with the gate drive circuit. The middle redundant gate test pad is located in the non-display area, is adjacent to the middle binding area and is insulated from the gate drive circuit. According to the design of the array substrate, the exposure times of the mask plate in the manufacturing process of the array substrate and the display panel can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display panel motherboard. Background Art

[0002] With the development of the TV panel industry and market demand, the TV panel industry is moving towards larger sizes. For large-size TV panels, due to the limitation of mask size, splicing is required to complete exposure in order to produce large-size TV panels. Therefore, a huge exposure capacity is required to support the production of large-size panels. Summary of the invention

[0003] The embodiments of the present application provide an array substrate, a display panel, and a display panel motherboard, which are beneficial to reducing the number of exposure times of the mask during the manufacturing process of the array substrate and the display panel, so as to at least partially solve the above-mentioned technical problems.

[0004] In order to achieve the above object, according to a first aspect of the present application, an array substrate is provided, comprising:

[0005] A substrate having a display area and a non-display area, wherein the non-display area is arranged around the display area and includes a binding area, wherein the binding area is located at one side of the display area in a first direction, the binding area includes two outer binding areas and a middle binding area, wherein the middle binding area is located between the two outer binding areas in a second direction, and the first direction intersects with the second direction;

[0006] A scan line, located on the substrate in the display area;

[0007] A gate driving circuit is located on the substrate and connected to the scanning line;

[0008] a gate test pad, located on the substrate in the non-display area and adjacent to at least one of the outer binding areas, and connected to the gate drive circuit;

[0009] The middle redundant gate test pad is located on the substrate in the non-display area and is adjacent to the middle binding area and is insulated from the gate driving circuit.

[0010] According to the second aspect of the present application, an embodiment of the present application provides a display panel, and the display panel includes the above-mentioned array substrate.

[0011] According to a third aspect of the present application, an embodiment of the present application provides a display panel motherboard, including:

[0012] A motherboard having a plurality of panel areas, each panel area including a display area and a non-display area, the non-display area being arranged around the display area and including a binding area, the binding area being located at one side of the display area in a first direction, the binding area including two outer binding areas and a middle binding area, the middle binding area being located between the two outer binding areas in a second direction, the second direction intersecting with the first direction;

[0013] A scan line is located on the motherboard of the display area;

[0014] A gate driving circuit is located on the motherboard and connected to the scanning line;

[0015] A gate test pad, located on the motherboard in the non-display area and adjacent to at least one of the outer binding areas, and connected to the gate drive circuit;

[0016] The middle redundant gate test pad is located on the motherboard in the non-display area and is adjacent to the middle binding area and is insulated from the gate driving circuit.

[0017] In the array substrate, display panel and display panel motherboard in some embodiments of the present application, when a gate test pad is provided around the outer binding area, an intermediate redundant gate test pad is additionally provided around the middle binding area. In this way, the pattern around the middle binding area tends to be the same as the pattern around the outer binding area. The pattern around the outer binding area and the pattern around the middle binding area can be prepared by splicing a mask plate, thereby reducing the number of exposure times of the mask plate in the process of manufacturing the array substrate and the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a planar structure of an array substrate provided in an exemplary embodiment of the present application;

[0019] Figure 2 It is provided in the exemplary embodiment of the present application Figure 1 A partial enlarged schematic diagram of an outer binding area of ​​the array substrate and its surroundings;

[0020] Figure 3 It is provided in the exemplary embodiment of the present application Figure 1 A partial enlarged schematic diagram of the middle binding area of ​​the array substrate and its surroundings;

[0021] Figure 4 It is provided along the exemplary embodiment of the present application Figure 3 The schematic diagram of the cross-sectional structure taken along the A-A' tangent line is shown;

[0022] Figure 5 It is provided in the exemplary embodiment of the present application Figure 1Another outer binding area of ​​the array substrate and a partial enlarged schematic diagram of its surroundings are shown;

[0023] Figure 6 The manufacturing method provided in the exemplary embodiment of the present application Figure 1 A schematic diagram of the process of the array substrate shown;

[0024] Figure 7 is a schematic diagram of a planar structure of a display panel provided in an exemplary embodiment of the present application;

[0025] Figure 8 is a schematic diagram of a planar structure of a display panel motherboard provided in an exemplary embodiment of the present application;

[0026] Fig. 9 It is provided in the exemplary embodiment of the present application Figure 8 A partial enlarged schematic diagram of the outer binding area of ​​the display panel motherboard and its surroundings is shown;

[0027] Fig.10 It is provided in the exemplary embodiment of the present application Figure 8 A partial enlarged schematic diagram of the middle binding area and its surroundings of the display panel motherboard is shown;

[0028] Fig.11 It is provided in the exemplary embodiment of the present application Figure 8 Another partial enlarged schematic diagram of the middle binding area and its surroundings of the display panel motherboard is shown.

[0029] Description of reference numerals:

[0030] 100, array substrate; 200, display panel; 300, display panel motherboard;

[0031] 11, substrate; 111, motherboard; 111A, panel area; 11A, display area; 11B, non-display area; 11C, binding area; 11C1, outer binding area; 11C2, middle binding area;

[0032] 20. Scan line;

[0033] 211, gate test pad; 212, first gate test pad; 213, second gate test pad; 214, middle redundant gate test pad; 215, first outer redundant gate test pad; 216, second outer redundant gate test pad;

[0034] 220, gate test line; 221, first gate test section; 222, second gate test section;

[0035] 223, middle redundant gate test line; 224, first redundant gate test section; 225, second redundant gate test section; 226, first outer redundant gate test line; 227, second outer redundant gate test line;

[0036] 241, a first gate array test pad; 242, a second gate array test pad; 243, a third gate array test pad;

[0037] 251, first connection line; 252, second connection line; 253, third connection line; 254, fourth connection line; 255, fifth connection line;

[0038] 26. Peripheral routing;

[0039] 30. Data cable;

[0040] 31. data short circuit routing; 311. first data short circuit section; 312. second data short circuit section;

[0041] 32. Data test pad;

[0042] 331, a first data array test pad; 332, a second data array test pad;

[0043] 34. Data array test connection line;

[0044] M1, first conductive layer; M2, second conductive layer;

[0045] 41. gate driving circuit; 51. pixel driving circuit; 52. pixel electrode;

[0046] 61. first outer binding pad; 62. second outer binding pad; 63. first middle binding pad; 64. second middle binding pad; 65. third outer binding pad;

[0047] 71. Drive unit;

[0048] S1, first mask; S2, second mask; Q1, first cutting line; Q2, second cutting line; Q3, third cutting line;

[0049] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0051] Figure 1 Schematic diagram of the planar structure of an array substrate provided in an exemplary embodiment of the present application. Figure 2 It is provided in the exemplary embodiment of the present application Figure 1 A partial enlarged schematic diagram of an outer binding area of ​​an array substrate and its surroundings is shown. Figure 3 It is provided in the exemplary embodiment of the present application Figure 1 A partial enlarged schematic diagram of the middle binding area of ​​the array substrate and its surroundings is shown. Figure 4 The exemplary embodiment of the present application provides Figure 3 The schematic diagram of the cross-sectional structure taken along the AA' line is shown. Figure 5 It is provided in the exemplary embodiment of the present application Figure 1 A partial enlarged schematic diagram of another outer binding area of ​​the array substrate and its surroundings is shown.

[0052] like Figures 1 to 5 As shown, the array substrate 100 includes a substrate 11 , a gate driving circuit 41 , a gate test pad 211 and an intermediate redundant gate test pad 214 .

[0053] like Figure 1 As shown, the substrate 11 has a display area 11A and a non-display area 11B. The non-display area 11B is arranged around the display area 11A. The substrate 11 may include a flexible substrate or a hard substrate. The flexible substrate includes an organic material. The hard substrate includes a hard material such as glass.

[0054] like Figures 1 to 3 as well as Figure 5 As shown, the display area 11A is provided with a plurality of signal lines. The plurality of signal lines include a plurality of data lines 30 extending along a first direction X and arranged along a second direction Y and a plurality of scan lines 20 extending along the second direction Y and arranged along the first direction X. The first direction X intersects with the second direction Y.

[0055] The first direction X is perpendicular to the second direction Y, but the present invention is not limited thereto. It is understood that the angle between the first direction X and the second direction Y may be an acute angle or an obtuse angle.

[0056] like Figure 1 As shown, in some embodiments, the display area 11A is further provided with a pixel driving circuit 51. The pixel driving circuit 51 is connected to the data line 30 and the scan line 20. In some embodiments, the display area 11A is further provided with a pixel electrode 52 of a liquid crystal display element. The pixel driving circuit 51 is connected to the pixel electrode 52 of the liquid crystal display element, and the pixel driving circuit 51 includes a thin film transistor. In other embodiments, the pixel driving circuit 51 can be connected to an organic light emitting diode.

[0057] like Figure 1As shown, the non-display area 11B includes a binding area 11C, and the binding area 11C is provided with a binding pad for binding the drive unit. In the first direction X, the binding area 11C is located on one side of the display area 11A. The binding area 11C includes two outer binding areas 11C1 and a middle binding area 11C2. In the second direction Y, the middle binding area 11C2 is located between the two outer binding areas 11C1. In other words, the two outer binding areas 11C1 are located at the edge of the binding area 11C in the second direction Y. Exemplarily, a plurality of middle binding areas 11C2 are located between the two outer binding areas 11C1.

[0058] The gate driving circuit 41 is located on the substrate 11. The gate driving circuit 41 is connected to the plurality of scanning lines 20 to output valid scanning signals and invalid scanning signals to the plurality of scanning lines 20. When each scanning line 20 receives a valid scanning signal of a high level, the pixel driving circuit 51 connected to the scanning line 20 can receive a data signal transmitted by the data line 30. When each scanning line 20 receives an invalid scanning signal of a low level, the pixel driving circuit 51 connected to the scanning line 20 may not receive a data signal transmitted by the data line 30.

[0059] In some embodiments, the gate driving circuit 41 may be integrated on the substrate 11, that is, formed on the substrate 11 through the manufacturing process of the display panel 200. In other embodiments, the gate driving circuit 41 may also be a gate driving chip, and the gate driving chip is bound to the substrate 11. In still other embodiments, the gate driving circuit 41 may also be disposed on a flexible base film, and the flexible base film is bound to the substrate 11.

[0060] In some embodiments, the gate driving circuit 41 is located in the non-display area 11B and is located on at least one side of the display area 11A in the second direction Y. In an exemplary embodiment, Figure 1 , Figure 2 as well as Figure 5 As shown, two gate driving circuits 41 are respectively located at opposite sides of the display area 11A in the second direction Y, that is, driving the scan lines 20 on both sides. In another exemplary embodiment, one gate driving circuit 41 may also be located at one side of the display area 11A, that is, driving the scan lines 20 on one side.

[0061] In some other embodiments, when the gate driving circuit 41 is formed on the substrate 11 through a manufacturing process of a display panel, at least a portion of the gate driving circuit 41 may be located in the display area 11A to reduce the frame of the array substrate 100 .

[0062] like Figure 2 and Figure 5As shown, the gate test pad 211 is located on the substrate 11 of the non-display area 11B. The gate test pad 211 is adjacent to at least one outer binding area 11C1 and is connected to the gate drive circuit 41. A gate test signal is loaded on the gate test pad 211, and the gate test signal is transmitted to the gate drive circuit 41, so that the gate drive circuit 41 outputs a valid scan signal and an invalid scan signal to a plurality of scan lines 20. In this way, the display screen can be detected during the test phase of the display panel 200.

[0063] In an exemplary embodiment, Figure 1 , Figure 2 as well as Figure 5 As shown, in the case where two gate driving circuits 41 are respectively located on opposite sides of the display area 11A in the second direction Y, the plurality of gate test pads 211 include a first gate test pad 212 and a second gate test pad 213. The first gate test pad 212 is located on a side of an outer binding area 11C1 away from the middle binding area 11C2 in the second direction Y, and is connected to a gate driving circuit 41. The second gate test pad 213 is located on a side of another outer binding area 11C1 away from the middle binding area 11C2 in the second direction Y, and is connected to another gate driving circuit 41. In this way, in the test phase of the display panel, gate test signals are applied to the first gate test pad 212 and the second gate test pad 213 respectively, so as to realize the detection of the display screen.

[0064] In some embodiments, the number of the first gate test pads 212 and the number of the second gate test pads 213 are both multiple. The number of the first gate test pads 212 is the same as the number of the second gate test pads 213. The multiple first gate test pads 212 are arranged at intervals along the second direction Y, and are located on the side of an outer binding area 11C1 away from the middle binding area 11C2, and are connected to a gate drive circuit 41. The multiple second gate test pads 213 are arranged at intervals along the second direction Y, and are located on the side of another outer binding area 11C1 away from the middle binding area 11C2, and are connected to another gate drive circuit 41. The multiple first gate test pads 212 and the multiple second gate test pads 213 can be loaded with a variety of different input signals of the gate drive circuit 41, such as clock signals and DC signals.

[0065] like Figure 3As shown, the intermediate redundant gate test pad 214 is located in the non-display area 11B. The intermediate redundant gate test pad 214 is adjacent to the intermediate binding area 11C2 and is insulated from the gate drive circuit 41. In this way, in the case where the gate test pad 211 is arranged around the outer binding area 11C1, the intermediate redundant gate test pad 214 is additionally arranged around the intermediate binding area 11C2. The pattern around the intermediate binding area 11C2 is similar to the pattern around the outer binding area 11C1. The pattern around the outer binding area 11C1 and the pattern around the intermediate binding area 11C2 can be prepared by splicing mask plates, that is, the pattern around the outer binding area 11C1 is prepared by splicing mask plates, which saves the space of the mask plates, reduces the number of exposure times of the mask plates in the process of manufacturing the array substrate 100, and supports the splicing of mask plates with different repeated exposure areas.

[0066] In some embodiments, at least one intermediate redundant gate test pad 214 is identical to the gate test pad 211, so that the intermediate redundant gate test pad 214 and the gate test pad 211 are formed in the same exposure process, and the pattern around the outer binding area 11C1 and the pattern around the intermediate binding area 11C2 can be formed by a splicing process of multiple mask templates.

[0067] In some embodiments, the shape of the middle redundant gate test pad 214 is the same as the shape of at least one gate test pad 211. Thus, the gate test pad 211 and the middle redundant gate test pad 214 are similar.

[0068] In some embodiments, when the shape of the middle redundant gate test pad 214 is the same as the shape of at least one gate test pad 211, the area of ​​the middle redundant gate test pad 214 is equal to the area of ​​at least one gate test pad 211. In this way, it is advantageous for the middle redundant gate test pad 214 to be the same as the gate test pad 211.

[0069] In some embodiments, the shapes of the gate test pad 211 and the middle redundant gate test pad 214 are at least one of a rectangle and a trapezoid, but are not limited thereto. Exemplarily, the shapes of the gate test pad 211 and the middle redundant gate test pad 214 are both rectangles.

[0070] The relative position between the gate test pad 211 and the outer binding area 11C1 is the same as the relative position between the middle redundant gate test pad 214 and the middle binding area 11C2. For example, the distance between the gate test pad 211 and the outer binding area 11C1 is equal to the distance between the middle redundant gate test pad 214 and the middle binding area 11C2.

[0071] In some embodiments, Figure 1 , Figure 2 as well as Figure 5As shown, when the two gate driving circuits 41 are respectively located on opposite sides of the display area 11A, and the multiple gate test pads 211 include a first gate test pad 212 and a second gate test pad 213, the array substrate 100 also includes a first outer redundant gate test pad 215 and a second outer redundant gate test pad 216.

[0072] like Figure 2 As shown, the first outer redundant gate test pad 215 is adjacent to an outer binding region 11C1, and the outer binding region 11C1 is located between the first outer redundant gate test pad 215 and the first gate test pad 212 in the second direction Y. Figure 5 As shown, the second outer redundant gate test pad 216 is adjacent to another outer binding region 11C1, and the other outer binding region 11C1 is located between the second outer redundant gate test pad 216 and the second gate test pad 213 in the second direction Y. Figure 3 As shown, middle redundant gate test pads 214 are disposed on both sides of each middle binding region 11C2 .

[0073] In the case where the two gate driving circuits 41 are respectively located at opposite sides of the display area 11A, and the plurality of gate test pads 211 include a first gate test pad 212 and a second gate test pad 213, a first outer redundant gate test pad 215 is added to a side of an outer binding area 11C1 away from the first gate test pad 212, and a second outer redundant gate test pad 216 is added to a side of another outer binding area 11C1 away from the second gate test pad 213. In addition, an intermediate redundant gate test pad 214 is added to both sides of each intermediate binding area 11C2. The patterns around the two outer binding areas 11C1 and the patterns around each intermediate binding area 11C2 are the same or tend to be the same, and the patterns around the two outer binding areas 11C1 and the patterns around the intermediate binding areas 11C2 can be formed by a splicing process of multiple mask plates.

[0074] In some embodiments, the first gate test pad 212 , the second gate test pad 213 , the middle redundant gate test pad 214 , the first outer redundant gate test pad 215 , and the second outer redundant gate test pad 216 are the same.

[0075] Figure 6 The manufacturing method provided in the exemplary embodiment of the present application Figure 1 Schematic diagram of the process of the array substrate shown.

[0076] When the gate test pad 211 is arranged around the outer binding area 11C1, but the gate test pad 211 is not arranged around the middle binding area 11C2, the pattern around the outer binding area 11C1 is different from the pattern around the middle binding area 11C2. The pattern around the outer binding area 11C1 needs to be produced by a separate mask plate and exposure process, and it cannot be produced by the same mask plate as the pattern around the middle binding area 11C2, resulting in that the pattern around the outer binding area 11C1 is difficult to be produced by splicing mask plates.

[0077] like Figure 2 , Figure 3 as well as Figure 5 As shown, an intermediate redundant gate test pad 214 is added around the middle binding region 11C2, which is conducive to the pattern around the middle binding region 11C2 being similar to the pattern around the outer binding region 11C1, and both can be formed in an exposure process of one mask. The pattern around the outer binding region 11C1 and the pattern around the middle binding region 11C2 can be formed by a splicing process of multiple mask plates, reducing the number of exposure times of the mask plate.

[0078] Specifically, Figure 6 As shown, when the first mask S1 and the second mask S2 are spliced, the overlapping area between the first mask S1 and the second mask S2 is the repeated exposure area H. In order to ensure that the pattern in the repeated exposure area H is similar to the pattern around the outer binding area 11C1, the pattern around the middle binding area 11C2 of the repeated exposure area H is controlled to be the same as or similar to the pattern around the outer binding area 11C1.

[0079] In some embodiments, N1 gate test pads 211 are located on at least one side of each of at least one outer binding region 11C1 in the second direction Y, and are adjacent to each of at least one outer binding region 11C1, and N1 is an integer greater than or equal to 1. N2 middle redundant gate test pads 214 are located on at least one side of a middle binding region 11C2 in the second direction Y, and are adjacent to a middle binding region 11C2, and N2 is an integer greater than or equal to 1, and N2 is less than or equal to N1. In this way, the pattern and the number around the middle binding region 11C2 are conducive to being the same as the pattern and the number around the outer binding region 11C1.

[0080] In an exemplary embodiment, the number of first gate test pads 212 and the number of second gate test pads 213 are the same as the number of middle redundant gate test pads 214, the number of first outer redundant gate test pads 215, and the number of second outer redundant gate test pads 216 on each side of the middle binding region 11C2 in the second direction.

[0081] In another exemplary embodiment, the number of the first gate test pads 212 is the same as the number of the second gate test pads 213. The number of the middle redundant gate test pads 214 on each side of the middle bonding region 11C2 in the second direction, the number of the first outer redundant gate test pads 215, and the number of the second outer redundant gate test pads 216 are the same. The number of the first gate test pads 212 is greater than the number of the middle redundant gate test pads 214 on each side of the middle bonding region 11C2 in the second direction.

[0082] It should be noted that when additional intermediate redundant gate test pads 214 are provided around the intermediate binding region 11C2 , the number of intermediate redundant gate test pads 214 on each side of the intermediate binding region 11C2 in the second direction Y depends on the number of intermediate redundant gate test pads 214 in the repeated exposure region.

[0083] In some embodiments, Figure 4 As shown, the gate test pad 211 and the middle redundant gate test pad 214 are located in the first conductive layer M1. Thus, when the first conductive layer M1 is formed by an exposure process using multiple spliced ​​mask plates, the gate test pad 211 and the middle redundant gate test pad 214 are formed.

[0084] In some embodiments, the first outer redundant gate test pad 215 and the second outer redundant gate test pad 216 are also located in the first conductive layer M1 .

[0085] In some embodiments, the first conductive layer M1 may further include a plurality of data lines 30 . Therefore, the gate test pad 211 and the middle redundant gate test pad 214 are located in the same layer as the plurality of data lines 30 .

[0086] In some embodiments, the first conductive layer M1 includes at least one of molybdenum, aluminum, titanium, copper, and silver.

[0087] In some embodiments, Figure 2 , Figure 3 as well as Figure 5As shown, the array substrate 100 further includes a first outer binding pad 61, a first middle binding pad 63, a gate test line 220, and a middle redundant gate test line 223. The first outer binding pad 61 is located on the substrate 11 of at least one outer binding area 11C1 and is connected to the gate driving circuit 41. The first middle binding pad 63 is located in the middle binding area 11C2. The gate test line 220 is adjacent to at least one outer binding area 11C1 and is connected to the first outer binding pad 61 and the gate test pad 211. The middle redundant gate test line 223 is adjacent to the middle binding area 11C2 and is insulated from at least one of the first middle binding pad 63 and the middle redundant gate test pad 214. In this way, when the gate test pad 211 is connected to the first outer binding pad 61 through the gate test line 220 around the outer binding area 11C1, the middle redundant gate test line 223 is further provided around the middle binding area 11C2, further making the pattern around the middle binding area 11C2 and the pattern around the outer binding area 11C1 tend to be the same.

[0088] In some embodiments, Figure 2 and Figure 5 As shown, the array substrate 100 further includes a peripheral trace 26 located in the non-display area 11B, and the peripheral trace 26 is connected between the first outer binding pad 61 and the gate driving circuit 41. In this way, the gate test pad 211 is connected to the gate driving circuit 41 through the gate test line 220, the first outer binding pad 61 and the peripheral trace 26.

[0089] In some embodiments, Figure 3 As shown, the middle redundant gate test line 223 is connected to the first middle binding pad 63 and is insulated from the middle redundant gate test pad 214. In this way, the risk of the redundant gate test pad 211 interfering with the display process of the display panel including the array substrate is reduced.

[0090] In some other embodiments, the middle redundant gate test line 223 is insulated from the first middle binding pad 63 and connected to the middle redundant gate test pad 214. In some further embodiments, the middle redundant gate test line 223 is insulated from both the first middle binding pad 63 and the middle redundant gate test pad 214.

[0091] It should be noted that the insulation between the intermediate redundant gate test line 223 and any one of the first intermediate binding pad 63 and the intermediate redundant gate test pad 214 means that the intermediate redundant gate test line 223 is not connected to any one of the first intermediate binding pad 63 and the intermediate redundant gate test pad 214. The intermediate redundant gate test line 223 can be disconnected by laser so that the intermediate redundant gate test line 223 is not connected to any one of the first intermediate binding pad 63 and the intermediate redundant gate test pad 214.

[0092] In some embodiments, the first middle binding pad 63 may be connected to a common electrode block (not shown).

[0093] In some embodiments, at least part of the middle redundant gate test line 223 and at least part of the gate test line 220 are non-linear, so as to improve the layout flexibility of the middle redundant gate test line 223 and the gate test line 220 and reduce the risk of short circuit between the middle redundant gate test line 223 and the gate test line 220 and other structures.

[0094] In some embodiments, the middle redundant gate test line 223 is the same as at least a portion of the gate test line 220. Thus, the pattern around the middle binding region 11C2 is the same as or tends to be the same as the pattern around the outer binding region 11C1.

[0095] In some embodiments, Figure 2 and Figure 3 As shown, the gate test line 220 includes a first gate test segment 221. The middle redundant gate test line 223 includes a first redundant gate test segment 224. The first gate test segment 221 is adjacent to the outer binding area 11C1 and is connected to the first outer binding pad 61. The first redundant gate test segment 224 is adjacent to the middle binding area 11C2 and is connected to the first middle binding pad 63. The first gate test segment 221 is the same as the first redundant gate test segment 224. In this way, the portion of the middle redundant gate test line 223 connected to the first middle binding pad 63 is the same as the portion of the gate test line 220 connected to the first outer binding pad 61.

[0096] In some embodiments, the first gate test segment 221 and the first redundant gate test segment 224 are in a zigzag shape. In other embodiments, the first gate test segment 221 and the first redundant gate test segment 224 may also be in a straight line shape.

[0097] In some embodiments, Figure 2 As shown, the gate test line 220 further includes a second gate test segment 222 . The second gate test segment 222 is connected between the first gate test segment 221 and the gate test pad 211 .

[0098] In some embodiments, Figure 2 As shown, at least part of the first gate test segment 221 and at least part of the second gate test segment 222 extend along the second direction Y and are staggered in the first direction X, so that the first gate test segment 221 is connected to the first outer binding pad 61 and the second gate test segment 222 is connected to the gate test pad 211.

[0099] In some embodiments, Figure 3As shown, the middle redundant gate test line 223 includes a second redundant gate test segment 225. The second redundant gate test segment 225 is connected to the middle redundant gate test pad 214 and is disconnected from the first redundant gate test segment 224.

[0100] In some embodiments, Figure 4 As shown, when the gate test pad 211 is located in the first conductive layer M1, the intermediate redundant gate test line 223 and the gate test line 220 are located in the second conductive layer M2. The second conductive layer M2 is located between the first conductive layer M1 and the substrate 11. In this way, the gate test line 220 and the gate test pad 211 are respectively located in different conductive layers, which improves the layout flexibility of the intermediate gate test line 220 and the gate test pad 211. In addition, when the second conductive layer M2 is formed by an exposure process using multiple spliced ​​mask templates, the intermediate redundant gate test line 223 and the gate test line 220 are formed.

[0101] In some embodiments, the second conductive layer M2 further includes a plurality of scan lines 20. The plurality of scan lines 20 are located in the same layer as the intermediate redundant gate test lines 223 and the gate test lines 220. In some embodiments, the second conductive layer M2 includes at least one of molybdenum, aluminum, titanium, copper, and silver.

[0102] In some embodiments, Figure 2 and Figure 5 As shown, when the array substrate 100 includes the first outer redundant gate test pad 215 and the second outer redundant gate test pad 216 , the array substrate 100 may further include a first outer redundant gate test line 226 , a second outer redundant gate test line 227 and a third outer binding pad 65 .

[0103] The first outer redundant gate test line 226 is adjacent to one outer binding region 11C1. In the second direction Y, at least part of the first outer redundant gate test line 226 and at least part of the gate test line 220 are located on the opposite side of one outer binding region 11C1. The first outer redundant gate test line 226 is insulated from at least one of the third outer binding pad 65 and the first outer redundant gate test pad 215 located in one outer binding region 11C1. In an exemplary embodiment, the first outer redundant gate test line 226 is connected to the third outer binding pad 65 located in one outer binding region 11C1, and is not connected to the first outer redundant gate test pad 215.

[0104] The second outer redundant gate test line 227 is adjacent to the other outer binding region 11C1. In the second direction Y, at least part of the second outer redundant gate test line 227 and at least part of the gate test line are located on the opposite side of the other outer binding region 11C1. The second outer redundant gate test line 227 is insulated from at least one of the third outer binding pad 65 and the second outer redundant gate test pad 216 located in the other outer binding region 11C1. In an exemplary embodiment, the second outer redundant gate test line 227 is connected to the third outer binding pad 65 located in the other outer binding region 11C1, and is not connected to the second outer redundant gate test pad 216.

[0105] In some embodiments, the first outer redundant gate test line 226 and the second outer redundant gate test line 227 are the same as the middle redundant gate test line.

[0106] In some embodiments, reference Figure 2 , Figure 3 as well as Figure 5 As shown, the array substrate 100 further includes a second outer binding pad 62, a second middle binding pad 64 and a data short-circuit line 31. The second outer binding pad 62 is located in the outer binding area 11C1 and is connected to the data line 30. The second middle binding pad 64 is located in the middle binding area 11C2 and is connected to the data line 30. The data short-circuit line 31 is connected to the second outer binding pad 62 and the second middle binding pad 64. The orthographic projection of the data short-circuit line 31 on the substrate 11 is staggered from the orthographic projection of the gate test pad 211 and the middle redundant gate test pad 214 on the substrate 11. In this way, the risk of short circuit between the data short-circuit line 31 and the gate test pad 211 and the middle redundant gate test pad 214 is reduced.

[0107] In some embodiments, when the array substrate 100 further includes a first outer redundant gate test pad 215 and a second outer redundant gate test pad 216 , the orthographic projection of the data short circuit trace 31 on the substrate 11 is staggered from the orthographic projection of the first outer redundant gate test pad 215 and the second outer redundant gate test pad 216 on the substrate 11 .

[0108] In some embodiments, Figure 2 , Figure 3 as well as Figure 5 As shown, at least part of the data short-circuit wiring 31 is non-linear, so as to improve the layout flexibility of the data short-circuit wiring 31 and facilitate the data short-circuit wiring 31 to avoid the gate test pad 211 and the middle redundant gate test pad 214.

[0109] In some embodiments, Figure 2 , Figure 3 as well as Figure 5As shown, the data short circuit line 31 includes a plurality of first data short circuit segments 311. The plurality of first data short circuit segments 311 are respectively adjacent to and staggered with the gate test pad 211 and the middle redundant gate test pad 214. Thus, at least part of the data short circuit line 31 is staggered with the gate test pad 211 and the middle redundant gate test pad 214.

[0110] In some embodiments, the plurality of first data short circuit segments 311 extend along the second direction Y, and are adjacent to and staggered with the gate test pad 211 and the middle redundant gate test pad 214 in the first direction X, respectively.

[0111] In some embodiments, the data short-circuit line 31 further includes a plurality of second data short-circuit sections 312. The plurality of second data short-circuit sections 312 are respectively adjacent to the outer binding area 11C1 and the middle binding area 11C2, and are connected to the second outer binding pad 62, the second middle binding pad 64, and the plurality of first data short-circuit sections 311. The plurality of second data short-circuit sections 312 are staggered with the plurality of first data short-circuit sections 311. In this way, the data short-circuit line 31 adopts a non-linear segmented structure to avoid the gate test pad 211 and the middle redundant gate test pad 214, and is also connected to the plurality of data lines 30 through the second outer binding pad 62 and the second middle binding pad 64.

[0112] In some embodiments, the plurality of second data short circuit segments 312 may be in a zigzag shape. Each second data short circuit segment 312 includes a data short circuit straight segment and a data short circuit inclined segment connected to each other. The data short circuit straight segment extends along the second direction Y, is connected to the second outer binding pad 62 and the second middle binding pad 64, and is staggered with the first data short circuit segment 311 in the first direction X. The data short circuit inclined segment is connected between the first data short circuit segment 311 and the data short circuit straight segment. The extension direction of the data short circuit straight segment intersects the first direction X and the second direction Y.

[0113] In some embodiments, the data short-circuit trace 31 and the redundant gate test pad 211 and the gate test pad 211 are located in the first conductive layer M1. In this way, the data short-circuit trace 31 and the redundant gate test pad 211 and the gate test pad 211 can be formed at the same time, simplifying the manufacturing process of the array substrate 100. In addition, when the orthographic projection of the data short-circuit trace 31 on the substrate 11 is staggered with the orthographic projection of the gate test pad 211 and the middle redundant gate test pad 214 on the substrate 11, the problem of interference between the data short-circuit trace 31 and the gate test pad 211 and the middle redundant gate test pad 214 caused by mask splicing is improved.

[0114] In some embodiments, Figure 2 , Figure 3 as well as Figure 5As shown, the array substrate 100 further includes a data test pad 32. The data test pad 32 is connected to the data short-circuit wiring 31. In this way, a data test signal is applied to the data test pad 32, and the data test signal can be transmitted to the plurality of data lines 30 through the data short-circuit wiring 31, so as to realize the detection of the picture in the test stage of the display panel.

[0115] In some embodiments, the plurality of data test pads 32 are respectively adjacent to the two outer binding regions 11C1 and the plurality of middle binding regions 11C2 .

[0116] In some embodiments, Figure 2 and Figure 5 As shown, when the array substrate 100 further includes a gate test line 220, when the gate test line 220 and the data short-circuit line 31 are located in different conductive layers, at least part of the orthographic projection of the gate test line 220 on the substrate 11 is staggered with the orthographic projection of the data short-circuit line 31 on the substrate 11, for example, the second data short-circuit section 312 is staggered with the first gate test section 221. In this way, the overlapping area between the gate test line 220 and the data short-circuit line 31 located in different layers is reduced, and the risk of damage to insulating film layers such as the planarization layer on the array substrate 100 due to the large overlapping area between the two is improved.

[0117] In some embodiments, Figure 3 As shown, when the array substrate 100 further includes an intermediate redundant gate test line 223, the intermediate redundant gate test line 223 and the data short-circuit line 31 are respectively located in different conductive layers. At least part of the orthographic projection of the intermediate redundant gate test line 223 on the substrate 11 is staggered with the orthographic projection of the data short-circuit line 31 on the substrate 11, for example, the second data short-circuit section 312 is staggered with the first redundant gate test section 224. In this way, the overlapping area between the intermediate redundant gate test line 223 and the data short-circuit line 31 located in different layers is reduced, and the risk of damage to insulating film layers such as the planarization layer on the array substrate 100 due to the large overlapping area between the two is improved.

[0118] In some embodiments, Figure 2 , Figure 3 as well as Figure 5 As shown, the middle redundant gate test line 223 and the gate test line 220 overlap with the data short-circuit line 31. In this way, the space occupied by the middle redundant gate test line 223, the gate test line 220 and the data short-circuit line 31 in the non-display area 11B is reduced, ensuring that the display panel 200 including the array substrate 100 realizes a narrow frame.

[0119] In some embodiments, the overlapping area between the gate test line 220 and the data short circuit line 31 is larger than the overlapping area between the middle redundant gate test line 223 and the data short circuit line 31. In this way, it is possible to adapt to the situation where the middle redundant gate test line 223 is connected to the first middle binding pad 63 and is not connected to the middle redundant gate test pad 214.

[0120] Figure 7 Schematic diagram of a planar structure of a display panel provided in an exemplary embodiment of the present application.

[0121] Based on the same inventive concept, Figure 7 As shown, the present application further provides a display panel 200 , which is the array substrate 100 of any of the above embodiments.

[0122] In some embodiments, Figure 7 As shown, the display panel 200 further includes a plurality of driving units 71. The plurality of driving units 71 are respectively bound to the two outer binding areas 11C1 and the middle binding area 11C2.

[0123] In some embodiments, the driving unit 71 may be a driving chip. In other embodiments, the driving unit 71 may include a flexible film and a driving chip on the flexible film, that is, the driving unit 71 is a chip-on-film.

[0124] In some embodiments, the display panel 200 may further include an opposing substrate 11 and a liquid crystal layer. The opposing substrate 11 is disposed opposite to the array substrate 100 , and a liquid crystal layer is disposed between the opposing substrate 11 and the array substrate 100 .

[0125] Figure 8 It is a schematic diagram of the planar structure of a display panel motherboard provided in an exemplary embodiment of the present application. Fig. 9 It is provided in the exemplary embodiment of the present application Figure 8 A partial enlarged schematic diagram of the outer binding area of ​​the display panel motherboard and its surroundings is shown. Fig.10 It is provided in the exemplary embodiment of the present application Figure 8 The figure shows a partial enlarged schematic diagram of the middle binding area and its surroundings of the display panel motherboard. Fig.11 It is provided in the exemplary embodiment of the present application Figure 8 Another partial enlarged schematic diagram of the middle binding area and its surroundings of the display panel motherboard is shown.

[0126] Reference Figures 8 to 11 As shown, the embodiment of the present application also provides a display panel motherboard 300. Fig. 9 and Fig.10 Cut along the first cutting line Q1, or Fig.11The display panel 200 can be obtained by cutting along the second cutting line Q2 and the third cutting line Q3. The display panel 200 includes the array substrate 100.

[0127] The display panel motherboard 300 includes a motherboard 111 , a gate driving circuit 41 , a gate test pad 211 , and an intermediate redundant gate test pad 214 .

[0128] The motherboard 111 has a plurality of panel areas 111A. Each panel area 111A includes a display area 11A and a non-display area 11B. The non-display area 11B is arranged around the display area 11A and includes a binding area 11C. The binding area 11C is located on one side of the display area 11A in the first direction X. The binding area 11C includes two outer binding areas 11C1 and a middle binding area 11C2. The middle binding area 11C2 is located between the two outer binding areas 11C1 in the second direction Y, and the second direction Y intersects with the first direction X. The scan line 20 is located on the motherboard 111 of the display area 11A. The gate drive circuit 41 is located on the motherboard 111. The gate test pad 211 is located in the non-display area 11B, adjacent to at least one outer binding area 11C1 in the second direction Y, and connected to the gate drive circuit 41. The middle redundant gate test pad 214 is located in the non-display area 11B, adjacent to the middle binding area 11C2, and insulated from the gate drive circuit 41.

[0129] In the display panel motherboard 300 of some embodiments of the present application, when the gate test pad 211 is arranged around the outer binding area 11C1, an intermediate redundant gate test pad 214 is additionally arranged around the middle binding area 11C2. In this way, the pattern around the middle binding area 11C2 tends to be the same as the pattern around the outer binding area 11C1. The pattern around the outer binding area 11C1 and the pattern around the middle binding area 11C2 can be prepared by splicing the mask template, thereby reducing the number of exposure times of the mask template in the process of manufacturing the display panel 200 template.

[0130] After the display panel motherboard 300 is cut, the display panel 200 including the array substrate 100 is obtained. The relevant contents of the array substrate 100 are also applicable to the display panel 200 motherboard, which will not be repeated here.

[0131] In some embodiments, Fig. 9 and Fig.10As shown, the display panel motherboard 300 further includes a first gate array test pad 241 and a second gate array test pad 242. The first gate array test pad 241 is located in the non-display area 11B, adjacent to the outer binding area 11C1, and connected to the gate drive circuit 41. The second gate array test pad 242 is located in the non-display area 11B, adjacent to the middle binding area 11C2. In this way, when the first gate array test pad 241 is arranged around the outer binding area 11C1, the second gate array test pad 242 is also arranged around the middle binding area 11C2, so that the pattern around the middle binding area 11C2 tends to be the same as the pattern around the outer binding area 11C1.

[0132] In the process of testing the array substrate 100 , a gate array test signal is applied to the first gate array test pad 241 to test the gate driving circuit 41 .

[0133] In some embodiments, the second gate array test pad 242 is insulated from the gate drive circuit 41. When the second gate array test pad 242 is insulated from the gate drive circuit 41, the second gate array test pad 242 is not connected to the gate drive circuit 41. When the second gate array test pad 242 is insulated from the gate drive circuit 41, during the test of the array substrate 100, the gate array test signal is not applied to the second gate array test pad 242.

[0134] In some embodiments, the first gate array test pad 241 is the same as the second gate array test pad 242 , that is, the shape and area of ​​the first gate array test pad 241 are the same as the shape and area of ​​the second gate array test pad 242 .

[0135] In some embodiments, the first gate array test pad 241 , the second gate array test pad 242 and the middle redundant gate test pad 214 are located in the first electrical layer M1 .

[0136] In some embodiments, Fig. 9 and Fig.10 As shown, the display panel motherboard 300 also includes a first connection line 251 and a second connection line 252. The first connection line 251 and the second connection line 252 are located on the motherboard 111 of the non-display area 11B. The first connection line 251 is adjacent to the outer binding area 11C1, and connects the first gate array test pad 241 and the gate test pad 211. The second connection line 252 is adjacent to the middle binding area 11C2, and connects the second gate array test pad 242 and the middle redundant gate test pad 214. In this way, when the first connection line 251 is provided in the outer binding area 11C1, the second connection line 252 is additionally provided around the middle binding area 11C2, and the pattern around the middle binding area 11C2 tends to be the same as the pattern around the outer binding area 11C1.

[0137] In some embodiments, Fig. 9 As shown, when the display panel motherboard 300 includes the first outer redundant gate test pad 215, the display panel motherboard 300 also includes a third gate array test pad 243 and a third connection line 253. The third connection line 253 connects the third gate array test pad 243 and the first outer redundant gate test pad 215.

[0138] In some embodiments, the first connection trace 251 to the third connection trace 253, the first gate array test pad 241 to the third gate array test pad 243, the gate test pad 211, the middle redundant gate test pad 214 and the first outer redundant gate test pad 215 are located on the first electrical layer M1. In this way, the first connection trace 251 connects the first gate array test pad 241 and the gate test pad 211, the second connection trace 252 connects the second gate array test pad 242 and the middle redundant gate test pad 214, and the third connection trace 253 connects the third gate array test pad 243 and the first outer redundant gate test pad 215.

[0139] In some embodiments, reference Fig. 9 and Fig.10 As shown, the display panel motherboard 300 further includes a plurality of data lines 30, a data short-circuit line 31, a first data array test pad 331, and a second data array test pad 332. The plurality of data lines 30 are located on the motherboard 111 of the display area 11A. The data short-circuit line 31 is located on the motherboard 111 of the non-display area 11B and is connected to the plurality of data lines 30. The first data array test pad 331 is located in the non-display area 11B, adjacent to the outer binding area 11C1, and connected to the data short-circuit line 31. The second data array test pad 332 is located in the non-display area 11B, adjacent to the middle binding area 11C2. In this way, when the first data array test pad 331 is arranged around the outer binding area 11C1, the second data array test pad 332 is additionally arranged around the middle binding area 11C2, so that the pattern around the middle binding area 11C2 tends to be the same as the pattern around the outer binding area 11C1.

[0140] In the process of testing the array substrate 100 , a data test signal is applied to the first data array test pad 331 to implement testing of the plurality of data lines 30 .

[0141] In some embodiments, the second data array test pad 332 may be connected to the plurality of data lines 30 or may be insulated from the plurality of data lines 30 .

[0142] In some embodiments, Fig. 9 and Fig.10As shown, the display panel motherboard 300 further includes a data array test connection line 34 and a data test pad 32. The data array test connection line 34 is connected to the first data array test pad 331 through the fourth connection line 254. The data array test connection line 34 is connected to the second data array test pad 332 through the fifth connection line 255. The data array test connection line 34 is connected to the data test pad 32, and the data test pad 32 is connected to the plurality of data lines 30 through the data short circuit line 31.

[0143] In some embodiments, the first data array test pad 331 and the second data array test pad 332 , the fourth connection trace 254 , the fifth connection trace 255 , the gate test pad 211 and the middle redundant gate test pad 214 are all located in the first conductive layer M1 .

[0144] In some embodiments, the data array test connection line 34 is located in the second conductive layer M2. The data array test connection line 34 intersects with the first connection line 251 to the fifth connection line 255. In this way, the data array test connection line 34 and the first connection line 251 to the fifth connection line 255 are located in different conductive layers, reducing the risk of short circuit between the data array test connection line 34 and the first connection line 251 and the second connection line 252.

[0145] In some embodiments, Fig.11 As shown, the data array test connection line 34 can also be reused as the data short-circuit line 31, and the data array test connection line 34 is connected to the plurality of data lines 30 through the second outer binding pad 62 of the outer binding area 11C1 and the second middle binding pad 64 of the middle binding area 11C2. In this way, the wiring of the non-display area 11B is reduced.

[0146] It should be noted that after the array test is completed, cutting is performed along the second cutting line Q2, and the remaining data array test connection lines 34 are used as data short-circuit lines 31. After the display panel test is completed, cutting is performed along the third cutting line Q3 to obtain a display panel.

[0147] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0148] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0149] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0150] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: include: A substrate having a display area and a non-display area, wherein the non-display area is arranged around the display area and includes a binding area, wherein the binding area is located at one side of the display area in a first direction, the binding area includes two outer binding areas and a middle binding area, wherein the middle binding area is located between the two outer binding areas in a second direction, and the first direction intersects with the second direction; A scan line, located on the substrate in the display area; A gate driving circuit is located on the substrate and connected to the scanning line; a gate test pad, located on the substrate in the non-display area and adjacent to at least one of the outer binding areas, and connected to the gate drive circuit; The middle redundant gate test pad is located on the substrate in the non-display area and is adjacent to the middle binding area and is insulated from the gate driving circuit.

2. The array substrate according to claim 1, characterized in that: At least one of the intermediate redundant gate test pads is identical to the gate test pad.

3. The array substrate according to claim 1, characterized in that: N1 gate test pads are located at least one side of each of the at least one outer binding region in the second direction and are adjacent to each of the at least one outer binding region, and N1 is an integer greater than or equal to 1; N2 of the intermediate redundant gate test pads are located at least on one side of each of the at least one intermediate binding regions in the second direction and are adjacent to each of the at least one intermediate binding regions, N2 is an integer greater than or equal to 1, and N2 is less than or equal to N1.

4. The array substrate according to claim 1, characterized in that: The gate test pad and the middle redundant gate test pad are located in the first conductive layer.

5. The array substrate according to claim 1, characterized in that: Also includes: a first outer binding pad, located on the substrate of at least one of the outer binding regions and connected to the gate driving circuit; a first middle binding pad, located on the substrate in the middle binding region; a gate test line, adjacent to at least one of the outer binding regions and connected to the first outer binding pad and the gate test pad; A middle redundant gate test line is adjacent to the middle binding region, connected to the first middle binding pad and insulated from at least one of the middle redundant gate test pads.

6. The array substrate according to claim 5, characterized in that: The intermediate redundant gate test line is identical to at least a portion of the gate test line.

7. The array substrate according to claim 5, characterized in that: The gate test pad is located in a first conductive layer, the middle redundant gate test line and the gate test line are located in a second conductive layer, and the second conductive layer is located between the first conductive layer and the substrate.

8. The array substrate according to claim 1, characterized in that: Also includes: A plurality of data lines are located on the substrate in the display area; a second outer binding pad, located on the substrate in the outer binding area and connected to the data line; A second middle binding pad, located on the substrate in the middle binding area and connected to the data line; A data short circuit line is connected to the second outer binding pad and the second middle binding pad, and an orthographic projection of the data short circuit line on the substrate is staggered from an orthographic projection of the gate test pad and the middle redundant gate test pad on the substrate.

9. The array substrate according to claim 8, characterized in that: At least part of the data short-circuit wiring is non-linear.

10. The array substrate according to claim 8 or 9, characterized in that: The data short-circuit routing line includes a first data short-circuit segment, and a plurality of the first data short-circuit segments are respectively adjacent to and staggered with the gate test pad and the middle redundant gate test pad.

11. The array substrate according to claim 10, characterized in that: The data short-circuit routing also includes multiple second data short-circuit segments, which are respectively adjacent to the outer binding area and the middle binding area, and are connected to the second outer binding pad, the second middle binding pad and the multiple first data short-circuit segments, and the multiple second data short-circuit segments are staggered with the multiple first data short-circuit segments.

12. The array substrate according to claim 8, characterized in that: The data short-circuit wiring, the redundant gate test pad and the gate test pad are located in the first conductive layer.

13. The array substrate according to claim 8, characterized in that: Also includes: a first outer side binding pad located at at least one of the outer side binding regions; A gate test line is adjacent to at least one of the outer binding areas and is connected to the first outer binding pad and the gate test pad. The gate test line and the data short-circuit line are respectively located in different conductive layers, and at least part of the gate test line's orthographic projection on the substrate is staggered from the orthographic projection of the data short-circuit line on the substrate.

14. The array substrate according to claim 13, characterized in that: Also includes: a first middle binding pad, located in the middle binding area; An intermediate redundant gate test line is adjacent to the intermediate binding area and is insulated from at least one of the first intermediate binding pad and the intermediate redundant gate test pad. The intermediate redundant gate test line and the data short-circuit line are respectively located in different conductive layers, and at least part of the orthographic projection of the intermediate redundant gate test line on the substrate is staggered from the orthographic projection of the data short-circuit line on the substrate.

15. The array substrate according to claim 1, characterized in that: The two gate driving circuits are respectively located at opposite sides of the display area in the second direction; The multiple gate test pads include a first gate test pad and a second gate test pad, the first gate test pad is located on a side of one of the outer binding regions away from the middle binding region in the second direction and is connected to one of the gate drive circuits, and the second gate test pad is located on a side of another of the outer binding regions away from the middle binding region in the second direction and is connected to another of the gate drive circuits.

16. The array substrate according to claim 15, characterized in that: Also includes: A first outer redundant gate test pad is adjacent to one of the outer binding regions, and in the second direction, one of the outer binding regions is located between the first outer redundant gate test pad and the first gate test pad; A second outer redundant gate test pad is adjacent to another outer binding region, and in the second direction, another outer binding region is located between the second outer redundant gate test pad and the second gate test pad; Wherein, at least one intermediate redundant gate test pad is respectively arranged on the opposite side of each intermediate binding region in the second direction.

17. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 16.

18. A display panel motherboard, characterized in that: include: A motherboard having a plurality of panel areas, each panel area including a display area and a non-display area, the non-display area being arranged around the display area and including a binding area, the binding area being located at one side of the display area in a first direction, the binding area including two outer binding areas and a middle binding area, the middle binding area being located between the two outer binding areas in a second direction, the second direction intersecting with the first direction; A scan line is located on the motherboard of the display area; A gate driving circuit is located on the motherboard and connected to the scanning line; A gate test pad, located on the motherboard in the non-display area and adjacent to at least one of the outer binding areas, and connected to the gate drive circuit; The middle redundant gate test pad is located on the motherboard in the non-display area and is adjacent to the middle binding area and is insulated from the gate driving circuit.

19. The display panel motherboard according to claim 18, characterized in that: Also includes: A first gate array test pad, located in the non-display area and adjacent to the outer binding area, and connected to the gate drive circuit; The second gate array test pad is located in the non-display area and is adjacent to the middle binding area.

20. The display panel motherboard according to claim 18, characterized in that: Also includes: A plurality of data lines are located on the motherboard of the display area; A data short-circuit wiring is located in the motherboard of the non-display area and is connected to a plurality of the data lines; A first data array test pad, located in the non-display area and adjacent to the outer binding area, and connected to the data short-circuit trace; The second data array test pad is located in the non-display area and is adjacent to the middle binding area.

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