Method for operating memory module, memory control device and MEMS component

Abstract

The invention relates to a method for operating a memory module, comprising the following steps: providing a memory module in a first step, the memory module comprising a memory region having a plurality of memory cells, the memory cells having data, providing at least one address boundary register having at least one address boundary in a second step, wherein, in a second step, the provision of the at least one address boundary register comprises: the provision of the address boundary to a new value and the provision of the at least one address boundary register being able to check whether the new value has changed in a direction allowed in terms of the value, and in a third step, the provision of the at least one address boundary register being able to change in the direction allowed in terms of the value. According to the invention, during access to data of a memory unit of a memory module, in particular a write access and / or a read access, it is checked whether the access is permitted and, if the access is permitted, the access is carried out. The invention further relates to a memory control device and to a MEMS component.

Description

Technical Field

[0001] The invention relates to a method for operating a memory module. The invention also relates to a memory controller and a MEMS component having a memory controller with a memory module. Background Art

[0002] The object of the present invention is to specify an improved method for operating a memory module as well as an improved memory control device and an improved MEMS component.

[0003] This object is achieved by the method according to the invention for operating a memory module, a memory control device and a MEMS component. Further advantageous embodiments of the invention are described below. Summary of the invention

[0004] A method for operating a storage module is proposed, comprising the following steps:

[0005] In a first step, a memory module is provided, wherein the memory module comprises a memory area having a plurality of memory cells, wherein the memory cells have data,

[0006] In a second step, at least one address boundary register is provided which has at least one address boundary, which can be changed in value at least in one direction,

[0007] wherein providing the at least one address boundary register in the second step comprises being able to set an address boundary to a new value and being able to check whether the new value has changed in a direction that is allowed in terms of value, and

[0008] In a third step, during access, in particular write access and / or read access, to data of a memory cell of the memory module, it is checked whether the access is permitted and, if the access is permitted, the access is carried out.

[0009] The term "data" may be understood as a synonym for data object.

[0010] In order to access the storage module, an access area of ​​possible access addresses is determined. Outside this access area, no read access and / or write access is possible. Therefore, if the access address is not located in the corresponding access area (this can vary depending on the implementation of the address boundary register), then for example, the access may not be allowed.

[0011] In particular, it is conceivable that if access to the data of the storage unit is not allowed in the third step, the access to the data of the storage unit is not performed and an error message is generated. Advantageously, this can increase security and protect important data from unauthorized access. The error message can be generated, for example, by the processing unit or its software module.

[0012] Microelectromechanical components (MEMS components, MEMS: Micro Electro Mechanical System) designed as MEMS sensors are used in various applications, such as smartphones, game controllers, smart watches, drones, headphones or other mobile terminal devices. This list should not be understood as exhaustive.

[0013] The MEMS sensor includes an analysis circuit, such as an ASIC element (ASIC: Application Specific Integrated Circuit), which may include a microprocessor-based system with a memory control device. The microprocessor-based system with a memory control device may include a processing unit, which is configured as a CPU and can be interconnected with a storage module / memory and peripheral devices via a bus system. The storage module can be configured in different types, for example, as a non-volatile memory (NVM) or a volatile memory, wherein the access control or method for operating the storage module can preferably be used for a storage module configured as an NVM memory. When the storage module is configured as an NVM memory, it is used to store:

[0014] Program code (firmware) that executes on microprocessor-based systems

[0015] Calibration data for ASIC or MEMS specific functions (e.g., VREG (voltage regulator) or POR adjustment (power-on reset adjustment), oscillator trimming, offset and gain adjustment for sensors)

[0016] Component-specific manufacturing information, such as unique ID, wafer ID and die coordinates, product variants, function bits, such as those used to block specific functions (e.g. shut down a memory block)

[0017] Security keys, such as for

[0018] - Certified firmware images

[0019] - Authentication e.g. for access rights to read / write adjustment data

[0020] -Decrypted firmware image

[0021] - Encrypted sensor data

[0022] - Authentication sensor data.

[0023] The terms "firmware" and "software" are to be understood herein as synonyms.

[0024] Access rights to storage modules must be managed because various data or contents may not always be accessible to the software.

[0025] · Fine-tuning data must not be changed after adjustment.

[0026] Wafer data cannot be read without authorization

[0027] The security key cannot be altered or read.

[0028] So far, such access control for storage modules has been implemented in hardware, for example, by means of lock bits. The entire storage module or a fixed section of a storage module can be controlled by means of the lock bits. A software bit (lock bit) can be written once after a startup process (reset) in order to lock / allow access, i.e. write access and / or read access. Before the next startup process (reset), the lock bit cannot be changed again or unlocked. A disadvantage of the known method and the known memory control device is the fact that only access to the entire storage module is enabled / prevented, or that a fixed sector size for each access area must be determined in hardware. The software or firmware has only limited decision possibilities regarding the time point and type of access enabled / prevented.

[0029] The proposed method advantageously allows for flexible access control of a memory module, which is preferably designed as a non-volatile memory, which access control does not require that the size and access restrictions of the individual memory cells of a memory area must be specified in the hardware design. Instead, the access regulations can be flexibly defined in the firmware so that the access can be handled flexibly and can also be changed by updating the firmware.

[0030] In this way, sensitive data can be protected in the best possible way, because an access area of ​​possible access addresses is determined for accessing the storage module. No read access and / or write access can be performed outside this access area. The access area of ​​the address boundary register is defined at least based on the following access address: the access address is higher in value than the value of the address boundary of the address boundary register in the first embodiment (in the case of an implementation with ascending address boundaries) or corresponds to the corresponding address boundary. In the second embodiment, the access area is defined at least based on the following access address: the access address is lower in value than the value of the address boundary of the address boundary register (in the case of an implementation with descending address boundaries) or corresponds to the corresponding address boundary. The combination of ascending and descending address boundaries in the case of using multiple address boundary registers is also conceivable. Here, access can only be performed when the access address is higher than one address boundary register and lower than another address boundary register.

[0031] The flexibility of the proposed method is also reflected in that the at least one address boundary register can be defined only for write access and / or can be defined only for read access and / or, in the case of a plurality of independent address boundary registers, one can be defined for write access and one can be defined for read access.

[0032] In another embodiment, the third step can be performed without previously performing the second step. For example, the following scenario can be envisaged: in this scenario, the address boundary is at the value "zero" after a system reset, which means that all accesses are performed. Here, the change of the address boundary and the actual access to the data of the memory cells of the memory module are independent events, which can occur in any number and order.

[0033] In another embodiment, the third step is repeated multiple times. For example, it is conceivable that the third step occurs multiple times without the second step. Here, the change of the address boundary and the actual access to the data of the storage unit of the storage module are independent events, which can occur in any number and order.

[0034] In another embodiment, the second step is repeated multiple times without performing the third step. Here, the change of the address boundary and the actual access to the data of the memory cells of the memory module are independent events, which can occur in any number and order.

[0035] In another embodiment, the second step and the third step are repeated multiple times. Here, the change of the address boundary and the actual access to the data of the storage unit of the storage module are independent events, which can occur in any number and order.

[0036] In addition, a memory control device is proposed, which includes the following components:

[0037] a processing unit which is operatively connected via a bus system to a memory module, which is in particular designed as a non-volatile memory,

[0038] The storage module includes a storage area having a plurality of storage units, wherein the storage units have data.

[0039] The memory control device includes an address logic module, which is operatively connected to the processing unit and the storage module via a bus system.

[0040] wherein the address logic module is configured to provide at least one address boundary register having at least one address boundary,

[0041] The processing unit comprises a software module which is designed to change at least one address boundary with respect to a value at least in one direction.

[0042] The address logic module is designed to set the address limit to a new value and to check whether the new value has changed in a direction permitted in terms of value,

[0043] Wherein, the address logic module includes at least one logic comparator element,

[0044] In this case, the logical comparator element is designed for an access, in particular a write access and / or a read access, to data of the memory cell to check whether the access is permitted and to carry out the access if the access is permitted.

[0045] The proposed memory control device including the memory module can be realized simply to realize the method for operating the memory module. For example, the possible access using the address logic or the address logic module used can be realized with only a few components (for example, one logic comparator element for write access or read access in each case). The logic comparator element can also be understood as a comparator.

[0046] Advantageously, no assumptions need to be made about the size of the possible access area when configuring the memory module and when designing the hardware. The access area can be constructed according to the above explanations and can be flexibly determined later in the software module, i.e. in the software, and can be variably adapted during the life cycle of the product by firmware updates. The term "software module" can be understood as a synonym for software or firmware.

[0047] In another embodiment, the at least one address boundary register is designed as a digital flip-flop structural element in hardware. The digital flip-flop structural element is designed to check whether the new value of the address boundary has changed in a direction that is allowed in terms of value. Therefore, a pure software implementation is advantageously not required. However, it should be understood that the setting of the flip-flop structural element can be implemented by means of program code (e.g. C++ or the like).

[0048] In another embodiment, access to sensor calibration data, security keys and / or firmware objects is controlled.Thus, the method is advantageously suitable for use in conjunction with MEMS sensors.

[0049] In another embodiment, a software module, in particular executed in the form of software on a microprocessor system, is designed to gradually set the address limit register to higher values ​​during the startup process and, as a result, to close access to data objects as soon as protection of access to data objects is required. Advantageously, this allows targeted protection of data or data objects from unauthorized access.

[0050] In another embodiment, the address boundary register can be implemented in ascending order in the address boundary. The software module of the processing unit is configured to set the at least one address boundary of the address boundary register in the direction of ascending order in terms of value. The software module of the processing unit is also configured to transmit the set value of the address boundary to the address logic module. The address logic module is configured to set the address boundary to the minimum possible value of the storage module when the system is started, and to check whether the new set value of the address boundary is greater than the previous value, and if this is the case, to adopt the set value of the address boundary. The address logic module is configured to grant access to the processing unit if the access address corresponds in value to at least the value of the address boundary and / or is greater in value than the value of the address boundary.

[0051] This advantageously enables flexible access control of the memory modules of the proposed memory control device by means of an implementation in the firmware. Various data or data elements can be stored in the individual memory cells of the memory module in ascending order. Immediately after uploading the firmware, all memory cells (data elements) are accessible. During the boot process (boot vorganges), write access or read access to the memory cells of the memory area of ​​the memory module can be continuously restricted in that at least one of the changeable address boundaries is set to a higher or larger value. Since the address boundary register can no longer be reset to a smaller value in the further process, access to the data contained in these memory cells can be effectively prevented for less privileged components of the firmware.

[0052] For the ascending realization of the address boundaries, it is necessary that the starting address of the address boundary register points to the lowest address of the storage module after the startup process (reset). Alternatively, the starting address can be set to zero. Here, the starting address can correspond to the address boundary that can be changed. After that, the change by the register write access to the address boundary register will only succeed if the newly written address boundary is greater than the current (changeable address boundary).

[0053] In another embodiment, the address boundary register can be implemented in descending order in the address boundaries. The software module of the processing unit is configured to set the at least one address boundary of the address boundary register in descending order in terms of value. The software module of the processing unit is also configured to transmit the set value to the address logic module.

[0054] The address logic module is designed to set the address boundary to the maximum possible value of the memory module when the system is started, and to check whether the new set value of the address boundary is less than the previous value and, if this is the case, to adopt the set value of the address boundary. The address logic module is designed to grant access to the processing unit if the access address at least corresponds in value to the value of the address boundary and / or in value is lower than the value of the address boundary.

[0055] This implementation is advantageously possible if the start address of the address boundary register points to the uppermost or maximum address after the startup process (reset). In this case, the start address can correspond to the changeable address boundary. Thereafter, a change by a register write access to the address boundary register will only succeed if the newly written address boundary is smaller than the current (changeable address boundary).

[0056] In another embodiment, at least one first address boundary register and a second address boundary register can be implemented, which can be configured independently of each other. Advantageously, independent access areas are possible, wherein the access areas can be implemented, for example, as a combination of the above-mentioned ascending and descending realization of the address boundaries of the independent address boundary registers. In this case, it is conceivable that firmware artifacts are stored in the first address boundary register (access addresses are blocked in the lower address area) and are protected by an ascending realization of the address boundaries of the first address boundary register, while security keys and fine-tuning data are stored in the second address boundary register (upper address area is blocked for access addresses) and are protected by a descending realization of the address boundaries of the second address boundary register.

[0057] In another embodiment, the address logic module includes a converter element. The converter element is configured to switch from at least one first address boundary register to a second address boundary register and / or the converter element is configured to switch from at least one second address boundary register to the first address boundary register. The first address boundary register and the second address boundary register can each be configured independently of one another.

[0058] Advantageously, the address boundary registers, which are designed independently of one another, can be designed according to the type of write access or read access and, for example, depict different rights of the processing unit. Here, the processing unit can be designed as a processor or a CPU. The different rights of the processing unit form, for example, a kernel mode (operating system, protected mode) and a user mode (software, unprotected mode). Therefore, the kernel mode and the user mode (or protected mode and unprotected mode) can be designed as independent address boundary registers with the above-mentioned features regarding the address boundaries that can be changed.

[0059] In another embodiment, the address boundary register with the changeable address boundaries has a maximum value during a startup process, in particular a software power-up process and / or a hardware reset process, which maximum value is designed to be reduced after the startup process. Advantageously, the address boundary register can only be reduced and not increased after the startup process, so that data or data elements worth protecting can be protected simply and reliably in the lower or upper part of the address boundary register. Because these data or data elements are not accessible outside the access area (for example, as defined above, depending on the implementation of one or more address boundary registers). In this case, the startup process and the startup program can be understood as synonyms.

[0060] In addition, a MEMS structural element is proposed, comprising:

[0061] a MEMS element which is designed as a sensor element, in particular as an inertial sensor element, and

[0062] An evaluation circuit comprises a microprocessor system having a memory controller which has the above-described features and is designed to carry out the above-described method for operating a memory module.

[0063] Advantageously, the MEMS structural element can be designed flexibly and, as required, can also form a micromechanical sensor system comprising a plurality of sensor elements, which can include the above-mentioned memory control device. The analysis and processing circuit can be realized, for example, by an ASIC element comprising a microprocessor system and a memory control device. This advantageously saves installation space. In addition, it is conceivable that the MEMS structural element forms a microelectromechanical system.

[0064] The implementation of a memory controller (i.e., a memory access controller) has the advantage that it can be implemented with very little hardware expenditure and logic area on the sensor ASIC and still achieves a strong protection effect for the protected memory area. This is particularly advantageous for implementation in MEMS sensors, since the ASICs used there are limited in area due to the size of the structure and therefore more complex memory access controllers are disadvantageous due to their logic area. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The above characteristics, features and advantages of the present invention and their implementation methods will become more clearly and clearly understandable in conjunction with the following description of the embodiments, which are explained in more detail in conjunction with the schematic drawings. The drawings show:

[0066] Figure 1 A schematic diagram of a method for operating a storage module;

[0067] Figure 2a Figure 1 A schematic diagram of an implementation of an address boundary register with ascending address boundaries of the method of FIG.

[0068] Figure 2b Figure 1 A schematic diagram of an implementation of an address boundary register with address boundaries in descending order according to the method of FIG.

[0069] Figure 2c Figure 1 A schematic diagram of an implementation scheme of two independent address boundary registers in ;

[0070] Figure 3a With the help of trigger structural elements Figure 2a A schematic diagram of an implementation scheme of an address boundary register in FIG.

[0071] Figure 3b With the help of trigger structural elements Figure 2b A schematic diagram of an implementation scheme of an address boundary register in FIG.

[0072] Figure 4a Based on Figure 2a and 3a A schematic diagram of a memory control device for implementing an address boundary register having ascending address boundaries;

[0073] Figure 4b Based on Figure 2b and 3b A schematic diagram of a memory control device for implementing an address boundary register having address boundaries in descending order;

[0074] Figure 4c have Figure 2cA schematic diagram of a memory control device for implementing two independent address boundary registers;

[0075] Figure 4d Based on Figure 2c and 4c A schematic diagram of a memory control device for implementing two independent address boundary registers;

[0076] Figure 5 Schematic diagram of MEMS structural elements. DETAILED DESCRIPTION

[0077] It is pointed out that the drawings are only schematic in nature and are not drawn to scale. In this sense, the parts and elements shown in the drawings may be shown larger or smaller for a better understanding. It is also pointed out that if elements and / or parts of the same or similar construction are involved, the reference numerals in the drawings are selected to be constant or similar.

[0078] Figure 1 A schematic diagram of a method 100 for operating a storage module 200, 300, 400 is shown. Figures 2a to 2c A possible implementation of the storage modules 200, 300, 400 is shown in FIG.

[0079] Figure 1 The method 100 in the embodiment of the present invention comprises: in a first step 105, a storage module 200, 300, 400 is provided, wherein the storage module 200, 300, 400 comprises a storage area 205, 305, 405 ( Figure 1 1 ). A second step 110 of the method 100 comprises providing at least one address boundary register 215, 315, 415, 417 having at least one address boundary 225, 325, 425, 455 that can be changed in value at least in one direction. Providing the at least one address boundary register in the second step 110 comprises being able to set the address boundary 225, 325, 425, 455 to a new value and being able to check whether the new value has changed in a direction that is allowed in value.

[0080] Advantageously, it is not necessary to have to make provisions for the size and access restrictions of the memory module 200, 300, 400 with the memory area 205, 305, 405 during the hardware design. With the proposed address boundary register 215, 315, 415, 417 having at least one address boundary 225, 325, 425, 455 that can be changed in value in one direction, provisions for access, in particular write access and / or read access to the data of the memory unit can be made flexibly in the firmware, i.e. in the software. This advantageously makes it possible to handle the access flexibly and to change the access, for example, also by updating the firmware.

[0081] In a third step 115 of method 100 , when accessing, in particular writing and / or reading, data of memory cells 210 , 310 , 410 of memory modules 200 , 300 , 400 is performed, it is checked whether the access is permitted and, if so, the access is performed.

[0082] In order to access the memory module, an access range of possible access addresses 240, 340, 440, 475 is determined. Outside this access range, no read access and / or write access is possible. Thus, if the access address 245, 345, 445, 480 is not located within the corresponding access range (this can vary depending on the implementation of the address boundary register), then, for example, the access is not allowed.

[0083] Let's describe it together Figure 2a , 3a and 4a. Figure 2a Show Figure 1 1 is a schematic diagram of an implementation of the address boundary register 215 with ascending address boundaries 250 of the method 100, and Figure 3a The trigger element 31 is shown Figure 2a Schematic diagram of an implementation of an address boundary register 215 in , which flip-flop structural element can be set, for example, using program code (C++ or the like). Figure 4a Shown according to Figure 2a and 3a Schematic diagram of a memory control device 500 showing an implementation of an address boundary register 215 having address boundaries 250 arranged in ascending order with respect to value.

[0084] Figure 2a The address boundary register 215 in the address boundary is implemented in ascending order 250. When the system is started, especially the software power-on process and / or the hardware reset process, the address boundary register 215 has a minimum value of "zero", which is configured to be able to increase after the system is started. Figure 2a2 also shows a region 220 of the address boundary register 215 for possible address boundaries. This region 220 is designed to be the largest at system startup and can be reduced thereafter by the address boundary register 215 being implemented in ascending order 250 in the address boundaries. Figure 3a The digital trigger structure element 31 in Figure 2a In the implementation of the address boundary register 215 of , the start process is indicated by a reset input R (here in the form of a reset 40). This can include the value "zero". It is understood that in alternative configurations, minimum values ​​other than the value "zero" are also conceivable here. The digital trigger structural element 31 (flip-flop gate) is a structural element controlled by a clock signal 35 (clock). Figure 3a In FIG. 1 , the clock switching symbol 60 (or dynamic input) of the flip-flop structural element 31 is represented.

[0085] The data can be stored in a plurality of storage units 210, for example, in ascending order (in an alternative configuration, it is also conceivable, for example, according to Figure 2b , wherein the data may form calibration data, security keys, fine-tuning data, etc., as explained at the beginning). Immediately after the boot process or after uploading the firmware (i.e. software), all memory cells are accessible, wherein it should be understood that the memory cell 210 is only used as an example for explaining the reference numeral 210 and this is not to be understood as a restriction in the sense of a single memory cell 210. During the boot process, write access and / or read access to the data of the memory cells can be continuously restricted in that the at least one address boundary 225 changes in value in one direction.

[0086] Specifically, the address boundary 225 of the address boundary register 215 is set in the ascending direction of the address boundary in the ascending order 250 implementation scheme, for example, by register write access (via the processing unit 505 or the software module 510), and the set value is transmitted to the address logic module 515. The address logic module 515 may include Figure 3a The address logic module 545 or the flip-flop structural element 31 is designed to check the new value of the address boundary (in Figure 3a is greater than the previous value of the at least one address boundary 225 (in Figure 3a ) and, if this is correct (together with the request 10 via the AND element 50), the set value is adopted. Then, setting the at least one address boundary 225 to a new address boundary with a larger value is allowed via a register write access ( Figure 3aThe address boundary set in 55). Figure 3a In the address bus, N represents the bus width of the address bus.

[0087] therefore, Figure 2a The possible access address 240 in is the new value corresponding to the address boundary 225 in terms of value ( Figure 3a b) and / or a new value that is above address boundary 225 in value ( Figure 3a b) in the access address. For such an access address 240, a write access and / or a read access is performed depending on the access type. Therefore, the address boundary register 215 implemented as a flip-flop structural element 31 can be moved in the arrow direction 233 about the address boundary of the ascending order 250. If the access address is outside the access area, Figure 2a The access area of ​​the type is formed by the access address 240 (according to Figure 2a , the blocked access address 245 is outside the access area), then the access to the data of the storage unit 210 is not performed and an error message (exception, English: exception) is generated. Therefore, the movement of the address boundary 225 in the direction of the arrow 235 (ie, to a smaller value) is not possible.

[0088] Figure 4a The memory control device 500 is shown with a processing unit 505 and the memory module 200 explained above with the address boundary register 215 having the address boundaries in ascending order 250. The processing unit 505 (e.g., a processor) is operatively connected to the memory module 200 via a bus system 507. An address logic module 515 is also operatively connected between the processing unit 505 and the memory module 200 via the bus system 507 (not shown here). Figure 3a 31 in the flip-flop structure element, which shows the implementation of the address boundary register 215 in hardware, which is part of the address logic module 515). M, n represent the respective bus widths, m represents the width of the data bus, and n represents the width of the address bus, for example, n = 10-bit bus width and m = 32-bit bus width. Different bus widths are also possible.

[0089] The storage module 200 can be designed as a non-volatile memory (NVM) and can have, for example, a flash memory architecture (for example, if security keys are stored that should no longer be readable from a certain point in time during the boot procedure). Alternatively, it is conceivable that the storage module 200 is designed as a volatile memory and has, for example, a RAM memory architecture (RAM: random access memory) (for example, if data that should be protected for subsequent read access and / or write access are generated during the boot procedure of the system).

[0090] The address logic module 515 is designed to provide the above-mentioned address boundary register 215 with the at least one changeable address boundary 225 for access.

[0091] exist Figure 4a In the illustration in , the address logic module 515 comprises a first logic comparator element 520 and a second logic comparator element 525. For example, the first logic comparator element 520 is linked to a write access 540 to the data of the memory cell 210 of the memory module 200, and the second logic comparator element 525 is linked to a read access 545 to the data of the memory cell 210 of the memory module 200. This is exemplarily selected in this illustration, it being understood that only one logic comparator element 520, 525, respectively, may be used when performing an exclusive write access 540 or an exclusive read access 545 to the data of the memory cell 210 of the memory module 2005.

[0092] Here, according to Figure 3a The address boundary 225 is changed by the interpretation of Figure 4a b in represents a possible access address 240 and a represents the current value of the address boundary 225. A first AND element 530 is connected to a first logic comparator element 520 and to an exemplary write enable request 10 of the processing unit 505 to the memory module 200 via the bus system 507. This write access request 10 is complied with by the address logic module 515 - i.e. 15 data elements (write_data) are written in the memory cell if the access address 240 corresponds in value to the address boundary 225 of the address boundary register 215 when compared with the address boundary 525 of the address boundary register by the logic comparator element 520 or if the access address 240 is above the address boundary 225 of the address boundary register 215 which can be changed in value.

[0093] This also applies analogously to the second logic comparator element 525 and the second AND element 535 for the read request 20 (read_enable) and for reading the data element 25 (read_data) from the memory cell 210 of the memory module 200 .

[0094] The software module 510 of the processing unit 505 is designed to set a new value for the address boundary 225 and to transfer the new value of the address boundary 225 to the address logic module 515 which provides the address boundary register 215. The address logic module 515 or the flip-flop structural element 31 is designed to check whether the set value of the address boundary is greater than the previous value of the at least one address boundary 225 and, if correct, to adopt the set (larger) value to the address logic module 515. This applies without restriction to both read access and write access.

[0095] In the ascending implementation 250, the address boundary register 215 can no longer be reset to the small value of the address boundary in the further process. Therefore, for the firmware or the less privileged parts of the software, access to these memory cells can be effectively prevented.

[0096] Possible application examples may include: storing a key for decrypting another firmware component or software component in a storage unit at the lower end of the storage module 200, that is, at the lower end of the storage module 200. After the firmware / software has completed decryption, an address boundary 225 (as a read address boundary) that can be changed in an ascending direction in terms of value may be set above the key (e.g., Figure 2a The shaded area in FIG. 1 is used as the area for the key, so that it is no longer possible to read the key in the further process until the next startup process or reset.

[0097] Alternative application examples may include the possibility of storing calibration data for a MEMS structural element (e.g. an inertial sensor) configured as a sensor in one or more memory cells of a storage module 200, the MEMS structural element comprising the memory control device 500 explained above. For example, these data can only be written in a special calibration mode of the firmware / software of the sensor. If the firmware determines after a startup process (i.e. after uploading) that the firmware / software of the sensor is in operating mode, write access to these data can be blocked by setting the address boundary 225 for write access to a new value, which is greater in value than the previous value of the address boundary 225, in order to protect the calibration data (e.g. Figure 2a The shaded area in the figure is used as the area for calibration data).

[0098] It should be understood that the application example can also be used for the descending implementation 353 of the address boundary, and then the data to be protected are respectively saved in the upper area of ​​the address boundary register 315.

[0099] Let's describe it together Figure 2b , 3b and 4b, wherein the differences from the preceding figures are particularly explained.

[0100] Figure 2b Show Figure 1 Schematic diagram of an implementation of the address boundary register 315 with address boundaries 353 in descending order of the method in Figure 3b The trigger element 33 is shown Figure 2b Schematic diagram of the implementation scheme of the address boundary register in . Figure 4b Shown according to Figure 2b and 3b Schematic diagram of a memory control device 300 showing an implementation of an address boundary register 315 having address boundaries 353 in descending order.

[0101] If the new value of the address boundary ( Figure 3b b) is less than the previous value of address boundary 325 ( Figure 3b a), then the address boundaries 325 of the address boundary register 315 in the implementation of the address boundary descending order 353 are set in the direction of descending order in terms of value. Figure 3b , corresponds to the logical comparator element 45. The at least one address boundary 325 is then set to a new (smaller) value 55. Figure 3b The trigger structure element 33 in Figure 3a The difference between the structural elements 31 in the embodiment is the different arrangement of the reset input (in Figure 3b The reset input is marked by S).

[0102] therefore, Figure 2b The possible access addresses 340 for accessing the data in the memory cell 210 are access addresses which correspond in value to the new address boundary 325 and / or which are below the new address boundary 325 in value. For such access addresses 340, a write access and / or a read access is performed depending on the access type. Thus, the address boundary register 315 implemented as a flip-flop structural element 33 can be moved in the arrow direction 333 about the address boundary in descending order 353.

[0103] The address logic of address logic module 615 is constructed similar to Figure 4a The embodiment of the present invention has the following differences: the first logic comparator element 620 and the second logic comparator element 625 are respectively based on Figure 3b The logic component 45 is used to check the possible access address 340 or the new address boundary.

[0104] Let's describe it together Figure 2c , 4c and 4d, wherein the differences from the preceding figures are emphasized.

[0105] Figure 2c Shows the Figure 11 is a schematic diagram of an implementation of two independent address boundary registers 415, 417 of the method 100, and, Figure 4c Regarding the write access 740 of the data of the storage unit 210 using each address boundary register 415, 417, it is shown that Figure 2c Schematic diagram of a memory control device 700 for implementing two independent address boundary registers 415, 417 in FIG. In the case of a first address boundary register 415, the independent address boundary registers 415, 417 can be configured in an ascending order 450 in the address boundary, i.e. in an ascending direction in terms of value of a changeable address boundary 425, and possible access addresses 440 can be depicted by changing the value of the address boundary 425 to a larger value (moving the arrow in the direction 433). See also Figure 2a , 3a and interpretation of 4a.

[0106] The second address boundary register 417 is constructed in descending order 453 in the address boundaries, ie in the at least one changeable address boundary 455. Possible access addresses 475 can be depicted by changing the value of the address boundary 455 to a smaller value (moving the arrow in the direction 465). Figure 2b , 3b and 4b.

[0107] It should be understood that the above-mentioned access type to the data of the storage unit 210 should not be limited to the two address boundary registers 415, 417, but can also be constructed in the form of read access or write access and read access. Each of the address boundary registers 415, 417 can respectively include an address logic module 715, 715 having the above-mentioned components.

[0108] Figure 4d Shown according to Figure 2c and 4c Schematic diagram of a memory control device 800 that implements two independent address boundary registers 415 and 417.

[0109] Unlike the drawings mentioned, Figure 4dThe memory control device 800 in FIG. 8 has only one address logic module 819. The address logic module 819 also includes a converter element 823 (multiplexer), which is connected upstream of the logic comparator element 820 and the AND element 830. The processing unit 805 can have different permissions (or modes), which is represented by the protection call 30 toward the converter element 823. Different permissions can form a kernel (operating system) and a user (software / firmware) or a kernel mode and a user mode. The converter element 823 is configured to switch from the first address boundary register 415 to the second address boundary register 417 and / or from the second address boundary register 417 to the first address boundary register 415. The first address boundary register 415 and the second address boundary register 417 are respectively configured independently of each other. In the illustrated example, the first address boundary register 415 forms a kernel register, and the second address boundary register 417 forms a user register. The user mode calls the kernel mode, which requires a switch between registers 415 , 417 , wherein in kernel register 415 , for example, a check is made to see whether access is permitted, ie whether access is possible, after the above sequence.

[0110] Figure 5 A schematic diagram of a MEMS component 900 is shown. The MEMS component 900 includes a MEMS element, which is configured as a sensor element 905, in particular as an inertial sensor element. The sensor element 905 is connected to an evaluation circuit 65 via an operational connection 909, wherein the evaluation circuit 65 can be configured as an ASIC and can include a microprocessor system (not shown) with a memory control device 500, 600, 700, 800. The memory control device 500, 600, 700, 800 can be configured according to the above explanation. The memory control device 500, 600, 700, 800 is configured to execute the method 100 for operating the memory module 200, 300, 400.

[0111] The present invention can be used in conjunction with smartphones and tablets, wearables, hearables, AR and VR, drones, games and toys, robotics, personal digital assistants, smart homes and in industrial settings, in particular for the following applications:

[0112] Significant motion recognition, free fall recognition, context recognition, gesture control, stable altitude, floor recognition, flight control, elderly care, calorie counter, navigation inside and outside buildings, location tracking, restriction and obstacle recognition; Detection of wearing status of headphones / earbuds (hearable devices) as in-ear detection, determination of head orientation and head movement.

[0113] MEMS systems are used in various computer-controlled devices, such as robots, household appliances, production facilities, access control systems, vehicles (e.g. autonomous vehicles), and for active and passive safety, such as for ESP, rollover sensing, etc., and in driver assistance systems.

[0114] The present invention has been described in detail by means of preferred embodiments. Instead of the described embodiments, further embodiments are conceivable, which may have further modifications or combinations of the described features. For this reason, the present invention is not limited to the disclosed examples, since those skilled in the art may derive other variants therefrom without departing from the scope of protection of the present invention.

Claims

1. A method (100) for operating a storage module (200, 300, 400), comprising the following steps: In a first step (105), a memory module (200, 300, 400) is provided, wherein the memory module (200, 300, 400) comprises a memory area (205, 305, 405) having a plurality of memory cells (210, 310, 410), the memory cells having data, In a second step (110), at least one address boundary register (215, 315, 415, 417) is provided having at least one address boundary (225, 325, 425, 455), which address boundary can be changed in value at least in one direction, wherein providing said at least one address boundary register in said second step (110) comprises being able to set said address boundary to a new value, and being able to check whether said new value has changed in a direction permitted in terms of value, and In a third step (115), when accessing, in particular writing and / or reading, data of the storage unit (210, 310, 410) of the storage module (200, 300, 400) is performed, it is checked whether the access is permitted, and if the access is permitted, the access is performed.

2. The method according to claim 1, in, The at least one address boundary register (215, 315, 415, 417) is designed as a digital flip-flop structural element (31, 33), In this case, based on the logic comparator element (45) it is possible to check whether the new value of the address boundary has changed in a direction that is permitted in terms of value.

3. The method according to any one of claims 1 to 2, in, The address boundary register (215, 415) is capable of being implemented in ascending order (250, 450) in the address boundary (225, 230, 425, 430), and the address boundary is set to the minimum possible value of the storage module (200, 300, 400) at system startup, wherein, if the new value of the address boundary is greater than the previous value of the address boundary (225, 425), the at least one address boundary (225, 425) is set in an ascending direction in terms of value in an implementation of an ascending order (250, 450) of the address boundaries (225, 230, 425, 430), and, In this case, the access is performed in the third step (115) if the access address (240, 440) corresponds in value to at least the value of the address boundary and / or in value to a value above the address boundary.

4. The method according to any one of claims 1 to 3, in, The address boundary register (315, 417) is capable of being implemented in descending order (353, 453) in the address boundary (325, 330, 455, 460), and the address boundary is set to the maximum possible value of the storage module (200, 300, 400) when the system is started, wherein the at least one address boundary (325, 455) is set in a descending direction in terms of value in a descending implementation (353, 453) if the new value of the address boundary is less than the previous value of the address boundary (225, 425), and In this case, the access is performed in the third step (115) if the access address (340, 475) corresponds in value to at least the value of the address boundary and / or lies below the value of the address boundary.

5. The method according to any one of the preceding claims, in, At least one first address boundary register (415) and a second address boundary register (417) can be implemented, each of which can be configured independently of each other, wherein the first address boundary register (415) is implementable in the address boundaries (425, 430) in ascending order (250, 450), and the second address boundary register (417) is implementable in the address boundaries (455, 460) in descending order, and / or The first address boundary register (415) can be implemented for write access, and the second address boundary register (417) can be implemented for read access.

6. A memory control device (500, 600, 700, 800), comprising: a processing unit (505, 605, 705, 805) which is operatively connected to a storage module (200, 300, 400) via a bus system (507, 607, 707, 807), the storage module being in particular designed as a non-volatile memory, The storage module (200, 300, 400) includes a storage area (205, 305, 405) having a plurality of storage units (210, 310, 410), wherein the storage units have data. The memory control device comprises an address logic module (515, 615, 715, 819), and the address logic module is operatively connected to the processing unit (505, 605, 705, 805) and the storage module (200, 300, 400) via the bus system (507, 607, 707, 807). wherein the address logic module (515, 615, 715, 819) is configured to provide at least one address boundary register (215, 315, 415, 417) having at least one address boundary (225, 325, 425, 455), wherein the processing unit (505, 605, 705, 805) comprises a software module (510, 610, 710, 810) which is designed to change the at least one address boundary (225, 325, 425, 455) in terms of value at least in one direction, wherein the address logic module (515, 615, 715, 819) is designed to set the address limit to a new value and to check whether the new value has changed in a direction that is permitted in terms of value, The address logic module (515, 615, 715, 819) includes at least one further logic comparator element (520, 525, 620, 625, 720, 725, 820), wherein the at least one further logic comparator element (520, 525, 620, 625, 720, 725, 820) is constructed for checking whether the access, in particular the write access and / or the read access, to the data of the storage unit (210, 310, 410) is permitted and, if the access is permitted, executing the access.

7. The memory control device according to claim 6, in, The at least one address boundary register (215, 315, 415, 417) is constructed as a digital flip-flop structural element (31, 33), and The digital trigger element (31, 33) is designed to check, based on the logic comparator element (45), whether the new value of the address boundary has changed in a direction that is permissible in terms of value.

8. The memory control device according to any one of claims 6 to 7, in, The software module (510, 710, 810) of the processing unit (505, 705, 805) is designed to set the at least one address boundary (225, 425) of the address boundary register (215, 415) in ascending order (250, 450) with respect to value, wherein the software module (510, 710, 810) of the processing unit (505, 705) is configured to transmit the set value to the address logic module (515, 715, 819), The address logic module (515, 715, 819) is configured to set the address boundary (225, 425) to the minimum possible value of the storage module (200, 300, 400) at system startup, and to check whether the new value of the address boundary is greater than the previous value of the address boundary (225, 425), and if this is the case, to adopt the set value of the address boundary (225, 425), The address logic module (515, 715, 819) is designed to allow the processing unit (505, 705) to perform the access if the access address (240, 440) corresponds in value to at least the value of the address boundary and / or exceeds the value of the address boundary.

9. The memory control device according to any one of claims 6 to 7, in, The software module (610, 710, 810) of the processing unit (605, 705, 805) is designed to set the at least one address boundary (325, 455) of the address boundary register (315, 417) in descending order with respect to value, wherein the software module (610, 710, 810) of the processing unit (605, 705, 805) is configured to transmit the set value to the address logic module (615, 715, 819), The address logic module (615, 715, 819) is configured to set the address boundary (325, 455) to the maximum possible value of the storage module (200, 300, 400) when the system is started, and to check whether the new set value of the address boundary is smaller than the previous value of the at least one address boundary (325, 455), and if this is the case, to adopt the set value of the address boundary, The address logic module (615, 715, 819) is designed to allow the processing unit (605, 705, 805) to perform the access if the access address (340, 475) corresponds in value to at least the value of the address boundary and / or lies below the value of the address boundary.

10. The memory control device according to any one of the preceding claims, in, The address logic module (819) includes a converter element (823), wherein the converter element (823) is configured to switch from at least one first address boundary register (415) to a second address boundary register (417), and / or wherein the converter element (823) is configured to switch from at least one second address boundary register (417) to a first address boundary register (415), and In this case, the first address limit register (415) and the second address limit register (417) can each be designed independently of one another.

11. A MEMS structural element (900), comprising: a MEMS element, which is designed as a sensor element (905), in particular an inertial sensor element, and An evaluation circuit (65) comprising a microprocessor system having a memory control device (500, 600, 700, 800) configured according to any one of claims 6 to 10, The memory control device (500, 600, 700, 800) is designed to carry out a method (100) for operating a memory module (200, 300, 400) according to any one of claims 1 to 5.

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