Semiconductor device, preparation method thereof and power device

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and a power device, and relates to the technical field of semiconductors. The preparation method of the semiconductor device comprises the steps of providing a substrate, wherein the substrate comprises a cellular region and a peripheral region which are adjacent to each other; forming a first dielectric layer, wherein the first dielectric layer is arranged on the substrate; forming a shielding structure and a first gate structure; forming a second dielectric layer, filling the recess region with the second dielectric layer, and covering the first gate structure; part of the second dielectric layer and part of the first dielectric layer are removed, and a filling groove is defined by the reserved second dielectric layer and the substrate; the first dielectric layer which is reserved and located on the substrate forms a first mask structure; forming a second gate structure in the filling groove; and doping the exposed substrate by taking the first mask structure as a mask to form a first doped region and a second doped region. According to the embodiment of the invention, the preparation process of the semiconductor device can be simplified, and the preparation difficulty of the semiconductor device is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same, and a power device. Background Art

[0002] Shielded gate trench field effect transistors have lower on-resistance and faster switching speed and are widely used in power devices.

[0003] A shielded gate trench field effect transistor generally includes a substrate, a shielding gate, a transistor and a diode arranged in the substrate. The shielding gate is used to reduce leakage current and improve the voltage resistance performance of the field effect transistor. However, the preparation process of the shielded gate trench field effect transistor is relatively complicated and difficult to prepare. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and a power device, which can simplify the manufacturing process of the semiconductor device and thereby reduce the difficulty of manufacturing the semiconductor device.

[0005] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] A first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a substrate, the substrate comprising a cell region and a peripheral region adjacent to each other;

[0008] forming a first dielectric layer, wherein the first dielectric layer is disposed on the substrate;

[0009] A shielding structure and a first gate structure are formed; the shielding structure is arranged in the cell region and extends into the substrate, wherein a top surface of the shielding structure and a top surface of the first dielectric layer form a recessed region; the first gate structure is arranged in the peripheral region and extends into the substrate;

[0010] forming a second dielectric layer, wherein the second dielectric layer completely fills the recessed area and covers the first gate structure;

[0011] removing part of the second dielectric layer and part of the first dielectric layer, and the remaining second dielectric layer and the substrate enclose a filling groove; wherein the remaining first dielectric layer located on the substrate constitutes a first mask structure, and the first mask structure covers the first gate structure and part of the peripheral area;

[0012] forming a second gate structure in the filling groove;

[0013] Using the first mask structure as a mask, the exposed substrate is doped to form a first doping region and a second doping region, wherein the first doping region is located between the first gate structure and the second gate structure, and the second doping region is located on a side of the first gate structure away from the second gate structure.

[0014] In a possible implementation manner, the top surface of the second dielectric layer is flush with the top surface of the first dielectric layer.

[0015] In a possible implementation manner, the step of forming the shielding structure and the first gate structure includes:

[0016] Patterning the first dielectric layer and the substrate to form a first groove and a second groove, wherein the first groove and the second groove are respectively located in the cell region and the peripheral region;

[0017] A shielding structure is formed in the first trench and a first gate structure is formed in the second trench.

[0018] In a possible implementation, the shielding structure includes a first barrier layer, a first gate dielectric layer, and a shielding gate which are stacked in sequence, and the first barrier layer is arranged on the inner wall of the first trench; wherein the shielding structure includes a first groove, and the first groove surrounds at least a portion of the shielding gate;

[0019] The first gate structure includes a second barrier layer, a second gate dielectric layer and a first gate which are stacked in sequence, and the second barrier layer is arranged on the inner wall of the second trench; wherein the first gate structure includes a second groove, and the second groove surrounds a portion of the first gate.

[0020] In a possible implementation manner, the step of removing a portion of the second dielectric layer and a portion of the first dielectric layer includes:

[0021] forming a second mask structure, wherein the mask structure covers a portion of the peripheral region and exposes the second dielectric layer and the first dielectric layer located on the cell region;

[0022] Using the second mask structure as a mask, a portion of the second dielectric layer exposed on the cell region is removed, so that the top surface of the remaining second dielectric layer is lower than the top surface of the first dielectric layer and encloses the filling groove with the substrate; and the exposed first dielectric layer is removed, and the remaining first dielectric layer constitutes a first mask structure.

[0023] In a possible implementation, the step of forming a second gate structure in the filling groove includes:

[0024] forming a second gate dielectric layer, wherein the second gate dielectric layer covers the inner wall of the filling groove and covers the top surface of the substrate;

[0025] A second gate is formed, and the second gate completely fills the area enclosed by the second gate dielectric layer in the filling groove; the second gate dielectric layer and the second gate constitute a second gate structure.

[0026] In a possible implementation manner, after the step of forming the first doping region and the second doping region, the method includes:

[0027] The first doping region and the second doping region are thermally treated.

[0028] In a possible implementation manner, after the step of forming the first doping region and the second doping region, the method includes:

[0029] forming a third mask structure, wherein the third mask structure covers the second doping region;

[0030] The first doping region is doped using the first mask structure and the third mask structure as masks to form a third doping region in the first doping region; wherein the conductivity type of the first doping region is the same as the conductivity type of the second doping region and different from the conductivity type of the third doping region.

[0031] In a possible implementation manner, after the step of forming the third doping region, the method further includes:

[0032] removing the third mask structure;

[0033] forming an insulating layer, wherein the insulating layer covers the third doping region, the second gate structure, the first mask structure and the second doping region;

[0034] Conductive plugs are formed in the insulating layer, the conductive plugs including a first conductive plug, a second conductive plug, a third conductive plug and a fourth conductive plug, the first conductive plug is electrically connected to the second gate, the second conductive plug is electrically connected to the first doped region, the third conductive plug is electrically connected to the first gate, and the fourth conductive plug is electrically connected to the second doped region.

[0035] In a possible implementation manner, before the step of forming the conductive plug, the method further includes:

[0036] A heavily doped region is formed, wherein the heavily doped region is disposed at an end of the conductive plug facing the substrate.

[0037] A second aspect of an embodiment of the present application provides a semiconductor device, comprising:

[0038] A substrate, the substrate comprising adjacent cellular regions and peripheral regions;

[0039] A shielding structure, the shielding structure is arranged in the cell region and extends into the substrate;

[0040] a first gate structure, the first gate structure being disposed in the peripheral region and extending into the substrate;

[0041] a second dielectric layer, the second dielectric layer being disposed on the shielding structure and forming a filling groove with the substrate;

[0042] a second gate structure, the second gate structure being disposed in the filling groove;

[0043] a first doping region and a second doping region, the first doping region being located between the first gate structure and the second gate structure, and the second doping region being located on a side of the first gate structure away from the second gate structure;

[0044] A first mask structure is disposed on the substrate and covers the first gate structure and a region between the first gate structure and the second doping region.

[0045] In a possible implementation manner, the second dielectric layer wraps a portion of the outer circumference of the shielding structure and covers the top surface of the shielding structure.

[0046] In a possible implementation manner, a third doping region is further included, where the third doping region is disposed on the first doping region, and a conductivity type of the third doping region is different from a conductivity type of the first doping region.

[0047] A third aspect of an embodiment of the present application provides a power device, comprising the semiconductor device described in the second aspect.

[0048] In the semiconductor device and its preparation method and power device provided by the embodiment of the present application, when the second dielectric layer is etched back, part of the first dielectric layer and the second dielectric layer are removed simultaneously, so that the first dielectric layer retained and located on the substrate constitutes a first mask structure; the first mask structure can be used as a mask, and then an ion doping process can be used to form a first doping region and a second doping region. In this way, the process of re-preparing the mask layer can be simplified, thereby improving the efficiency of the preparation method and the yield of the semiconductor device, and reducing the manufacturing cost.

[0049] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor devices and their preparation methods, power devices provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 A process flow chart of a method for preparing a semiconductor device is provided for an embodiment of the present application;

[0052] Figure 2 A schematic diagram of forming a first dielectric layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0053] Figure 3 A schematic diagram of forming a first photoresist layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0054] Figure 4 A schematic diagram of forming a first trench and a second trench in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0055] Figure 5 A schematic diagram of forming a first barrier material layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0056] Figure 6 A schematic diagram of forming a first gate material layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0057] Figure 7 Schematic diagram of removing part of the first gate material layer in the method for preparing a semiconductor device provided in an embodiment of the present application Figure 1 ;

[0058] Figure 8 Schematic diagram of removing part of the first gate material layer in the method for preparing a semiconductor device provided in an embodiment of the present application Figure 2 ;

[0059] Fig. 9 A schematic diagram of forming a shielding gate in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0060] Fig.10 A schematic diagram of forming a shielding structure and a first gate structure in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0061] Fig.11 A schematic diagram of forming a second dielectric material layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0062] Fig.12 A schematic diagram of removing part of the second dielectric material layer in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0063] Fig.13 A schematic diagram of forming a second dielectric layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0064] Fig.14 A schematic diagram of removing part of the first dielectric layer in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0065] Fig.15 A schematic diagram of forming a first mask structure in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0066] Fig.16 A schematic diagram of forming a third gate dielectric layer in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0067] Fig.17 A schematic diagram of forming a second gate material layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0068] Fig.18 A schematic diagram of forming a second gate structure in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0069] Fig.19 A schematic diagram of forming a first doping region and a second doping region in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0070] Fig. 20 A schematic diagram of the first doping region and the second doping region after heat treatment in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0071] Fig.21 A schematic diagram of forming a third mask structure in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0072] Fig. 22 A schematic diagram of forming a third doping region in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0073] Fig.23 A schematic diagram of forming an insulating layer in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0074] Fig.24 A schematic diagram of forming a third photoresist layer in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0075] Fig.25 Schematic diagram of forming an etched hole in the method for preparing a semiconductor device provided in an embodiment of the present application Figure 1 ;

[0076] Fig.26 Schematic diagram of forming an etched hole in the method for preparing a semiconductor device provided in an embodiment of the present application Figure 2 ;

[0077] Fig. 27 A schematic diagram of forming a heavily doped region in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0078] Fig.28 Schematic diagram of forming an etched hole in the method for preparing a semiconductor device provided in an embodiment of the present application Figure 3 ;

[0079] Fig.29 A schematic diagram of forming a conductive plug in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0080] Fig.30 A schematic diagram of forming an interconnection layer in a method for preparing a semiconductor device provided in an embodiment of the present application.

[0081] Description of reference numerals:

[0082] 10: substrate; 11: cell region; 12: peripheral region; 13: first groove; 14: second groove; 15: recessed region; 16: filling groove;

[0083] 20: first dielectric layer; 21: first sub-dielectric layer; 22: second sub-dielectric layer; 23: third sub-dielectric layer; 24: first mask structure;

[0084] 30: shielding structure; 31: first barrier layer; 311: first barrier material layer; 32: first gate dielectric layer; 321: first gate dielectric material layer; 33: shielding grid; 331: gate material layer; 34: first groove;

[0085] 40: first gate structure; 41: second barrier layer; 42: second gate dielectric layer; 43: first gate; 44: second groove;

[0086] 51: first photoresist layer; 511: first opening; 52: second photoresist layer; 53: third photoresist layer; 531: second opening;

[0087] 60: second dielectric layer; 61: second dielectric material layer;

[0088] 70: second mask structure;

[0089] 80: second gate structure; 81: third gate dielectric layer; 82: second gate; 821: second gate material layer;

[0090] 91: first doping region; 92: second doping region; 93: third doping region;

[0091] 100: third mask structure;

[0092] 110: insulation layer;

[0093] 121: first conductive plug; 1211: third barrier layer; 1212: conductive layer; 122: second conductive plug; 123: third conductive plug; 124: fourth conductive plug;

[0094] 131: first etching hole; 132: second etching hole; 133: third etching hole; 134: fourth etching hole; 135: fifth etching hole;

[0095] 140: heavily doped region;

[0096] 150: Interconnect layer. DETAILED DESCRIPTION

[0097] As described in the background technology, the preparation process of the shielded gate trench field effect transistor in the related art is relatively complicated. The inventors have found that the reason for this problem is that when the second dielectric layer is etched back, the first dielectric layer and the second dielectric layer located on the substrate are usually completely etched away. After that, when the second dielectric layer located above the shielding structure is etched again, a mask layer needs to be prepared; and when the first doped region and the second doped region are formed in the substrate, the mask layer also needs to be re-prepared, which increases the steps of preparing and removing the mask layer, making the preparation process of the shielded gate trench field effect transistor relatively complicated, thereby increasing the difficulty of preparation.

[0098] In view of the above technical problems, the embodiments of the present application provide a semiconductor device and a method for manufacturing the same, as well as a power device. When etching back the second dielectric layer, a portion of the first dielectric layer and the second dielectric layer are removed simultaneously, so that the first dielectric layer that is retained and located on the substrate constitutes a first mask structure; the first mask structure can be used as a mask, and then an ion doping process can be used to form a first doped region and a second doped region. In this way, the process of re-preparing the mask layer can be simplified, thereby improving the efficiency of the preparation method and the yield of the semiconductor device, and reducing the manufacturing cost.

[0099] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application.

[0100] Please refer to the attached Figure 1 The present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0101] Step S100: providing a substrate, wherein the substrate includes adjacent cell regions and a peripheral region.

[0102] The substrate 10 is used as a supporting component of the semiconductor device to support other components arranged thereon, wherein the substrate 10 can be made of a semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds. It should be noted that the substrate 10 can be a single-layer structure or a stacked-layer structure. For example, the substrate 10 includes a substrate and an epitaxial layer arranged on the substrate.

[0103] The substrate 10 includes adjacent cell regions 11 and peripheral regions 12. The cell region 11 is the main functional region in the semiconductor device, usually including a plurality of repeated unit structures or cells. The peripheral region 12 is the region around the cell region 11, usually used to support and protect the normal operation of the cell region 11.

[0104] Step S200: forming a first dielectric layer, wherein the first dielectric layer is disposed on a substrate.

[0105] The first dielectric layer 20 may be a single film layer or a stacked layer. Figure 2 The first dielectric layer 20 includes a first sub-dielectric layer 21 , a second sub-dielectric layer 22 and a third sub-dielectric layer 23 which are stacked in sequence. The first sub-dielectric layer 21 is disposed on the substrate 10 .

[0106] It should be noted that each film layer of the first dielectric layer 20 can be prepared by a deposition process or by other methods. Exemplarily, the material of the first sub-dielectric layer 21 includes silicon oxide. The first sub-dielectric layer 21 can be formed on the substrate 10 by a thermal oxidation process, so that the first sub-dielectric layer 21 can be ensured to have a high purity and quality, and the top surface of the first sub-dielectric layer 21 can be as flat as possible, thereby improving the interface flatness of the first sub-dielectric layer 21.

[0107] Afterwards, a second sub-dielectric layer 22 and a third sub-dielectric layer 23 are stacked on the first sub-dielectric layer 21 through a deposition process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In this embodiment, the material of the second sub-dielectric layer 22 includes silicon nitride, and the material of the third sub-dielectric layer 23 includes silicon oxide.

[0108] In this embodiment, the thickness of the first sub-dielectric layer 21 is 30A-500A; the thickness of the second sub-dielectric layer 22 is 100A-150A; and the thickness of the third sub-dielectric layer 23 is 200A-2500A.

[0109] Step S300: forming a shielding structure and a first gate structure; the shielding structure is arranged in the cell region and extends into the substrate, wherein the top surface of the shielding structure and the top surface of the first dielectric layer form a recessed region; the first gate structure is arranged in the peripheral region and extends into the substrate.

[0110] For example, please refer to the attached Figure 3 and attached Figure 4 The first dielectric layer 20 and the substrate 10 are patterned to form a first groove 13 and a second groove 14, which are respectively located in the cell region 11 and the peripheral region 12. It should be noted that the depth of the first groove 13 and the depth of the second groove 14 can be the same or different.

[0111] Please refer to the attached Figure 3 , a first photoresist layer 51 is formed on the first dielectric layer 20, that is, the first photoresist layer 51 can be formed on the surface of the first dielectric layer 20 away from the substrate 10 by coating. Then, the first photoresist layer 51 is patterned to form first openings 511 spaced apart on the first photoresist layer 51. The orthographic projections of some of the first openings 511 on the substrate 10 are located in the cell region 11, and the orthographic projections of some of the first openings 511 on the substrate 10 are located in the peripheral region 12.

[0112] It should be noted that the number of the first openings 511 in the cell region 11 and the number of the first openings 511 in the peripheral region 12 can be selected according to actual conditions, and will not be further elaborated in this embodiment.

[0113] Please refer to the attached Figure 4 The first dielectric layer 20 and a portion of the substrate 10 exposed in the first opening 511 are removed by etching to form a first trench 13 and a second trench 14 in the substrate 10. The depth of the first trench 13 and the second trench 14 is 3.3 um, and the critical dimension CD of the first trench 13 and the second trench 14 is 1.0 um.

[0114] Afterwards, please refer to the attached Figure 5 To Attachment Fig.10 , forming a shielding structure 30 in the first trench 13, and forming a first gate structure 40 in the second trench 14. It should be noted that the shielding structure 30 and the first gate structure 40 can be prepared in the same process, which can simplify the preparation process of the shielding structure 30 and the first gate structure 40.

[0115] Please refer to the attached Fig.10 , wherein the shielding structure 30 comprises a first barrier layer 31, a first gate dielectric layer 32 and a shielding gate 33 which are stacked in sequence, the first barrier layer 31 being arranged on the inner wall of the first trench 13, the first gate dielectric layer 32 being arranged on the first barrier layer 31, and the shielding gate 33 filling the area surrounded by the first gate dielectric layer 32. The shielding structure 30 comprises a first groove 34, and the first groove 34 surrounds at least part of the shielding gate 33; it should be understood that the first groove 34 may surround part of the shielding gate 33, or may surround the entire shielding gate 33.

[0116] The shielding gate 33 is usually grounded or connected to the source potential and is used to shield the second gate 82 (see the attached Fig.18 ) and the drain, thereby reducing the gate charge and gate-drain capacitance. When voltage is applied to the main gate, a channel is formed between the source and the drain, and current can flow through the channel. The presence of the shielded gate can optimize the electric field distribution and reduce the on-resistance and switching loss.

[0117] It should be noted that the second grid is usually arranged above the shield grid 33. Fig.18 ) and the shielding grid 33 usually adopt a second dielectric layer 60 (see the attached Fig.11 ) is insulated. In this embodiment, the shielding structure 30 includes a first groove 34, and the first groove 34 surrounds at least a portion of the shielding grid 33. In this way, the second dielectric layer 60 (please refer to the attached Fig.14) not only covers the top surface of the shielding grid 33, but also wraps the side surface of the shielding grid 33 to increase the contact area between the second dielectric layer 60 and the shielding grid 33. On the one hand, it can improve the interface strength between the second dielectric layer 60 and the shielding grid, and on the other hand, it can also enhance the insulation performance of the shielding grid 33 and the second grid.

[0118] The first gate structure 40 includes a second barrier layer 41, a second gate dielectric layer 42 and a first gate 43 which are stacked in sequence, the second barrier layer 41 is disposed on the inner wall of the second trench 14, the second gate dielectric layer 42 is disposed on the second barrier layer 41, and the first gate 43 fills the area surrounded by the second barrier layer 41. The first gate structure 40 includes a second groove 44 which surrounds a portion of the first gate 43.

[0119] The transistor formed by the first gate structure 40 is used to control edge effects, optimize electric field distribution, thermal management, prevent leakage current, relieve mechanical stress, protect transistors located in the cell area, and improve packaging reliability. In addition, the design of the second groove 44 also helps to disperse stress and reduce the failure of the semiconductor device during use.

[0120] In some possible implementations, the shielding structure 30 and the first gate structure 40 can be formed simultaneously, which can simplify the manufacturing process of the semiconductor device. Figure 5 A first barrier material layer 311 and a first gate dielectric material layer 321 are stacked and formed on the inner walls of the first trench 13 and the second trench 14 , and the first barrier material layer 311 covers the inner walls of the first trench 13 and the second trench 14 .

[0121] Afterwards, please refer to the attached Figure 6 , forming a first gate material layer 331, the first gate material layer 331 fills the area surrounded by the first gate dielectric material layer 321, and covers the top surface of the first dielectric layer 20, that is, the top surface of the first gate material layer 331 is higher than the top surface of the first dielectric layer 20. The material of the first gate material layer 331 includes polysilicon.

[0122] In this embodiment, the materials of the first barrier material layer 311 and the first gate dielectric material layer 321 can be the same, for example, both include silicon oxide, and the difference lies in the formation process. For example, the first barrier material layer 311 can be formed by oxidizing the substrate 10 exposed in the first trench 13 and the second trench 14 at 115°C through a thermal oxidation process. Among them, the thickness of the first barrier material layer 311 is 150A. Afterwards, the first gate dielectric material layer 321 is formed on the first barrier material layer 311 by a deposition process. It should be understood that the first gate dielectric material layer 321 can also cover the top surface of the first dielectric layer 20. Among them, the thickness of the first gate dielectric material layer 321 is 180A. Afterwards, the semiconductor device can also be heat-treated at 1110°C for 30 minutes. In this way, the performance of the first barrier material layer 311 and the first gate dielectric material layer 321 can be improved, and the risk of the first barrier material layer 311 and the first gate dielectric material layer 321 being broken down can be reduced, thereby avoiding the occurrence of gate-induced drain leakage current.

[0123] Please refer to the attached Figure 7 The first gate material layer 331 is planarized by a chemical mechanical polishing (CMP) process so that the top surface of the first gate material layer 331 is flush with the top surface of the first dielectric layer 20 .

[0124] Please refer to the attached Figure 8 , using the first dielectric layer 20 as a mask, continue to etch the first gate material layer 331 so that the top surface of the first gate material layer 331 is lower than the top surface of the first dielectric layer 20 , for example, the top surface of the first gate material layer 331 is flush with the top surface of the first sub-dielectric layer 21 .

[0125] Please refer to the attached Fig. 9 A second photoresist layer 52 is formed on the first dielectric layer 20, the second photoresist layer 52 covers the peripheral area, and the first gate material layer 331 exposed in the cell area 11 is continuously etched using the second photoresist layer 52 as a mask, so that the top surface of the retained first gate material layer 331 is lower than the top surface of the substrate 10. The first gate material layer 331 retained in the cell area 11 constitutes the shielding gate 33, and the first gate material layer 331 retained in the peripheral area 12 constitutes the first gate 43.

[0126] Please refer to the attached Fig.10, remove the second photoresist layer 52, and use the first dielectric layer as a mask to etch the first barrier material layer 311 and the first gate dielectric material layer 321. The first barrier material layer 311 retained in the cell region 11 constitutes the first barrier layer 31, and the first barrier material layer 311 retained in the peripheral region 12 constitutes the second barrier layer 41. The first gate dielectric material layer 321 retained in the cell region 11 constitutes the first gate dielectric layer 32, and the first gate dielectric material layer 321 retained in the peripheral region 12 constitutes the second gate dielectric layer 42.

[0127] In addition, the top surface of the first gate dielectric layer 32 is lower than the shielding gate 33, so that the first barrier layer 31, the first gate dielectric layer 32 and the shielding gate 33 enclose a first groove 34. The top surface of the second gate dielectric layer 42 is lower than the first gate 43, so that the second barrier layer 41, the second gate dielectric layer 42 and the first gate 43 enclose a second groove 44.

[0128] It should be noted that, since the top surface of the shielding structure 30 is lower than the first dielectric layer 20 , the top surface of the shielding structure 30 and the top surface of the first dielectric layer 20 form a recessed area 15 .

[0129] Step S400: forming a second dielectric layer, wherein the second dielectric layer fills the recessed area and covers the first gate structure.

[0130] For example, please refer to the attached Fig.11 A second dielectric material layer 61 is formed by a deposition process, and the second dielectric material layer 61 fills the recessed area 15 and covers the first gate structure 40 and the first dielectric layer 20. The material of the second dielectric material layer 61 may include silicon oxide.

[0131] Please refer to the attached Fig.12 , remove part of the second dielectric material layer 61, so that the top surface of the remaining second dielectric material layer 61 is flush with the top surface of the first dielectric layer 20. In this step, the second dielectric material layer 61 can be polished by a chemical mechanical polishing process to remove part of the second dielectric material layer 61. After removal, the semiconductor device can be heat-treated, for example, the semiconductor device is heat-treated at 950° C. for 60 minutes to improve the performance of the second dielectric material layer 61.

[0132] In this embodiment, the second dielectric layer 60 is flush with the top surface of the first dielectric layer 20, that is, in this step, the first dielectric layer 20 is removed so that a portion of the first dielectric layer 20 can subsequently form the first mask structure 24 (see the attached Fig.16 ).

[0133] Step S500: removing part of the second dielectric layer and part of the first dielectric layer, and the remaining second dielectric layer and the substrate enclose a filling groove; wherein the remaining first dielectric layer on the substrate constitutes a first mask structure, and the first mask structure covers the first gate structure and part of the peripheral area.

[0134] Please refer to the attached Fig.13 , forming a second mask structure 70, the second mask structure 70 covers a portion of the peripheral region 12 and exposes the second dielectric layer 60 and the first dielectric layer 20 located on the cell region 11. The second mask structure 70 may be a photoresist layer or a hard mask layer.

[0135] Please refer to the attached Fig.14 , using the second mask structure 70 as a mask, remove the portion of the second dielectric layer 60 exposed on the cell region, so that the top surface of the remaining second dielectric layer 60 is lower than the top surface of the first dielectric layer 20, and forms a filling groove 16 with the substrate 10. The filling groove 16 is located in the first trench 13.

[0136] It should be noted that in this step, the exposed portion of the first dielectric layer 20 is also removed. For example, this step can remove the third sub-dielectric layer 23. In addition, in this embodiment, the second dielectric layer 60 and a portion of the first dielectric layer 20 are removed by a wet etching process. Therefore, a portion of the first dielectric layer 20 located under the second mask structure 70 is also removed. In other words, this step can remove the structure of which can be referred to in the attached Fig.14 .

[0137] Please refer to the attached Fig.15 , continue to use the second mask structure 70 as a mask to etch the exposed first dielectric layer 20 to expose the top surface of the substrate 10 , and the retained first dielectric layer 20 constitutes the first mask structure 24 .

[0138] Step S600: forming a second gate structure in the filling trench.

[0139] Please refer to the attached Fig.16 , forming a third gate dielectric layer 81, the third gate dielectric layer 81 covers the inner wall of the filling groove 16 and covers the top surface of the substrate 10. It should be noted that the third gate dielectric layer 81 can be formed by a deposition process or an oxidation process, and the material of the third gate dielectric layer 81 includes silicon oxide. Exemplarily, the third gate dielectric layer 81 is formed by an oxidation process, wherein the preparation temperature is 1050°C.

[0140] Please refer to the attached Fig.17 and attached Fig.18 , forming a second gate 82 , the second gate 82 fills the area surrounded by the third gate dielectric layer 81 in the filling groove 16 ; the third gate dielectric layer 81 and the second gate 82 constitute a second gate structure 80 .

[0141] The second gate material layer 821 is formed by a deposition process, and the second gate material layer 821 fills the area enclosed by the third gate dielectric layer 81 in the filling groove 16, and covers the third gate dielectric layer 81 and the first mask structure 24. The material of the second gate material layer 821 includes polysilicon. Then, a chemical mechanical polishing process is used to remove part of the second gate material layer 821, so that the remaining second gate material layer 821 constitutes the second gate 82, and the top surface of the second gate 82 is flush with the top surface of the substrate 10.

[0142] Step S700: Using the first mask structure as a mask, doping the exposed substrate to form a first doping region and a second doping region, wherein the first doping region is located between the first gate structure and the second gate structure, and the second doping region is located on a side of the first gate structure away from the second gate structure.

[0143] Please refer to the attached Fig.19 , doping is performed on the exposed substrate 10 using a plasma doping process to form a first doping region 91 and a second doping region 92. The first doping region 91 and the second doping region 92 have the same conductivity type. In one example, the first doping region 91 and the second doping region 92 have a P-type conductivity. In another example, the first doping region 91 and the second doping region 92 have an N-type conductivity.

[0144] Please refer to the attached Fig. 20 , the above-mentioned device can be heat treated, that is, the first doping region 91 and the second doping region 92 can be heat treated. For example, it can be treated at 1050°C for 60 minutes to increase the thickness of the first doping region 91 and the second doping region 92, which helps to form a deeper doping region, thereby improving the electrical performance of the semiconductor device. In addition, the diffusion of doping ions can be promoted, so that the doping concentration in the doping region is more uniform, which helps to improve the performance stability and consistency of the semiconductor device. Among them, the thickness of the first doping region 91 and the second doping region 92 is 500A.

[0145] In this embodiment, the first dielectric layer 20 that is retained and located on the substrate is used to form a first mask structure 24; the first mask structure 24 is used as a mask, and then an ion doping process is used to form the first doping region 91 and the second doping region 92. In this way, the process of re-preparing the mask layer can be simplified, thereby improving the efficiency of the preparation method and the yield of the semiconductor device, and reducing the manufacturing cost.

[0146] In a possible implementation, after the step of forming the first doping region and the second doping region, the method for preparing a semiconductor device includes:

[0147] Please refer to the attached Fig.21, a third mask structure 100 , the third mask structure 100 covers the second doping region 92 .

[0148] Please refer to the attached Fig. 22 , using the first mask structure 24 and the third mask structure 100 as masks, doping the first doping region 91 to form a third doping region 93 in the first doping region 91; wherein the conductivity type of the first doping region 91 is the same as the conductivity type of the second doping region 92, and different from the conductivity type of the third doping region 93. In one example, when the conductivity type of the first doping region 91 is P-type, the conductivity type of the third doping region 93 is N-type; in another example, when the conductivity type of the first doping region 91 is N-type, the conductivity type of the third doping region 93 is P-type.

[0149] In this embodiment, the ion implantation process has an implantation energy of 60 keV and an implantation dose of 5×1015 ions / cm 2 After the ion implantation is completed, the semiconductor device may be subjected to a heat treatment, for example, at 950° C. for 30 minutes.

[0150] In this embodiment, the third doping region 93 and the first doping region 91 are stacked in a direction perpendicular to the substrate 10 , so that the third doping region 93 constitutes a source region or a drain region of the transistor, and the first doping region 91 constitutes a channel region of the transistor.

[0151] In one possible implementation, please refer to the attached Fig.23 , and remove the third mask structure 100 .

[0152] Afterwards, please refer to the attached Fig.23 , forming an insulating layer 110, the insulating layer 110 covers the third doping region 93, the second gate structure 80, the first mask structure 24 and the second doping region 92; the insulating layer 110 is formed by an atomic layer deposition process. The insulating layer 110 is made of polyethylene oxide (PEOX) and / or bisphenol S (BPS).

[0153] Please refer to the attached Fig.24 To Attachment Fig.30 , a conductive plug is formed in the insulating layer, the conductive plug includes a first conductive plug 121, a second conductive plug 122, and a third conductive plug 123, the first conductive plug 121 is electrically connected to the second gate 82, the second conductive plug 122 is electrically connected to the third doped region 93, and the third conductive plug 123 is electrically connected to the second doped region 92.

[0154] For example, please refer to the attached Fig.24, a third photoresist layer 53 is formed on the insulating layer 110 , and the third photoresist layer 53 is patterned to form a plurality of second openings 531 in the third photoresist layer 53 .

[0155] Please refer to the attached Fig.25 , the insulating layer 110 and the first mask structure 24 exposed in the second opening 531 are removed by etching to form a plurality of etching holes. It should be understood that the number of the plurality of etching holes can be set according to the number of devices in the substrate 10.

[0156] Exemplarily, the plurality of etching holes include a first etching hole 131, a second etching hole 132, a third etching hole 133, a fourth etching hole 134, and a fifth etching hole 135. The first etching hole 131 exposes the top surface of the second gate 82, the second etching hole 132 exposes the top surface of the third doping region 93, the third etching hole 133 exposes the top surface of the first gate 43, the fourth etching hole 134 exposes the top surface of the second sub-dielectric layer in the first mask structure 24, and the fifth etching hole 135 exposes the top surface of the second doping region 92.

[0157] Please refer to the attached Fig.26 , continue along the first etched hole 131, the second etched hole 132, the third etched hole 133 and the fifth etched hole 135, so that the bottom of the first etched hole 131 extends into the second gate 82, the bottom of the second etched hole 132 extends into the first doped region 91, the bottom of the third etched hole 133 extends into the first gate 43, and the bottom of the fifth etched hole 135 extends into the second doped region 92.

[0158] It should be noted that the conductive plug formed later is electrically connected to the corresponding device. In order to reduce the contact resistance between the two, the preparation method provided in this embodiment also includes: forming a heavily doped region 140, which is arranged at the end of the conductive plug facing the substrate 10.

[0159] For example, please refer to the attached Fig. 27 , heavily doped in the area exposed by each etched hole by plasma doping process to form heavily doped area 140. Such arrangement can reduce the contact resistance between the conductive plug and the corresponding device, help improve the current transmission efficiency, reduce power loss. It can also improve the overall performance of the semiconductor device, including switching speed, signal transmission speed and current driving capability.

[0160] Please refer to the attached Fig.28 , continue etching along the fourth etching hole 134 to remove the first mask structure 24 exposed in the fourth etching hole 134 to expose the top surface of the substrate 10.

[0161] Please refer to the attached Fig.29, a conductive plug is formed in each etched hole by a deposition process. The plurality of conductive plugs include a first conductive plug 121, a second conductive plug 122, a third conductive plug 123 and a fourth conductive plug 124, the first conductive plug 121 is electrically connected to the second gate 82, the second conductive plug 122 is electrically connected to the first doping region 91, the third conductive plug 123 is electrically connected to the first gate 43, and the fourth conductive plug 124 is electrically connected to the second doping region 92.

[0162] The conductive plug may include a third barrier layer 1211 and a conductive layer 1212, wherein the third barrier layer 1211 is disposed on the inner wall of the etched hole and covers the insulating layer 110; and the conductive layer 1212 fills the area surrounded by the third barrier layer 1211. The material of the third barrier layer 1211 includes titanium nitride, and the material of the conductive layer 1212 includes tungsten.

[0163] It should be noted that after the conductive plug is formed, an interconnection layer needs to be formed, and the interconnection layer includes a plurality of interconnection blocks that are insulated from each other, and each interconnection block is used to be electrically connected to the corresponding conductive plug to facilitate connection with the peripheral circuit. In addition, the drain of the transistor and the other electrode of the diode are usually formed on the back of the substrate 10, which belongs to the related art and will not be described in detail in this embodiment.

[0164] The present application also provides a semiconductor device, including:

[0165] The substrate 10 includes an adjacent cell region 11 and a peripheral region.

[0166] The shielding structure 30 is disposed in the cell region 11 and extends into the substrate 10 , wherein the top surface of the shielding structure 30 and the top surface of the first dielectric layer 20 form a recessed region 15 .

[0167] The first gate structure 40 is disposed in the peripheral region 12 and extends into the substrate 10 .

[0168] The second dielectric layer 60 is disposed on the shielding structure 30 and forms a filling groove 16 with the substrate 10 .

[0169] The second gate structure 80 is disposed in the filling trench 16 .

[0170] A first doping region 91 and a second doping region 92 , wherein the first doping region 91 is located between the first gate structure 40 and the second gate structure 80 , and the second doping region 92 is located on a side of the first gate structure away from the second gate structure.

[0171] The first mask structure 24 is disposed on the substrate 10 and covers the first gate structure 40 and a region between the first gate structure 40 and the second doping region 92 .

[0172] In some possible embodiments, the second dielectric layer 60 includes a portion of the outer peripheral surface that wraps the shielding structure 30 and covers the top surface of the shielding structure 30. This configuration is used to increase the contact area between the second dielectric layer 60 and the shielding grid 33, which can improve the interface strength between the second dielectric layer 60 and the shielding grid on the one hand, and enhance the insulation performance between the shielding grid 33 and the second grid on the other hand.

[0173] In some possible embodiments, the semiconductor device further includes a third doping region 93, which is disposed on the first doping region 91, and the conductivity type of the third doping region 93 is different from the conductivity type of the first doping region 91. It should be noted that a fourth doping region (not shown in the figure) is further disposed on the side of the first doping region 91 away from the third doping region 93, and the fourth doping region has the same conductivity type as the third doping region 93, so that the third doping region 93, the first doping region 91 and the fourth doping region form a PNP structure or an NPN structure.

[0174] The embodiment of the present application also provides a power device, including the semiconductor device described in any of the above embodiments. The power device formed by this embodiment is not limited to a shielded gate field-effect transistor (SGFET).

[0175] It should be noted that the beneficial effects of the power device provided in the embodiment of the present application are the same as the beneficial effects of the semiconductor device provided in the above embodiment, and this embodiment will not be described in detail. The power device provided in the embodiment of the present application can be applied to discrete devices, ACDC converters or temperature sensors.

[0176] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0177] It should be noted that the phrases "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. mentioned in the specification indicate that the described embodiments may include certain features, structures or characteristics, but not every embodiment may include the certain features, structures or characteristics. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when describing certain features, structures or characteristics in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such features, structures or characteristics in conjunction with other embodiments, whether explicitly or not explicitly described.

[0178] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include; Providing a substrate, the substrate comprising a cell region and a peripheral region adjacent to each other; forming a first dielectric layer, wherein the first dielectric layer is disposed on the substrate; A shielding structure and a first gate structure are formed; the shielding structure is arranged in the cell region and extends into the substrate, wherein a top surface of the shielding structure and a top surface of the first dielectric layer form a recessed region; the first gate structure is arranged in the peripheral region and extends into the substrate; forming a second dielectric layer, wherein the second dielectric layer completely fills the recessed area and covers the first gate structure; removing part of the second dielectric layer and part of the first dielectric layer, and the remaining second dielectric layer and the substrate enclose a filling groove; wherein the remaining first dielectric layer located on the substrate constitutes a first mask structure, and the first mask structure covers the first gate structure and part of the peripheral area; forming a second gate structure in the filling groove; Using the first mask structure as a mask, the exposed substrate is doped to form a first doping region and a second doping region, wherein the first doping region is located between the first gate structure and the second gate structure, and the second doping region is located on a side of the first gate structure away from the second gate structure.

2. The method for preparing a semiconductor device according to claim 1, wherein: The top surface of the second dielectric layer is flush with the top surface of the first dielectric layer.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of forming the shielding structure and the first gate structure comprises: Patterning the first dielectric layer and the substrate to form a first groove and a second groove, wherein the first groove and the second groove are respectively located in the cell region and the peripheral region; A shielding structure is formed in the first trench and a first gate structure is formed in the second trench.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The shielding structure comprises a first barrier layer, a first gate dielectric layer and a shielding gate which are stacked in sequence, wherein the first barrier layer is arranged on the inner wall of the first groove; wherein the shielding structure comprises a first groove, wherein the first groove surrounds at least a portion of the shielding gate; The first gate structure includes a second barrier layer, a second gate dielectric layer and a first gate which are stacked in sequence, and the second barrier layer is arranged on the inner wall of the second trench; wherein the first gate structure includes a second groove, and the second groove surrounds a portion of the first gate.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The step of removing part of the second dielectric layer and part of the first dielectric layer comprises: forming a second mask structure, wherein the mask structure covers a portion of the peripheral region and exposes the second dielectric layer and the first dielectric layer located on the cell region; Using the second mask structure as a mask, a portion of the second dielectric layer exposed on the cell region is removed, so that the top surface of the remaining second dielectric layer is lower than the top surface of the first dielectric layer and encloses the filling groove with the substrate; and the exposed first dielectric layer is removed, and the remaining first dielectric layer constitutes a first mask structure.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The step of forming a second gate structure in the filling groove comprises: forming a second gate dielectric layer, wherein the second gate dielectric layer covers the inner wall of the filling groove and covers the top surface of the substrate; A second gate is formed, and the second gate completely fills the area enclosed by the second gate dielectric layer in the filling groove; the second gate dielectric layer and the second gate constitute a second gate structure.

7. The method for preparing a semiconductor device according to any one of claims 1 to 6, characterized in that: After the step of forming the first doping region and the second doping region, the method includes: The first doping region and the second doping region are thermally treated.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: After the step of forming the first doping region and the second doping region, the method includes: forming a third mask structure, wherein the third mask structure covers the second doping region; The first doping region is doped using the first mask structure and the third mask structure as masks to form a third doping region in the first doping region; wherein the conductivity type of the first doping region is the same as the conductivity type of the second doping region and different from the conductivity type of the third doping region.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: After the step of forming the third doping region, the method further includes: removing the third mask structure; forming an insulating layer, wherein the insulating layer covers the third doping region, the second gate structure, the first mask structure and the second doping region; Conductive plugs are formed in the insulating layer, the conductive plugs including a first conductive plug, a second conductive plug, a third conductive plug and a fourth conductive plug, the first conductive plug is electrically connected to the second gate, the second conductive plug is electrically connected to the first doped region, the third conductive plug is electrically connected to the first gate, and the fourth conductive plug is electrically connected to the second doped region.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: Before the step of forming the conductive plug, the method further includes: A heavily doped region is formed, wherein the heavily doped region is disposed at an end of the conductive plug facing the substrate.

11. A semiconductor device, characterized in that: include: A substrate, the substrate comprising adjacent cellular regions and peripheral regions; A shielding structure, the shielding structure is arranged in the cell region and extends into the substrate; a first gate structure, the first gate structure being disposed in the peripheral region and extending into the substrate; a second dielectric layer, the second dielectric layer being disposed on the shielding structure and forming a filling groove with the substrate; a second gate structure, the second gate structure being disposed in the filling groove; a first doping region and a second doping region, the first doping region being located between the first gate structure and the second gate structure, and the second doping region being located on a side of the first gate structure away from the second gate structure; A first mask structure is disposed on the substrate and covers the first gate structure and a region between the first gate structure and the second doping region.

12. The semiconductor device according to claim 11, characterized in that The second dielectric layer wraps a portion of the outer circumference of the shielding structure and covers the top surface of the shielding structure.

13. The semiconductor device according to claim 12, characterized in that The method further includes a third doping region, wherein the third doping region is disposed on the first doping region, and a conductivity type of the third doping region is different from a conductivity type of the first doping region.

14. A power device, characterized in that: Comprising the semiconductor device according to any one of claims 11 to 13.

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