Delay control circuit, method, device, equipment, storage medium and program product

Abstract

The invention provides a delay control circuit, method, device and equipment, a storage medium and a program product, which are applied to the technical field of signal processing. The circuit comprises a first frequency divider, a second frequency divider, a third frequency divider, a first phase-locked loop and a phase discriminator, the first frequency divider is used for converting an input signal into a low-frequency signal; the first phase-locked loop is used for locking the frequency of the low-frequency signal in a first frequency interval and transmitting the low-frequency signal to the second frequency divider and the third frequency divider in two paths; the second frequency divider is used for performing reset adjustment on the phase of the frequency division signal of the second frequency divider by taking the phase of the frequency division signal of the third frequency divider as a reference; and the phase discriminator is used for detecting the phase difference between the frequency division signal of the second frequency divider and the frequency division signal of the third frequency divider.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a delay control circuit, method, device, equipment, storage medium and program product. Background Art

[0002] In the prior art, signal delay processing can usually be achieved through delay lines. According to the frequency, delay lines can be divided into high-frequency delay lines and low-frequency delay lines. High-frequency delay lines are controlled by analog voltage, with high delay resolution but small delay range; low-frequency delay lines are controlled by digital-analog hybrid, with a large delay range. Digital control achieves large-step delay, while analog control achieves small-step delay. However, both high-frequency and low-frequency delay lines have poor temperature stability and linearity. Summary of the invention

[0003] The present invention provides a delay control circuit, method, device, equipment, storage medium and program product, which are used to solve the problem of poor temperature stability and linearity of the delay line in the prior art.

[0004] The present invention provides a delay control circuit, comprising: a first frequency divider, a second frequency divider, a third frequency divider, a first phase-locked loop and a phase detector; the first frequency divider is connected to the first phase-locked loop, the first phase-locked loop is respectively connected to the second frequency divider and the third frequency divider, the second frequency divider and the third frequency divider are respectively connected to the phase detector; the first frequency divider is used to convert an input signal into a low-frequency signal; the first phase-locked loop is used to lock the frequency of the low-frequency signal in a first frequency range, and transmit the low-frequency signal to the second frequency divider and the third frequency divider in two paths; the second frequency divider is used to reset and adjust the phase of the frequency division signal of the second frequency divider based on the phase of the frequency division signal of the third frequency divider; the phase detector is used to detect the phase difference between the frequency division signal of the second frequency divider and the frequency division signal of the third frequency divider.

[0005] According to a delay control circuit provided by the present invention, the second frequency divider is specifically used to repeatedly reset and adjust the phase of the frequency divided signal of the second frequency divider when the phase difference between the two frequency divided signals detected by the phase detector is not zero.

[0006] According to a delay control circuit provided by the present invention, the third frequency divider is a frequency divider with a fixed frequency division ratio, and the second frequency divider is a frequency divider with a reset function.

[0007] According to a delay control circuit provided by the present invention, the delay time length of the frequency-divided signal is the product of the output period of the first phase-locked loop and the fixed frequency-dividing ratio.

[0008] A delay control circuit provided according to the present invention further includes a second phase-locked loop, wherein the second phase-locked loop is used to convert the output signal of the phase detector into a high-frequency signal.

[0009] The present invention provides a delay control method, comprising: detecting the phase difference between a frequency division signal of a second frequency divider and a frequency division signal of a third frequency divider; and resetting and adjusting the phase of the frequency division signal of the second frequency divider when the phase difference is not zero.

[0010] The present invention also provides a delay control device, comprising the following modules: a detection module and a processing module; the detection module is used to detect the phase difference between the frequency division signal of the second frequency divider and the frequency division signal of the third frequency divider; the processing module is used to reset and adjust the phase of the frequency division signal of the second frequency divider when the phase difference is not zero.

[0011] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any of the delay control methods described above is implemented.

[0012] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the delay control method described in any one of the above is implemented.

[0013] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the delay control method described above is implemented.

[0014] The delay control circuit, method, device, equipment, storage medium and program product provided by the present invention may include: a first frequency divider, a second frequency divider, a third frequency divider, a first phase-locked loop and a phase detector; the first frequency divider is connected to the first phase-locked loop, the first phase-locked loop is respectively connected to the second frequency divider and the third frequency divider, and the second frequency divider and the third frequency divider are respectively connected to the phase detector; the first frequency divider is used to convert the input signal into a low-frequency signal; the first phase-locked loop is used to lock the frequency of the low-frequency signal in a first frequency range, and transmit the low-frequency signal to the second frequency divider and the third frequency divider in two paths; the second frequency divider is used to reset and adjust the phase of the frequency divided signal of the second frequency divider based on the phase of the frequency divided signal of the third frequency divider; the phase detector is used to detect the phase difference between the frequency divided signal of the second frequency divider and the frequency divided signal of the third frequency divider. Through this solution, on the one hand, since the second frequency divider can reset and adjust the phase of the frequency division signal of the second frequency divider based on the phase of the frequency division signal of the third frequency divider, it is possible to adjust and control the phase difference between the frequency division signals, thereby realizing linear control of the signal delay; on the other hand, since the frequency divider is a digital control device, it has better temperature stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 It is a structural schematic diagram of the delay control circuit provided by the present invention; Figure 2 It is a signal schematic diagram of the delay control circuit provided by the present invention; Figure 3 It is a flow chart of the delay control method provided by the present invention; Figure 4 It is a structural schematic diagram of the delay control device provided by the present invention; Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] It should be noted that, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0019] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0020] In order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and order of execution.

[0021] The embodiments of the present application describe some exemplary embodiments for the purpose of explanation. It should be understood that the present application can be implemented in other ways that are not specifically shown in the drawings.

[0022] like Figure 1As shown, an embodiment of the present application provides a delay control circuit, which includes: a first frequency divider 101, a second frequency divider 102, a third frequency divider 103, a first phase-locked loop 104 and a phase detector 105; the first frequency divider 101 is connected to the first phase-locked loop 104, the first phase-locked loop 104 is respectively connected to the second frequency divider 102 and the third frequency divider 103, and the second frequency divider 102 and the third frequency divider 103 are respectively connected to the phase detector 105.

[0023] The first frequency divider 101 is used to convert an input signal into a low-frequency signal.

[0024] The first phase-locked loop 104 is used to lock the frequency of the low-frequency signal within a first frequency range, and transmit the low-frequency signal to the second frequency divider and the third frequency divider in two paths.

[0025] The second frequency divider 102 is used to reset and adjust the phase of the frequency divided signal of the second frequency divider based on the phase of the frequency divided signal of the third frequency divider 103.

[0026] The phase detector 105 is used to detect the phase difference between the frequency divided signal of the second frequency divider and the frequency divided signal of the third frequency divider.

[0027] Optionally, the second frequency divider 102 is specifically configured to repeatedly reset and adjust the phase of the frequency divided signal of the second frequency divider 102 when the phase difference between the two frequency divided signals detected by the phase detector 105 is not zero.

[0028] Optionally, the third frequency divider 103 is a frequency divider with a fixed frequency division ratio, and the second frequency divider 102 is a frequency divider with a reset function.

[0029] Specifically, continue to refer to Figure 1 , the input signal can be converted into a low-frequency signal S after passing through the first frequency divider 101, and the low-frequency signal S can be provided to the first phase-locked loop 104 as a reference clock, and the first phase-locked loop 104 locks the frequency to a preset frequency range. The output of the first phase-locked loop 104 is divided into two paths, one of which is provided to the third frequency divider 103 with a fixed frequency division ratio to be divided into a low frequency as a reference signal, and the other is provided to the second frequency divider 102 with a reset function. The frequency division ratio of the second frequency divider 102 is kept consistent with the frequency division ratio of the reference signal channel. Afterwards, the phase difference between the two frequency division signals can be detected by the phase detector 105. When the phase difference between the two frequency division signals detected by the phase detector 105 is not zero, the phase ambiguity characteristic of the second frequency divider 102 is used to repeatedly reset and adjust the phase of the frequency division signal of the second frequency divider 102 until the desired phase position is met.

[0030] It should be noted that since the frequency divider is a digital device, there is no phase error. Therefore, when the frequency division ratio of the second frequency divider 102 is consistent with the frequency division ratio of the third frequency divider 103, the frequencies of the two frequency division signals are the same, but the phases of the two frequency division signals may be different. In order to achieve signal delay control, the frequency division signal of the third frequency divider 103 can be used as a reference to adjust the phase difference by continuously resetting the second frequency divider 102.

[0031] For example, Figure 2 As shown, taking the frequency of the low-frequency signal S as 16 GHz and the fixed frequency division ratio N=2 as an example, at most two frequency division signals can be obtained through the processing of the first phase-locked loop 104, namely, the frequency division signal P1 obtained by processing the third frequency divider 103 and the frequency division signal P2 obtained by processing the second frequency divider 102, wherein the starting position of the frequency division signal P1 is the first signal rising edge of the low-frequency signal S, the starting position of the frequency division signal P2 is the second signal rising edge of the low-frequency signal S, and the phase difference between the two frequency division signals is one cycle of the low-frequency signal S. By resetting and adjusting the phase of the frequency division signal of the second frequency divider 102, the phases of the two frequency division signals can be kept consistent.

[0032] Optionally, the delay time length of the frequency-divided signal is the product of an output period of the first phase-locked loop and the fixed frequency-dividing ratio.

[0033] It should be noted that, when the output period of the first phase-locked loop is determined, the delay time length of the signal can be extended by increasing the frequency division ratio through cascading frequency dividers, thereby achieving the purpose of controlling the signal delay.

[0034] Alternatively, if Figure 1 As shown, the delay control circuit provided in the embodiment of the present application further includes a second phase-locked loop 106, and the second phase-locked loop 106 is used to convert the output signal of the phase detector into a high-frequency signal.

[0035] In the embodiment of the present application, on the one hand, since the second frequency divider can reset and adjust the phase of the frequency division signal of the second frequency divider based on the phase of the frequency division signal of the third frequency divider, it is possible to adjust and control the phase difference between the frequency division signals, thereby realizing linear control of the signal delay; on the other hand, since the frequency divider is a digital control device, it has better temperature stability.

[0036] like Figure 3 As shown, an embodiment of the present application provides a delay control method, which can be applied to a delay control device, and the delay control device includes the above-mentioned delay control circuit. The delay control method may include S301-S302: S301. A delay control device detects a phase difference between a frequency-divided signal of a second frequency divider and a frequency-divided signal of a third frequency divider.

[0037] S302: When the phase difference is not zero, the delay control device resets and adjusts the phase of the frequency division signal of the second frequency divider.

[0038] In the embodiment of the present application, since the phase of the divided signal of the third divider can be used as a reference to reset and adjust the phase of the divided signal of the second divider, the phase difference between the divided signals can be adjusted and controlled, thereby achieving control of signal delay.

[0039] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. In order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiment disclosed herein, the embodiment of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0040] The delay control method provided in the embodiment of the present application can be executed by a delay control device or a control module for delay control in the delay control device. In the embodiment of the present application, the delay control device provided in the embodiment of the present application is described by taking the delay control method executed by the delay control device as an example.

[0041] It should be noted that the embodiment of the present application can divide the functional modules of the delay control device according to the above method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. Optionally, the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0042] like Figure 4 As shown, an embodiment of the present application provides a delay control device 400. The delay control device 400 includes: a detection module 401 and a processing module 402. The detection module 401 is used to detect the phase difference between the frequency division signal of the second frequency divider and the frequency division signal of the third frequency divider; the processing module 402 is used to reset and adjust the phase of the frequency division signal of the second frequency divider when the phase difference is not zero.

[0043] In the embodiment of the present application, since the phase of the divided signal of the third divider can be used as a reference to reset and adjust the phase of the divided signal of the second divider, the phase difference between the divided signals can be adjusted and controlled, thereby achieving control of signal delay.

[0044] Figure 5 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 5 As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the delay control method, which includes: detecting the phase difference between the frequency division signal of the second frequency divider and the frequency division signal of the third frequency divider; and resetting and adjusting the phase of the frequency division signal of the second frequency divider when the phase difference is not zero.

[0045] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0046] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the delay control method provided by the above-mentioned methods, which includes: detecting the phase difference between the divided signal of the second frequency divider and the divided signal of the third frequency divider; when the phase difference is not zero, resetting and adjusting the phase of the divided signal of the second frequency divider.

[0047] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the delay control method provided by the above-mentioned methods. The method includes: detecting the phase difference between the divided signal of the second frequency divider and the divided signal of the third frequency divider; when the phase difference is not zero, resetting and adjusting the phase of the divided signal of the second frequency divider.

[0048] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0049] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A delay control circuit, characterized in that: include: A first frequency divider, a second frequency divider, a third frequency divider, a first phase-locked loop, and a phase detector; The first frequency divider is connected to the first phase-locked loop, the first phase-locked loop is respectively connected to the second frequency divider and the third frequency divider, and the second frequency divider and the third frequency divider are respectively connected to the phase detector; The first frequency divider is used to convert the input signal into a low-frequency signal; The first phase-locked loop is used to lock the frequency of the low-frequency signal within a first frequency range, and transmit the low-frequency signal to the second frequency divider and the third frequency divider in two paths; The second frequency divider is used to reset and adjust the phase of the frequency divided signal of the second frequency divider based on the phase of the frequency divided signal of the third frequency divider; The phase detector is used to detect the phase difference between the frequency divided signal of the second frequency divider and the frequency divided signal of the third frequency divider.

2. The delay control circuit according to claim 1, characterized in that: The second frequency divider is specifically used to repeatedly reset and adjust the phase of the frequency divided signal of the second frequency divider when the phase difference between the two frequency divided signals detected by the phase detector is not zero.

3. The delay control circuit according to claim 2, characterized in that: The third frequency divider is a frequency divider with a fixed frequency dividing ratio, and the second frequency divider is a frequency divider with a reset function.

4. The delay control circuit according to claim 1, characterized in that: The delay time length of the frequency-divided signal is the product of the output period of the first phase-locked loop and the fixed frequency-dividing ratio.

5. The delay control circuit according to any one of claims 1 to 4, characterized in that: It also includes a second phase-locked loop, which is used to convert the output signal of the phase detector into a high-frequency signal.

6. A delay control method, applied to the delay control circuit, characterized in that: include: detecting a phase difference between a frequency-divided signal of the second frequency divider and a frequency-divided signal of the third frequency divider; When the phase difference is not zero, the phase of the frequency division signal of the second frequency divider is reset and adjusted.

7. A delay control device, characterized in that: include: Detection module and processing module; The detection module is used to detect the phase difference between the frequency division signal of the second frequency divider and the frequency division signal of the third frequency divider; The processing module is used to reset and adjust the phase of the frequency division signal of the second frequency divider when the phase difference is not zero.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the delay control method as claimed in claim 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the delay control method as claimed in claim 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the delay control method as claimed in claim 6 is implemented.

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