Electronic component and fault management method thereof

Abstract

The invention relates to the technical field of electronic components, in particular to an electronic component and a fault management method thereof. The method comprises the following steps that circuit board design data are analyzed through a system, and the reliability and performance of electronic components are improved; the method comprises the steps of obtaining circuit board design data, performing circuit wiring analysis, generating wiring data and cross wiring data, then detecting electromagnetic radiation enhancement conditions, calculating a circuit fault probability, and further detecting a short-circuit fault of an electronic component; performing comprehensive analysis on the short-circuit fault data and the fault probability, and estimating the aging trend of the component; circuit board design is optimized according to the aging trend and fault probability data, and availability performance improvement of the electronic components is calculated; according to the invention, the design of the electronic component and the circuit board is optimized, so that the fault identification of the electronic component is more accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic components, and in particular to an electronic component and a fault management method thereof. Background Art

[0002] Electronic components can be divided into two categories: active components and passive components. Each component has its own specific working principle and application scenario, and the types of failures are also different. The fault management methods for components mainly include preventive maintenance, monitoring and diagnosis, fault analysis and repair. Monitoring and diagnosis use various sensors and detection equipment to monitor the working status of components in real time and identify potential faults through data analysis. Fault analysis involves in-depth research on the cause of the fault, usually using methods such as failure mode and effect analysis to find out the root cause of the fault and take corresponding measures to improve it. Fault management methods are also gradually developing in the direction of intelligence and automation. Through machine learning and artificial intelligence algorithms, the system can automatically identify fault modes and predict the probability of fault occurrence, thereby achieving more efficient fault management. However, traditional electronic component fault management methods have the problem of inaccurate analysis of fault causes and inaccurate prediction of aging and attenuation of electronic components. Summary of the invention

[0003] Based on this, it is necessary to provide a fault management method for electronic components to solve at least one of the above technical problems.

[0004] To achieve the above object, a fault management method for electronic components includes the following steps:

[0005] Step S1: Acquire circuit board design data; perform circuit wiring analysis according to the circuit board design data to obtain circuit wiring data; perform cross wiring statistics on the circuit wiring data to obtain circuit board cross wiring data;

[0006] Step S2: Perform electromagnetic radiation enhancement detection according to the cross wiring data of the circuit board to obtain cross wiring electromagnetic radiation enhancement data; perform circuit fault probability calculation according to the circuit board cross wiring data and the cross wiring electromagnetic radiation enhancement data to obtain circuit fault probability data; perform electronic component short circuit fault detection according to the circuit fault probability data to obtain electronic component short circuit fault data;

[0007] Step S3: Calculate the electronic component failure probability based on the electronic component short circuit failure data and the circuit failure probability data to obtain the electronic component failure probability data; and estimate the electronic component aging trend based on the electronic component failure probability data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data;

[0008] Step S4: optimizing the circuit board design data according to the electronic component aging trend data and the electronic component failure probability data to obtain circuit board design optimization data; performing electronic component available performance enhancement calculation according to the circuit board design optimization data to obtain electronic component available performance enhancement data.

[0009] The present invention can significantly improve the fault management and analysis effect of electronic components through the implementation of this series of steps. First, obtaining circuit board design data and performing wiring analysis can help to deeply understand the structure and function of the circuit, identify potential design defects, ensure reasonable wiring, and thus reduce the risk of signal interference. Cross wiring statistics not only provide an intuitive assessment of wiring complexity, but also lay the foundation for subsequent electromagnetic radiation detection. Secondly, by performing electromagnetic radiation enhancement detection through cross wiring data, the radiation level and its impact on circuit performance can be quantified. This process helps to identify the hidden faults caused by electromagnetic radiation as early as possible, and combined with the calculation of fault probability, it can accurately predict the fault risks of each component in the circuit, thereby reducing the probability of short circuit faults and enhancing the stability and reliability of the system. Further analysis of short circuit fault data and fault probability data can more carefully evaluate the fault trend of each component. Combined with electromagnetic radiation data, this analysis provides a scientific basis for the prediction of the aging trend of electronic components, so that in the life cycle of the equipment, it can effectively monitor and respond to the performance degradation caused by component aging, and improve the overall reliability of the equipment. Finally, through the comprehensive analysis of aging trend and fault probability data, the circuit board design can be optimized to ensure that the circuit is more reliable and efficient in practical applications. This optimization can not only significantly improve the usability of components, but also reduce downtime and maintenance costs caused by failures, thereby improving the overall performance and market competitiveness of electronic equipment. Therefore, the present invention is an optimization of a traditional electronic component failure management method, which solves the problem of inaccurate analysis of failure causes and inaccurate prediction of aging and attenuation of electronic components in the traditional electronic component failure management method, and improves the accuracy of failure cause analysis and aging and attenuation prediction.

[0010] Preferably, step S1 comprises the following steps:

[0011] Step S11: obtaining circuit board design data;

[0012] Step S12: collecting distribution information of electronic components according to the circuit board design data to obtain distribution information of electronic components;

[0013] Step S13: performing circuit wiring analysis according to the electronic component distribution data and the circuit board design data to obtain circuit wiring data;

[0014] Step S14: Perform cross-wiring statistics on the circuit wiring data and the electronic component distribution data to obtain circuit board cross-wiring data.

[0015] The present invention can effectively improve the fault management and analysis capabilities of electronic components through the implementation of this series of steps. First, obtaining circuit board design data lays the foundation for subsequent analysis, ensuring that the entire fault management process has a basis to rely on. The collection of electronic component distribution enables the design team to clearly understand the layout of components on the circuit board, identify existing design defects and improper layout, and thus provide an important basis for subsequent analysis. On this basis, combining the electronic component distribution data with the circuit board design data for circuit wiring analysis can reveal the complexity and effectiveness of circuit connections. This analysis not only helps to evaluate the rationality of wiring, but also can discover potential interference sources and circuit instability factors in advance, thereby providing important information for subsequent fault prediction and risk assessment. Finally, the cross wiring statistics of circuit wiring data and electronic component distribution data can clarify the number of cross wiring and its impact. This statistical result provides a direct basis for identifying electromagnetic interference risks, and helps to take measures to reduce potential fault hazards in the design stage, thereby improving the overall reliability and stability of the circuit board. Through the organic combination of these steps, a set of systematic fault management and analysis frameworks can be formed to ensure the reliable operation of electronic components in practical applications.

[0016] Preferably, step S2 comprises the following steps:

[0017] Step S21: performing electromagnetic radiation enhancement detection according to the cross wiring data of the circuit board to obtain cross wiring electromagnetic radiation enhancement data;

[0018] Step S22: performing circuit board design abnormality analysis according to the circuit board cross wiring data and the cross wiring electromagnetic radiation enhancement data to obtain circuit board design abnormality data;

[0019] Step S23: Calculate the circuit failure probability according to the circuit board design abnormality data and the cross wiring electromagnetic radiation enhancement data to obtain circuit failure probability data;

[0020] Step S24: performing electronic component short circuit fault detection according to the circuit fault probability data and the circuit board design abnormality data to obtain electronic component short circuit fault data.

[0021] The present invention can significantly enhance the fault management and analysis capabilities of electronic components through the implementation of this series of steps. First, electromagnetic radiation enhancement detection is performed based on the cross wiring data of the circuit board, so that the design team can quantify the impact of electromagnetic radiation on circuit performance and identify potential radiation problems, which lays the foundation for subsequent fault analysis. Next, circuit board design abnormality analysis is performed based on cross wiring data and electromagnetic radiation enhancement data, which can effectively identify potential defects and unreasonableness in the design and ensure the stability and reliability of the circuit. Subsequently, the circuit failure probability is calculated by combining the circuit board design abnormality data with the electromagnetic radiation enhancement data, so that the fault prediction is more accurate. By quantifying the failure probability, high-risk components can be identified in the design stage, which helps to formulate corresponding maintenance and monitoring strategies in advance, thereby reducing the failure rate in actual operation. Finally, electronic component short-circuit fault detection is performed based on circuit failure probability data and design abnormality data, which can timely discover and locate short-circuit faults and provide necessary information for subsequent maintenance and adjustment. This detection process not only improves the speed of fault response, but also improves the overall reliability of the equipment, and reduces the downtime and maintenance costs caused by faults. Through the comprehensive application of these steps, a complete and efficient electronic component fault management and analysis system can be established to ensure the stability and safety of electronic equipment in actual operation.

[0022] Preferably, step S21 includes the following steps:

[0023] Step S211: Calculate the circuit board loop area growth using the circuit board cross wiring data to obtain circuit board loop area growth data;

[0024] Step S212: Calculating the circuit board route spacing according to the circuit board loop area growth data and the circuit board cross wiring data to obtain the circuit board route spacing data;

[0025] Step S213: performing signal line crossing acquisition according to the circuit board cross wiring data to obtain circuit board signal line crossing data;

[0026] Step S214: performing electromagnetic coupling effect enhancement calculation according to the circuit board signal line crossing data and the circuit board route spacing data to obtain circuit board electromagnetic coupling effect enhancement data;

[0027] Step S215: Perform electromagnetic radiation enhancement detection according to the circuit board electromagnetic coupling effect enhancement data and the circuit board loop area growth data to obtain cross wiring electromagnetic radiation enhancement data.

[0028] The present invention can further enhance the fault management and analysis capability of electronic components through the implementation of this series of steps. First, the circuit board loop area growth calculation is performed using the circuit board cross wiring data, which can reveal the influence of wiring design on the loop area and provide an important basis for subsequent analysis. Understanding the change in loop area helps to identify potential signal interference sources and current paths, thereby laying a foundation for the stability of the circuit. Next, the circuit board route spacing is calculated based on the loop area growth data and the cross wiring data, which can ensure that a reasonable spacing is maintained between signal lines and reduce the risk of electromagnetic interference. This calculation provides guidance for optimizing circuit design, allowing the design team to consider electromagnetic compatibility in the layout stage, thereby reducing the probability of failure. Further signal line cross acquisition through cross wiring data helps to identify the cross situation between signal lines and clarify the potential source of signal interference. This process provides data support for subsequent electromagnetic coupling effect calculations, ensuring that the degree of interference between signal lines can be accurately evaluated. On this basis, the electromagnetic coupling effect enhancement calculation is performed based on the signal line cross data and the route spacing data, which can quantify the influence of electromagnetic coupling on circuit performance. This evaluation helps the design team identify signal paths that need to be optimized, reduce signal distortion caused by coupling effects, and thus improve the overall reliability of the circuit. Finally, electromagnetic radiation enhancement detection is performed based on the electromagnetic coupling effect enhancement data and loop area growth data, which can comprehensively evaluate the radiation performance of the circuit board and promptly identify high radiation areas and potential design defects. The comprehensive application of these steps can not only improve the accuracy of fault management analysis, but also effectively reduce the failure risk of electronic components in actual operation, ensuring the stability and safety of electronic equipment in complex environments.

[0029] Preferably, step S23 includes the following steps:

[0030] Step S231: Calculate the signal phase offset according to the cross wiring electromagnetic radiation enhancement data to obtain circuit board signal phase offset data;

[0031] Step S232: performing circuit board synchronization failure detection according to the circuit board signal phase offset data to obtain circuit board synchronization failure data;

[0032] Step S233: Calculate the circuit board bit error rate growth by using the circuit board synchronization failure data and the circuit board signal phase offset data to obtain the circuit board bit error rate growth data;

[0033] Step S234: performing power rail abnormality detection according to the circuit board design abnormality data to obtain the circuit board power rail abnormality data;

[0034] Step S235: Calculating circuit board voltage fluctuation according to circuit board power rail abnormality data to obtain circuit board voltage fluctuation data;

[0035] Step S236: Calculate the circuit failure probability based on the circuit board voltage fluctuation data and the circuit board bit error rate growth data to obtain circuit failure probability data.

[0036] The present invention can further enhance the fault management and analysis capabilities of electronic components through the implementation of this series of steps. First, the signal phase offset calculation is performed based on the cross wiring electromagnetic radiation enhancement data, which helps to identify the phase difference that occurs during the signal transmission process. This calculation provides a basis for subsequent synchronization failure detection, ensuring that the design team can promptly discover potential problems caused by phase offset. Next, the circuit board synchronization failure detection is performed based on the signal phase offset data, which can clarify the reliability of the circuit in terms of synchronization and provide guarantee for the stable operation of the system. This detection can pre-identify the risk of causing data transmission errors, thereby providing support for fault prevention. Subsequently, the bit error rate growth calculation is performed using the synchronization failure data and the signal phase offset data, which can quantify the impact of synchronization failure on system performance. This data analysis provides a basis for system optimization, allowing the design team to adjust the circuit design in a targeted manner, reduce the bit error rate, and thus improve the accuracy and stability of data transmission. In addition, the power rail abnormality detection is performed based on the circuit board design abnormality data, which can promptly discover problems in power management and ensure the reliability of the circuit in terms of power supply. This detection is crucial to maintaining system stability, because the abnormality of the power rail directly leads to the failure of the entire circuit. Further, the voltage fluctuation calculation is performed based on the power rail abnormality data, which helps to quantify the stability of the power supply. This process enables the design team to identify the impact of unstable power supply, adjust the power supply design in time to reduce fluctuations, and ensure the normal operation of electronic components. Finally, the circuit failure probability calculation is combined with the voltage fluctuation data and the bit error rate growth data to comprehensively evaluate the failure risk of the circuit under actual working conditions. This calculation helps to take preventive measures in the design stage, reduce the probability of failure, and ensure the high reliability and stability of electronic equipment in actual operation.

[0037] Preferably, step S3 comprises the following steps:

[0038] Step S31: performing electronic component current detection on the electronic component short-circuit fault data to obtain electronic component short-circuit current data;

[0039] Step S32: performing heat accumulation simulation of electronic components according to the short-circuit current data of the electronic components and the circuit failure probability data to obtain heat accumulation data of the electronic components;

[0040] Step S33: Calculating the electronic component failure probability according to the electronic component current overload data and the electronic component heat accumulation data to obtain the electronic component failure probability data;

[0041] Step S34: estimating the aging trend of electronic components according to the electronic component failure probability data, the electronic component heat accumulation data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data.

[0042] The present invention can further improve the fault management and analysis capabilities of electronic components through the implementation of this series of steps. First, the short-circuit fault data of the electronic components is detected by current, and the current change under the short-circuit condition can be monitored in real time, thereby obtaining the short-circuit current data. This data helps to identify the severity of the short-circuit fault and take necessary measures in time to prevent further damage. Next, heat accumulation simulation is performed based on the short-circuit current data and the circuit failure probability data, which helps to quantify the heat generation of components under the short-circuit condition. This simulation analysis can reveal the thermal stress faced by components under overload conditions, thereby providing an important basis for fault prevention and ensuring that the design team can consider thermal management strategies in the design stage. Further, the failure probability of electronic components is calculated based on the current overload data and the heat accumulation data, which can more accurately evaluate the failure risk of components under different working conditions. This calculation not only improves the accuracy of fault prediction, but also helps designers identify high-risk components, thereby making corresponding adjustments in the design and reducing the probability of failure. Finally, by combining the failure probability data, the heat accumulation data and the cross-wiring electromagnetic radiation enhancement data to predict the aging trend of electronic components, the service life and performance degradation trend of components can be effectively predicted. This estimate provides a basis for the development of maintenance plans, allowing the team to take maintenance measures in advance, extend the service life of components, and ensure the long-term stability of electronic equipment.

[0043] Preferably, step S32 includes the following steps:

[0044] Step S321: Acquire rated current data of electronic components;

[0045] Step S322: Calculating the frequency of occurrence of transient voltage on the circuit board based on the circuit failure probability data to obtain data on the frequency of occurrence of transient voltage on the circuit board;

[0046] Step S323: Calculate the circuit board current surge based on the circuit board transient voltage frequency data and the electronic component short-circuit current data to obtain the electronic component current surge data;

[0047] Step S324: performing current overload division on the rated current data of the electronic components according to the current surge data of the electronic components to obtain current overload data of the electronic components;

[0048] Step S325: Calculating the growth of power loss of electronic components according to the current overload data of the electronic components to obtain the growth data of power loss of electronic components;

[0049] Step S326: Detecting the continuous increase in component temperature based on the electronic component power loss growth data and the electronic component current surge data, and obtaining the electronic component temperature continuous increase data;

[0050] Step S327: performing electronic component heat accumulation simulation on the electronic component temperature continuous increase data and the electronic component power loss growth data to obtain electronic component heat accumulation data.

[0051] The present invention can significantly improve the fault management and analysis capabilities of electronic components through the implementation of this series of steps. First, obtaining the rated current data of the electronic components provides a benchmark for subsequent overload analysis, so that the design team can clearly understand the safe operating range of each component. The acquisition of this basic data is an important prerequisite for ensuring the stability of the system. Next, by calculating the transient voltage occurrence frequency of the circuit failure probability data, the frequency of transient voltage occurrence of the circuit under different working conditions can be quantified. This information provides an important basis for understanding the response of the circuit under transient conditions and helps to identify the risk of causing failures under specific circumstances. On this basis, the current surge calculation based on the transient voltage occurrence frequency data and the short-circuit current data can evaluate the current mutation experienced by the components under sudden conditions. This calculation enables designers to identify the current overload situation in advance, so as to take corresponding preventive measures. Further, the rated current data is divided into current overloads according to the current surge data, which can effectively identify the specific situation of the current overload. This division provides an important basis for the subsequent power loss analysis, so that the design team can optimize the circuit design in a targeted manner and ensure that the components work within a safe range. Subsequently, the power loss growth calculation based on the current overload data can quantify the additional heat generated by the components under overload conditions. This data is crucial to evaluating the thermal performance of components and can help the design team develop an effective heat dissipation solution. Continuing, the continuous temperature rise detection using the power loss growth data and the current surge data helps to identify the temperature changes of components under extreme conditions. This detection can timely discover potential thermal runaway risks, thereby providing strong support for fault prevention. Finally, by simulating the heat accumulation of the continuous temperature rise data and the power loss growth data, the thermal management capabilities of the components can be fully evaluated. This simulation result provides an important reference for optimizing the design and ensures that electronic components can operate safely and reliably under various working conditions.

[0052] Preferably, step S34 includes the following steps:

[0053] Step S341: performing thermal expansion detection of electronic components according to heat accumulation data of electronic components to obtain thermal expansion data of electronic components;

[0054] Step S342: Calculate the stress growth of the connection points according to the thermal expansion data of the electronic components to obtain the stress growth data of the connection points of the electronic components;

[0055] Step S343: performing connection point failure prediction on the electronic component connection point stress growth data and the electronic component thermal expansion data to obtain connection point failure data;

[0056] Step S344: estimating the electronic component function degradation according to the connection point failure data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component function degradation data;

[0057] Step S345: estimating the aging trend of electronic components based on the electronic component function degradation data, the connection point failure data, and the electronic component failure probability data to obtain the electronic component aging trend data.

[0058] First, the present invention performs thermal expansion detection based on heat accumulation data, which can quantify the expansion of components caused by temperature changes during operation. This detection provides a basis for understanding the physical changes of components under different thermal conditions, ensuring that the structural impact is considered in the design stage. Next, the connection point stress growth calculation is performed based on the thermal expansion data, which helps to evaluate the connection point stress changes caused by thermal expansion. This analysis can reveal the potential risks of the connection point under high temperature conditions and help the design team identify the failure point. The connection point failure prediction based on the connection point stress growth data and thermal expansion data can more accurately predict the reliability of the connection point under working conditions. This prediction provides an important basis for the formulation of fault prevention and maintenance plans, ensuring that effective intervention measures can be taken before the failure occurs. The functional degradation prediction is combined with the connection point failure data and the electromagnetic radiation enhancement data, so that the team can identify the functional degradation caused by the connection point failure. This evaluation helps to discover the performance problems encountered by the system in actual operation in advance, thereby providing guidance for the optimization design. By predicting the aging trend of the functional degradation data, the connection point failure data and the failure probability data, the performance changes of the components during long-term use can be comprehensively evaluated. This trend analysis provides a basis for the formulation of maintenance and replacement strategies, enabling the team to promptly maintain or replace components based on estimated aging conditions to ensure system stability and reliability.

[0059] Preferably, step S4 comprises the following steps:

[0060] Step S41: estimating the life attenuation of electronic components according to the electronic component aging trend data and the electronic component failure probability data to obtain the electronic component life attenuation data;

[0061] Step S42: performing circuit board design defect analysis on the circuit board design data according to the electronic component life attenuation data and the electronic component aging trend data to obtain circuit board design defect data;

[0062] Step S43: optimizing the circuit board design data according to the circuit board design defect data and the electronic component failure probability data to obtain circuit board design optimization data;

[0063] Step S44: performing available performance enhancement calculation of electronic components according to the circuit board design optimization data to obtain available performance enhancement data of electronic components.

[0064] The present invention estimates the life attenuation according to the aging trend data and failure probability data of electronic components, which helps to quantify the performance degradation of components during actual use. This estimate provides a scientific basis for subsequent maintenance and replacement strategies, enabling the design team to take necessary measures before the components reach a critical state, thereby avoiding sudden failures. Next, the circuit board design data is defect analyzed using the life attenuation data and the aging trend data to identify potential problems in the design. This analysis can reveal the design defects that lead to early failure of electronic components, provide the design team with a direction for improvement, and ensure that future designs are more reasonable. On this basis, the circuit board design is optimized according to the design defect data and the failure probability data, which can improve the robustness and reliability of the design. Through optimization, the design team can ensure that the circuit board can effectively support the normal operation of components under various working conditions, thereby reducing the risk of failure. Finally, the available performance enhancement calculation of electronic components is performed based on the optimized design data, and the performance improvement brought by the optimization can be quantified. This process not only improves the performance of components in practical applications, but also enhances the reliability and efficiency of the entire system.

[0065] This specification also provides an electronic component for executing the above-mentioned electronic component fault management method, the electronic component comprising:

[0066] Circuit board cross wiring statistics module: obtain circuit board design data; perform circuit wiring analysis based on the circuit board design data to obtain circuit wiring data; perform cross wiring statistics on the circuit wiring data to obtain circuit board cross wiring data;

[0067] Short-circuit fault detection module: Perform electromagnetic radiation enhancement detection based on the cross-wiring data of the circuit board to obtain the cross-wiring electromagnetic radiation enhancement data; perform circuit fault probability calculation based on the circuit board cross-wiring data and the cross-wiring electromagnetic radiation enhancement data to obtain circuit fault probability data; perform electronic component short-circuit fault detection based on the circuit fault probability data to obtain electronic component short-circuit fault data;

[0068] Aging trend prediction module: calculate the electronic component failure probability based on the electronic component short-circuit failure data and circuit failure probability data to obtain the electronic component failure probability data; predict the electronic component aging trend based on the electronic component failure probability data and cross-wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data;

[0069] Available performance enhancement calculation module: based on the electronic component aging trend data and the electronic component failure probability data, the circuit board design data is optimized to obtain the circuit board design optimization data; based on the circuit board design optimization data, the available performance enhancement calculation of the electronic components is performed to obtain the available performance enhancement data of the electronic components.

[0070] Beneficial effects of the present invention: Through the implementation of this series of steps, the present invention can significantly improve the fault management and analysis effect of electronic components, obtain circuit board design data and perform wiring analysis, which is helpful to deeply understand the structure and function of the circuit, identify potential design defects, ensure reasonable wiring, and thus reduce the risk of signal interference. Cross wiring statistics not only provide an intuitive assessment of wiring complexity, but also lay the foundation for subsequent electromagnetic radiation detection. Secondly, by performing electromagnetic radiation enhancement detection through cross wiring data, the radiation level and its impact on circuit performance can be quantified. This process helps to identify the hidden faults caused by electromagnetic radiation as early as possible. Combined with the calculation of fault probability, the failure risk of each component in the circuit can be accurately predicted, thereby reducing the probability of short circuit failure and enhancing the stability and reliability of the system. Further analysis of short circuit fault data and fault probability data can more carefully evaluate the failure trend of each component. Combined with electromagnetic radiation data, this analysis provides a scientific basis for the prediction of the aging trend of electronic components, so that in the life cycle of the equipment, it is possible to effectively monitor and respond to the performance degradation caused by component aging, and improve the overall reliability of the equipment. Finally, through the comprehensive analysis of aging trend and fault probability data, the circuit board design can be optimized to ensure that the circuit is more reliable and efficient in practical applications. This optimization can not only significantly improve the usability of components, but also reduce downtime and maintenance costs caused by failures, thereby improving the overall performance and market competitiveness of electronic equipment. Therefore, the present invention is an optimization of a traditional electronic component failure management method, which solves the problem of inaccurate analysis of failure causes and inaccurate prediction of aging and attenuation of electronic components in the traditional electronic component failure management method, and improves the accuracy of failure cause analysis and aging and attenuation prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 A schematic diagram of the steps of a fault management method for electronic components;

[0072] Figure 2 for Figure 1 Detailed implementation steps of step S2 in the flowchart;

[0073] Figure 3 for Figure 1 Detailed implementation steps of step S3 in FIG.

[0074] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0075] The technical method of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0076] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0077] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0078] To achieve this, please refer to Figures 1 to 3 , a fault management method for electronic components, comprising the following steps:

[0079] Step S1: Acquire circuit board design data; perform circuit wiring analysis according to the circuit board design data to obtain circuit wiring data; perform cross wiring statistics on the circuit wiring data to obtain circuit board cross wiring data;

[0080] Step S2: Perform electromagnetic radiation enhancement detection according to the cross wiring data of the circuit board to obtain cross wiring electromagnetic radiation enhancement data; perform circuit fault probability calculation according to the circuit board cross wiring data and the cross wiring electromagnetic radiation enhancement data to obtain circuit fault probability data; perform electronic component short circuit fault detection according to the circuit fault probability data to obtain electronic component short circuit fault data;

[0081] Step S3: Calculate the electronic component failure probability based on the electronic component short circuit failure data and the circuit failure probability data to obtain the electronic component failure probability data; and estimate the electronic component aging trend based on the electronic component failure probability data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data;

[0082] Step S4: optimizing the circuit board design data according to the electronic component aging trend data and the electronic component failure probability data to obtain circuit board design optimization data; performing electronic component available performance enhancement calculation according to the circuit board design optimization data to obtain electronic component available performance enhancement data.

[0083] In the embodiment of the present invention, reference Figure 1 The above is a schematic flow chart of the steps of a fault management method for electronic components of the present invention. In this example, the fault management method for electronic components includes the following steps:

[0084] Step S1: Acquire circuit board design data; perform circuit wiring analysis according to the circuit board design data to obtain circuit wiring data; perform cross wiring statistics on the circuit wiring data to obtain circuit board cross wiring data;

[0085] In an embodiment of the present invention, firstly, circuit board design data is obtained, which includes information such as wiring diagram, component layout and electrical parameters. These data are usually exported by PCB design software (such as Altium Designer or Eagle) to ensure the integrity and accuracy of the data. Next, a special wiring analysis tool is used to analyze the circuit wiring and extract wiring data, including information such as line width, line spacing and wiring hierarchy. The analysis tool can provide detailed wiring information for subsequent statistics. Then, the extracted circuit wiring data is cross-wiring counted to identify and record all intersections and their related parameters, such as intersection angles and intersection numbers. This process is usually carried out using data processing software (such as MATLAB or Python), and the circuit board cross wiring data is generated by scripting automation processing.

[0086] Step S2: Perform electromagnetic radiation enhancement detection according to the cross wiring data of the circuit board to obtain cross wiring electromagnetic radiation enhancement data; perform circuit fault probability calculation according to the circuit board cross wiring data and the cross wiring electromagnetic radiation enhancement data to obtain circuit fault probability data; perform electronic component short circuit fault detection according to the circuit fault probability data to obtain electronic component short circuit fault data;

[0087] In an embodiment of the present invention, electromagnetic radiation enhancement detection is first performed based on the cross wiring data of the circuit board. This process uses an electromagnetic simulation tool (such as HFSS or CST Microwave Studio) to perform modeling, inputs the cross wiring data, performs electromagnetic field analysis, and calculates the impact of the cross wiring on electromagnetic radiation. The obtained cross wiring electromagnetic radiation enhancement data is used for subsequent analysis. Next, the circuit board cross wiring data is combined with the cross wiring electromagnetic radiation enhancement data, and a probability calculation method (such as fault tree analysis or Monte Carlo simulation) is used to evaluate the circuit failure probability. By establishing a fault model, identifying the fault path, calculating the probability of occurrence of each fault mode, and finally obtaining the circuit failure probability data. Finally, electronic component short circuit fault detection is performed based on the circuit failure probability data, and special test equipment (such as an oscilloscope and a multimeter) is used to perform electrical testing on the components, detect short circuit phenomena, and record and generate electronic component short circuit fault data.

[0088] Step S3: Calculate the electronic component failure probability based on the electronic component short circuit failure data and the circuit failure probability data to obtain the electronic component failure probability data; and estimate the electronic component aging trend based on the electronic component failure probability data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data;

[0089] In the embodiment of the present invention, firstly, the electronic component short circuit fault data and the circuit fault probability data are comprehensively analyzed, and the electronic component fault probability is calculated using statistical analysis software (such as R or SPSS). By analyzing the fault occurrence frequency and its influencing factors, an electronic component fault probability model is constructed to obtain the electronic component fault probability data, and the electronic component aging trend is estimated based on the electronic component fault probability data and the cross wiring electromagnetic radiation enhancement data. This process adopts the historical data analysis method, and the future aging trend is predicted by performing regression analysis on the aging data of the components under different working environments, and finally the electronic component aging trend data is obtained.

[0090] Step S4: optimizing the circuit board design data according to the electronic component aging trend data and the electronic component failure probability data to obtain circuit board design optimization data; performing electronic component available performance enhancement calculation according to the circuit board design optimization data to obtain electronic component available performance enhancement data.

[0091] In an embodiment of the present invention, firstly, the circuit board design data is optimized according to the electronic component aging trend data and the electronic component failure probability data. The current design is simulated using circuit simulation software (such as LTspice or PSpice) to analyze the influence of different design parameters on the failure probability and aging trend. By adjusting the design parameters (such as wiring width, spacing and number of layers), the circuit board design is optimized to reduce the risk of failure. After the optimization is completed, the circuit board design optimization data is generated. Finally, the electronic component available performance enhancement calculation is performed according to the circuit board design optimization data, the performance of the components designed after optimization is evaluated using a performance analysis tool, the improved performance data is recorded, and the electronic component available performance enhancement data is obtained.

[0092] Preferably, step S1 comprises the following steps:

[0093] Step S11: obtaining circuit board design data;

[0094] Step S12: collecting distribution information of electronic components according to the circuit board design data to obtain distribution information of electronic components;

[0095] Step S13: performing circuit wiring analysis according to the electronic component distribution data and the circuit board design data to obtain circuit wiring data;

[0096] Step S14: Perform cross-wiring statistics on the circuit wiring data and the electronic component distribution data to obtain circuit board cross-wiring data.

[0097] In an embodiment of the present invention, firstly, circuit board design data is obtained, and the data includes circuit diagram, component list, hierarchical information and electrical parameters, etc. The data is usually generated by a PCB design tool (such as Altium Designer or Cadence) and exported as a standard format file, such as a Gerber file or an IPC-D-356 format file, to ensure the readability and integrity of the data. Based on the obtained circuit board design data, the distribution of electronic components is collected, and the actual position and distribution information of the components on the circuit board are extracted through the component layout function in the circuit design tool, including the coordinates, size and type of each component, etc., and these data are exported to a structured format (such as CSV or Excel) for subsequent statistical analysis. This step needs to ensure that the layout of components is accurately recorded, and circuit wiring analysis is performed according to the electronic component distribution data and circuit board design data. Using the wiring analysis tool, the design data and component distribution information are input to perform signal integrity and electrical characteristics analysis. By evaluating the signal path of the circuit board, parameters such as line width, line spacing and layer spacing are calculated to generate circuit wiring data. Conduct cross wiring statistics on circuit wiring data and electronic component distribution data, identify crossover points in circuit wiring through data processing tools, and record crossover line pairs and their positions. This process includes analyzing the relative position, crossover angle and number of crossovers between lines, and generating detailed cross wiring data reports, including the frequency and type of cross wiring and factors affecting signal transmission.

[0098] Preferably, step S2 comprises the following steps:

[0099] Step S21: performing electromagnetic radiation enhancement detection according to the cross wiring data of the circuit board to obtain cross wiring electromagnetic radiation enhancement data;

[0100] Step S22: performing circuit board design abnormality analysis according to the circuit board cross wiring data and the cross wiring electromagnetic radiation enhancement data to obtain circuit board design abnormality data;

[0101] Step S23: Calculate the circuit failure probability according to the circuit board design abnormality data and the cross wiring electromagnetic radiation enhancement data to obtain circuit failure probability data;

[0102] Step S24: performing electronic component short circuit fault detection according to the circuit fault probability data and the circuit board design abnormality data to obtain electronic component short circuit fault data.

[0103] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes:

[0104] Step S21: performing electromagnetic radiation enhancement detection according to the cross wiring data of the circuit board to obtain cross wiring electromagnetic radiation enhancement data;

[0105] In an embodiment of the present invention, electromagnetic radiation enhancement detection is first performed based on the cross wiring data of the circuit board. This process uses an electromagnetic field simulation tool (such as CST Microwave Studio or ANSYS HFSS) to import the cross wiring data into the software and establish an electromagnetic model of the circuit board. The model is analyzed in the frequency domain to calculate the distribution and intensity of electromagnetic radiation, focusing on the radiation enhancement effect of the cross wiring area. The detection results generate cross wiring electromagnetic radiation enhancement data, which includes electromagnetic radiation intensity, frequency response and its potential impact on circuit performance.

[0106] Step S22: performing circuit board design abnormality analysis according to the circuit board cross wiring data and the cross wiring electromagnetic radiation enhancement data to obtain circuit board design abnormality data;

[0107] In an embodiment of the present invention, circuit board design anomaly analysis is performed based on circuit board cross wiring data and cross wiring electromagnetic radiation enhancement data. First, the cross wiring data is statistically analyzed using data processing software (such as MATLAB or Python) to identify potential design anomalies, such as excessive cross frequency or improper component layout, and the electromagnetic radiation enhancement data is combined with the design data to determine the abnormal situation by setting a threshold. The analysis results generate circuit board design anomaly data, which lists all identified design defects, including wiring problems that cause electromagnetic interference.

[0108] Step S23: Calculate the circuit failure probability according to the circuit board design abnormality data and the cross wiring electromagnetic radiation enhancement data to obtain circuit failure probability data;

[0109] In the embodiment of the present invention, the circuit failure probability is calculated based on the circuit board design abnormality data and the cross wiring electromagnetic radiation enhancement data. The fault tree analysis method is used to first establish a fault model, and the identified design abnormality is used as the root cause of the potential fault. Combined with the cross wiring electromagnetic radiation enhancement data, the probability of occurrence of each fault mode is calculated to determine the critical fault path. This process uses statistical analysis tools (such as R or SPSS) to process the data, and finally obtains the circuit failure probability data.

[0110] Step S24: performing electronic component short circuit fault detection according to the circuit fault probability data and the circuit board design abnormality data to obtain electronic component short circuit fault data.

[0111] In an embodiment of the present invention, short-circuit fault detection of electronic components is performed based on circuit fault probability data and circuit board design abnormality data. First, a detection scheme is established, and electrical tests are performed on key components using dedicated test equipment (such as a digital oscilloscope and a multimeter). During the test, current and voltage changes are monitored to identify short circuit phenomena. By analyzing the fault probability data, high-risk components and locations are determined, and these areas are focused on for detailed detection. Finally, the test results are recorded to generate electronic component short-circuit fault data.

[0112] Preferably, step S21 includes the following steps:

[0113] Step S211: Calculate the circuit board loop area growth using the circuit board cross wiring data to obtain circuit board loop area growth data;

[0114] Step S212: Calculating the circuit board route spacing according to the circuit board loop area growth data and the circuit board cross wiring data to obtain the circuit board route spacing data;

[0115] Step S213: performing signal line crossing acquisition according to the circuit board cross wiring data to obtain circuit board signal line crossing data;

[0116] Step S214: performing electromagnetic coupling effect enhancement calculation according to the circuit board signal line crossing data and the circuit board route spacing data to obtain circuit board electromagnetic coupling effect enhancement data;

[0117] Step S215: Perform electromagnetic radiation enhancement detection according to the circuit board electromagnetic coupling effect enhancement data and the circuit board loop area growth data to obtain cross wiring electromagnetic radiation enhancement data.

[0118] In an embodiment of the present invention, the circuit board cross wiring data is used to calculate the circuit board loop area growth. First, the cross wiring data of the circuit board is extracted, including the location of the intersection and the relevant line segment information, and the loop area change caused by the cross wiring is calculated by a mathematical algorithm. The calculation can be implemented by a programming language (such as Python), and the wiring intersection area is identified by a geometric calculation method, and its area is integrated. Finally, the circuit board loop area growth data is generated, including the comparison information of the loop area before and after the cross wiring, and the circuit board route spacing is calculated according to the circuit board loop area growth data and the circuit board cross wiring data, and the specific value of the loop area growth data is determined, and the cross wiring data is analyzed to identify the factors affecting the wiring spacing, and the circuit design standards and specifications are used to set the calculation formula of the route spacing, considering the signal integrity and electromagnetic compatibility, and using the formula to calculate the optimal route spacing. According to the circuit board cross wiring data, the signal line cross collection is performed, the cross wiring data is analyzed, and the intersection of all signal lines is identified, including the intersection of the line segments, angles and quantity information. The cross wiring data is processed using a data analysis tool (such as Python's Pandas library), and a program is written to extract the intersection of the signal lines to generate signal line intersection data. According to the circuit board signal line crossing data and circuit board route spacing data, the electromagnetic coupling effect enhancement calculation is performed. The model is established using an electromagnetic field simulation tool (such as CST or HFSS), and the signal line crossing data and route spacing information are input. Perform electromagnetic field analysis to calculate the electromagnetic coupling effect between signal lines, with particular attention to the degree of electromagnetic interference in the crossing area. The simulation results generate electromagnetic coupling effect enhancement data, including coupling coefficient, interference amplitude and its impact on signal transmission. According to the circuit board electromagnetic coupling effect enhancement data and circuit board loop area growth data, electromagnetic radiation enhancement detection is performed. The electromagnetic coupling effect enhancement data is combined with the loop area growth data, and analyzed through the electromagnetic radiation calculation formula to determine the degree of electromagnetic radiation enhancement. This process can use electromagnetic simulation tools to verify the model, input the required parameters for radiation intensity analysis, and obtain electromagnetic radiation enhancement data.

[0119] Preferably, step S23 includes the following steps:

[0120] Step S231: Calculate the signal phase offset according to the cross wiring electromagnetic radiation enhancement data to obtain circuit board signal phase offset data;

[0121] Step S232: performing circuit board synchronization failure detection according to the circuit board signal phase offset data to obtain circuit board synchronization failure data;

[0122] Step S233: Calculate the circuit board bit error rate growth by using the circuit board synchronization failure data and the circuit board signal phase offset data to obtain the circuit board bit error rate growth data;

[0123] Step S234: performing power rail abnormality detection according to the circuit board design abnormality data to obtain the circuit board power rail abnormality data;

[0124] Step S235: Calculating circuit board voltage fluctuation according to circuit board power rail abnormality data to obtain circuit board voltage fluctuation data;

[0125] Step S236: Calculate the circuit failure probability based on the circuit board voltage fluctuation data and the circuit board bit error rate growth data to obtain circuit failure probability data.

[0126] In an embodiment of the present invention, a signal phase offset calculation is performed based on the cross wiring electromagnetic radiation enhancement data. The calculation is performed by using a high-precision measuring instrument such as an oscilloscope to obtain the signal waveform at different points of the circuit board. After obtaining the signal waveform, the phase difference of each signal point is analyzed, and the phase information of each signal point is recorded by setting a reference signal to calculate the phase offset. The time domain signal is converted into the frequency domain by using the FFT (Fast Fourier Transform) algorithm, and the frequency component of the signal is further identified to obtain the signal phase offset data. According to the circuit board signal phase offset data, a circuit board synchronization failure detection is performed. The detection is performed by using a logic analyzer to monitor the synchronization of the signal. The signal phase offset data is compared with the preset synchronization standard to identify the signal that deviates from the standard. During the detection process, it is verified one by one whether the phase of each signal channel meets the set synchronization requirements, and the synchronization failure event and the time and frequency of its occurrence are recorded, and finally the circuit board synchronization failure data is generated. The circuit board bit error rate growth calculation is performed using the circuit board synchronization failure data and the circuit board signal phase offset data, and a long-term data transmission test is performed on each signal channel of the circuit, and the bit error rate is calculated by recording the ratio of the received valid data to the error data. On this basis, combined with the synchronization failure data, the growth trend of the bit error rate under the synchronization failure is analyzed. The bit error rates under different test conditions are compared by using statistical analysis tools, and the bit error rate growth data of the circuit board is finally obtained. The power rail anomaly detection is performed according to the abnormal data of the circuit board design. The voltage change on the power rail is continuously monitored by the voltage monitor and compared with the design standard. The monitored voltage data is compared with the expected value of the power rail in real time to identify any abnormal fluctuations in the power rail. At the same time, the response characteristics of the power rail under load changes are recorded by an oscilloscope to determine the stability of the power rail, and finally a power rail abnormal data report is formed. The circuit board voltage fluctuation is calculated according to the abnormal data of the circuit board power rail, and the voltage change amplitude and frequency are extracted by analyzing the voltage data obtained in the power rail abnormal detection stage. The voltage fluctuation is statistically analyzed by using data processing software, and the standard deviation of the voltage fluctuation and its change in a specific time period are calculated. Through comparative analysis, it is determined whether the voltage fluctuation exceeds the design allowable range, and the voltage fluctuation data is recorded. The circuit failure probability is calculated according to the circuit board voltage fluctuation data and the circuit board bit error rate growth data. Using the Bayesian analysis method, the historical data of voltage fluctuation and bit error rate are input into the statistical model, and the probability of circuit failure under current conditions is calculated through the probability inference algorithm. By constructing a fault tree analysis model and combining the impact of voltage fluctuation on the normal operation of the circuit, the circuit failure probability data is finally obtained.

[0127] Preferably, step S3 comprises the following steps:

[0128] Step S31: performing electronic component current detection on the electronic component short-circuit fault data to obtain electronic component short-circuit current data;

[0129] Step S32: performing heat accumulation simulation of electronic components according to the short-circuit current data of the electronic components and the circuit failure probability data to obtain heat accumulation data of the electronic components;

[0130] Step S33: Calculating the electronic component failure probability according to the electronic component current overload data and the electronic component heat accumulation data to obtain the electronic component failure probability data;

[0131] Step S34: estimating the aging trend of electronic components according to the electronic component failure probability data, the electronic component heat accumulation data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data.

[0132] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes:

[0133] Step S31: performing electronic component current detection on the electronic component short-circuit fault data to obtain electronic component short-circuit current data;

[0134] In an embodiment of the present invention, when performing current detection on the short-circuit fault data of electronic components, it is first necessary to use a high-precision current detection instrument, such as a current clamp meter or an oscilloscope, to clamp the wire connected to the component to be tested in the circuit to monitor the current value in real time under the short-circuit condition. In the specific operation, first disconnect the power supply to ensure safety, and then connect the detection instrument to the power supply line of the component. After the power is turned on, the current waveform and value when the short circuit occurs are recorded, and stable current data is obtained through multiple detections. Finally, the current data is analyzed to confirm the actual value of the short-circuit current, and the results are organized into short-circuit current data of the electronic components.

[0135] Step S32: performing heat accumulation simulation of electronic components according to the short-circuit current data of the electronic components and the circuit failure probability data to obtain heat accumulation data of the electronic components;

[0136] In an embodiment of the present invention, heat accumulation simulation is performed based on the short-circuit current data of electronic components and the circuit failure probability data. This step first requires collecting short-circuit current data, and using thermal analysis software (such as ANSYS, etc.) to simulate and calculate heat accumulation. Set the material properties and thermal conductivity characteristics of the circuit elements, input the short-circuit current data and run the simulation. During the simulation process, the heat generated when the current passes through the components is calculated, with particular attention paid to the distribution of heat inside the components. The results will include temperature changes at different time points to form heat accumulation data of electronic components and analyze the thermal stress of components under different working conditions.

[0137] Step S33: Calculating the electronic component failure probability according to the electronic component current overload data and the electronic component heat accumulation data to obtain the electronic component failure probability data;

[0138] In an embodiment of the present invention, the failure probability is calculated based on the current overload data of the electronic components and the heat accumulation data of the electronic components. First, the current overload data and the heat accumulation data are input into the fault tree analysis to evaluate the impact of different current levels and heat accumulation on the performance of the components. The historical failure data is used as a reference, and the probability of component failure under specific conditions is calculated in combination with statistical methods. By constructing an association model, the correlation between current and heat on the occurrence of failures is analyzed, thereby obtaining the failure probability data of the electronic components.

[0139] Step S34: estimating the aging trend of electronic components according to the electronic component failure probability data, the electronic component heat accumulation data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data.

[0140] In an embodiment of the present invention, the aging trend of electronic components is estimated based on the electronic component failure probability data, heat accumulation data, and cross-wiring electromagnetic radiation enhancement data. This step requires first sorting out the failure probability data and heat accumulation data, and combining these data with the cross-wiring electromagnetic radiation enhancement data. The time series analysis method is used to analyze the aging trend of components under different electromagnetic radiation and heat accumulation conditions. By establishing an aging model, the long-term performance attenuation of components is evaluated, and the aging trend data of electronic components is generated.

[0141] Preferably, step S32 includes the following steps:

[0142] Step S321: Acquire rated current data of electronic components;

[0143] Step S322: Calculating the frequency of occurrence of transient voltage on the circuit board based on the circuit failure probability data to obtain data on the frequency of occurrence of transient voltage on the circuit board;

[0144] Step S323: Calculate the circuit board current surge based on the circuit board transient voltage frequency data and the electronic component short-circuit current data to obtain the electronic component current surge data;

[0145] Step S324: performing current overload division on the rated current data of the electronic components according to the current surge data of the electronic components to obtain current overload data of the electronic components;

[0146] Step S325: Calculating the growth of power loss of electronic components according to the current overload data of the electronic components to obtain the growth data of power loss of electronic components;

[0147] Step S326: Detecting the continuous increase in component temperature based on the electronic component power loss growth data and the electronic component current surge data, and obtaining the electronic component temperature continuous increase data;

[0148] Step S327: performing electronic component heat accumulation simulation on the electronic component temperature continuous increase data and the electronic component power loss growth data to obtain electronic component heat accumulation data.

[0149] In the embodiment of the present invention, when obtaining the rated current data of electronic components, it is first necessary to refer to the technical specifications of the components, which provide the rated working conditions and parameters of each component. In a laboratory environment, by using a high-precision ammeter, measurements are performed under the working conditions of different types of electronic components (such as resistors, capacitors, transistors, etc.). Connect the ammeter to the circuit, adjust the power supply to the rated voltage, and record the current value at the rated voltage to ensure that the current is within the safe working range of the components. All measured data should be classified and sorted to generate the rated current data of the electronic components. When calculating the frequency of occurrence of transient voltage on the circuit board for the circuit failure probability data, it is necessary to analyze the historical data of voltage changes in the circuit. Use an oscilloscope to monitor the transient voltage that occurs during the operation of the circuit board, and record the frequency of occurrence of transient voltage events. Through multiple tests, collect enough transient voltage data, and use statistical tools (such as Excel or Matlab) to calculate the frequency of occurrence of transient voltage. This frequency data will be used for subsequent analysis to evaluate the stability and failure risk of the circuit. When calculating the circuit board current surge based on the transient voltage frequency data of the circuit board and the short-circuit current data of the electronic components, the transient voltage data is combined with the short-circuit current data to analyze the current surge when the transient voltage event occurs. Use an oscilloscope to record the current change when the transient voltage occurs, and calculate the maximum current surge value through the collected data. Data processing software can be used to graphically display the collected data, analyze the current surge characteristics, and finally generate the electronic component current surge data. According to the electronic component current surge data, the rated current data of the electronic components is divided into current overload, and all the collected current surge data are compared with the rated current to identify which data exceeds the rated value. In this process, a threshold can be set to divide the current value into normal and overload. Record the situation exceeding the rated current in detail, mark the specific situation of the current overload, and archive it as the electronic component current overload data. When calculating the power loss growth based on the electronic component current overload data, the power loss of each component in the overload state is calculated by inputting the current overload data and the corresponding resistance value. Through multiple measurements and calculations, the growth of power loss with current overload is obtained, and finally the power loss growth data of electronic components is generated. The continuous temperature increase of components is detected based on the power loss growth data of electronic components and the current surge data of electronic components. This step requires the use of a thermal imager or temperature sensor to continuously monitor the temperature changes of components under working conditions. Record the curve of temperature change over time and analyze whether the temperature of components continues to rise when the current surges and power loss increase. By comparing multiple experimental data, the temperature change trend of components is determined, and the continuous temperature increase data of electronic components is generated.When simulating heat accumulation for the data of the continuous increase in temperature of electronic components and the increase in power loss of electronic components, use data recording and processing tools (such as Matlab or Python) to analyze the relationship between temperature and power loss. By inputting the power loss data into the heat accumulation calculation model, the heat accumulation of components under different working conditions is simulated. Pay special attention to the heat distribution inside the components, and finally generate the heat accumulation data of electronic components by setting different working times and ambient temperatures.

[0150] Preferably, step S34 includes the following steps:

[0151] Step S341: performing thermal expansion detection of electronic components according to heat accumulation data of electronic components to obtain thermal expansion data of electronic components;

[0152] Step S342: Calculate the stress growth of the connection points according to the thermal expansion data of the electronic components to obtain the stress growth data of the connection points of the electronic components;

[0153] Step S343: performing connection point failure prediction on the electronic component connection point stress growth data and the electronic component thermal expansion data to obtain connection point failure data;

[0154] Step S344: estimating the electronic component function degradation according to the connection point failure data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component function degradation data;

[0155] Step S345: estimating the aging trend of electronic components based on the electronic component function degradation data, the connection point failure data, and the electronic component failure probability data to obtain the electronic component aging trend data.

[0156] In an embodiment of the present invention, when performing thermal expansion detection according to the heat accumulation data of electronic components, a high-precision temperature sensor or thermal imager is first used to record the temperature change of the components during operation. The thermal expansion amount of the components at a specific temperature is determined by calculating the collected temperature data with the thermal expansion coefficient of the material. The required data can be obtained through actual testing, for example, placing the electronic components in a temperature-controlled environment, gradually increasing the temperature to the working range, and recording the thermal expansion amount at each temperature point. Finally, the thermal expansion data of the electronic components are formed, specifically including the expansion of each material at different temperatures. When calculating the stress growth of the connection point according to the thermal expansion data of the electronic components, it is necessary to understand the material properties of the connection point and its bearing capacity. Use stress analysis software (such as ANSYS or SolidWorks) to model the connection point, input thermal expansion data, and simulate the stress effect of thermal expansion on the connection point. During the simulation process, different temperature conditions and connection point geometries are set to calculate the stress distribution caused by temperature changes. The output results should include the stress growth of the connection point at different temperatures to generate stress growth data of the electronic component connection point. When estimating the failure of electronic component connection points based on stress growth data and thermal expansion data of electronic components, failure analysis methods, especially fatigue analysis, need to be used. Combine the stress data of connection points with the thermal expansion data, and use reliability analysis tools (such as Weibull analysis) to evaluate the failure probability of connection points under expected working conditions. By defining the stress-life curve, the fatigue life of the connection points under specific stress conditions is determined, thereby generating connection point failure data. When estimating the functional degradation of electronic components based on the connection point failure data and the electromagnetic radiation enhancement data of cross wiring, the connection point failure data needs to be sorted out, and the failure mode and effects analysis (FMEA) method is used in combination with the influence of electromagnetic radiation. By constructing an influence matrix, the potential impact of connection point failure on component functions is evaluated, and the degree of its impact on the overall performance of the system is quantified. Use statistical analysis tools to process the data and finally generate electronic component functional degradation data. When estimating the aging trend of electronic component functional degradation data, connection point failure data, and electronic component failure probability data, it is necessary to sort out various types of data and establish a multidimensional data model. Use time series analysis methods to analyze the relationship between functional degradation and connection point failure and time. Combined with historical failure data, the aging trend of electronic components under different environmental and operating conditions is predicted, and the estimated results are output. Finally, the aging trend data of electronic components is generated.

[0157] Preferably, step S4 comprises the following steps:

[0158] Step S41: estimating the life attenuation of electronic components according to the electronic component aging trend data and the electronic component failure probability data to obtain the electronic component life attenuation data;

[0159] Step S42: performing circuit board design defect analysis on the circuit board design data according to the electronic component life attenuation data and the electronic component aging trend data to obtain circuit board design defect data;

[0160] Step S43: optimizing the circuit board design data according to the circuit board design defect data and the electronic component failure probability data to obtain circuit board design optimization data;

[0161] Step S44: performing available performance enhancement calculation of electronic components according to the circuit board design optimization data to obtain available performance enhancement data of electronic components.

[0162] In an embodiment of the present invention, when estimating the life attenuation of electronic components based on the aging trend data of electronic components and the failure probability data of electronic components, it is first necessary to conduct an in-depth analysis of the aging trend of electronic components, including the performance change rate of components under different working environments. By recording the frequency of failures of components during long-term operation, statistical methods such as accelerated life testing are used to collect relevant data and build a life prediction model. Combined with the failure probability data, the life distribution model in reliability engineering, such as Weibull distribution or exponential distribution, is used to calculate the expected life attenuation value of the components, and finally generate the life attenuation data of electronic components. When analyzing the design defects of circuit boards based on the life attenuation data of electronic components and the aging trend data of electronic components, it is necessary to conduct a comprehensive review of the design data of the circuit board, combined with the service life of the components and their position in the circuit. By using the design failure mode and effects analysis (DFMEA) method, the factors that lead to accelerated aging of electronic components in the design, such as unreasonable power rail layout or insufficient thermal management, are evaluated. The life decay data is applied to the design review, the potential risks of design defects are identified and quantitatively analyzed, and finally the circuit board design defect data is output. When optimizing the design based on the circuit board design defect data and the electronic component failure probability data, the defect data should be collected, and the design should be comprehensively evaluated in combination with the failure mode of the electronic components. The wiring, component layout and thermal management of the circuit board are optimized by using computer-aided design (CAD) tools. The design defects are reviewed item by item, and the parametric design principle is applied to adjust the component spacing, improve the heat dissipation channel and optimize the power distribution. After the optimization is completed, the failure probability of each component is recalculated to generate the circuit board design optimization data. When the electronic component available performance enhancement calculation is performed based on the circuit board design optimization data, the impact of the optimized design on the component performance needs to be analyzed. The effect of the optimized design is evaluated by establishing performance evaluation indicators such as power loss, response time and operating temperature range. The circuit board is simulated using thermal simulation software to analyze the thermal distribution of the components under the new design. The performance indicators before and after optimization are compared to quantify the improvement of available performance. Finally, the electronic component available performance enhancement data is formed.

[0163] This specification also provides an electronic component for executing the above-mentioned electronic component fault management method, the electronic component comprising:

[0164] Circuit board cross wiring statistics module: obtain circuit board design data; perform circuit wiring analysis based on the circuit board design data to obtain circuit wiring data; perform cross wiring statistics on the circuit wiring data to obtain circuit board cross wiring data;

[0165] Short-circuit fault detection module: Perform electromagnetic radiation enhancement detection based on the cross-wiring data of the circuit board to obtain the cross-wiring electromagnetic radiation enhancement data; perform circuit fault probability calculation based on the circuit board cross-wiring data and the cross-wiring electromagnetic radiation enhancement data to obtain circuit fault probability data; perform electronic component short-circuit fault detection based on the circuit fault probability data to obtain electronic component short-circuit fault data;

[0166] Aging trend prediction module: calculate the electronic component failure probability based on the electronic component short-circuit failure data and circuit failure probability data to obtain the electronic component failure probability data; predict the electronic component aging trend based on the electronic component failure probability data and cross-wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data;

[0167] Available performance enhancement calculation module: based on the electronic component aging trend data and the electronic component failure probability data, the circuit board design data is optimized to obtain the circuit board design optimization data; based on the circuit board design optimization data, the available performance enhancement calculation of the electronic components is performed to obtain the available performance enhancement data of the electronic components.

[0168] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for fault management of electronic components, characterized in that: The following steps are involved: Step S1: Obtain circuit board design data; Perform circuit wiring analysis according to circuit board design data to obtain circuit wiring data; Perform cross-wiring statistics on circuit wiring data to obtain circuit board cross-wiring data; Step S2: Perform electromagnetic radiation enhancement detection according to the cross wiring data of the circuit board to obtain cross wiring electromagnetic radiation enhancement data; perform circuit fault probability calculation according to the cross wiring data of the circuit board and the cross wiring electromagnetic radiation enhancement data to obtain circuit fault probability data; Perform short-circuit fault detection on electronic components according to circuit fault probability data to obtain short-circuit fault data on electronic components; Step S3: Calculate the electronic component failure probability based on the electronic component short circuit failure data and the circuit failure probability data to obtain the electronic component failure probability data; and estimate the electronic component aging trend based on the electronic component failure probability data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data; Step S4: optimizing the circuit board design data according to the electronic component aging trend data and the electronic component failure probability data to obtain circuit board design optimization data; The available performance enhancement calculation of electronic components is performed according to the circuit board design optimization data to obtain the available performance enhancement data of the electronic components.

2. The electronic component fault management method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: obtaining circuit board design data; Step S12: collecting distribution information of electronic components according to the circuit board design data to obtain distribution information of electronic components; Step S13: performing circuit wiring analysis according to the electronic component distribution data and the circuit board design data to obtain circuit wiring data; Step S14: Perform cross-wiring statistics on the circuit wiring data and the electronic component distribution data to obtain circuit board cross-wiring data.

3. The electronic component fault management method according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: performing electromagnetic radiation enhancement detection according to the cross wiring data of the circuit board to obtain cross wiring electromagnetic radiation enhancement data; Step S22: performing circuit board design abnormality analysis according to the circuit board cross wiring data and the cross wiring electromagnetic radiation enhancement data to obtain circuit board design abnormality data; Step S23: Calculate the circuit failure probability according to the circuit board design abnormality data and the cross wiring electromagnetic radiation enhancement data to obtain circuit failure probability data; Step S24: performing electronic component short circuit fault detection according to the circuit fault probability data and the circuit board design abnormality data to obtain electronic component short circuit fault data.

4. The electronic component fault management method according to claim 3, characterized in that: Step S21 includes the following steps: Step S211: Calculate the circuit board loop area growth using the circuit board cross wiring data to obtain circuit board loop area growth data; Step S212: Calculating the circuit board route spacing according to the circuit board loop area growth data and the circuit board cross wiring data to obtain the circuit board route spacing data; Step S213: performing signal line crossing acquisition according to the circuit board cross wiring data to obtain circuit board signal line crossing data; Step S214: performing electromagnetic coupling effect enhancement calculation according to the circuit board signal line crossing data and the circuit board route spacing data to obtain circuit board electromagnetic coupling effect enhancement data; Step S215: Perform electromagnetic radiation enhancement detection according to the circuit board electromagnetic coupling effect enhancement data and the circuit board loop area growth data to obtain cross wiring electromagnetic radiation enhancement data.

5. The electronic component fault management method according to claim 3, characterized in that: Step S2 includes the following steps: Step S231: Calculate the signal phase offset according to the cross wiring electromagnetic radiation enhancement data to obtain circuit board signal phase offset data; Step S232: performing circuit board synchronization failure detection according to the circuit board signal phase offset data to obtain circuit board synchronization failure data; Step S233: Calculate the circuit board bit error rate growth by using the circuit board synchronization failure data and the circuit board signal phase offset data to obtain the circuit board bit error rate growth data; Step S234: performing power rail abnormality detection according to the circuit board design abnormality data to obtain the circuit board power rail abnormality data; Step S235: Calculating circuit board voltage fluctuation according to circuit board power rail abnormality data to obtain circuit board voltage fluctuation data; Step S236: Calculate the circuit failure probability based on the circuit board voltage fluctuation data and the circuit board bit error rate growth data to obtain circuit failure probability data.

6. The electronic component fault management method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: performing electronic component current detection on the electronic component short-circuit fault data to obtain electronic component short-circuit current data; Step S32: performing heat accumulation simulation of electronic components according to the short-circuit current data of the electronic components and the circuit failure probability data to obtain heat accumulation data of the electronic components; Step S33: Calculating the electronic component failure probability according to the electronic component current overload data and the electronic component heat accumulation data to obtain the electronic component failure probability data; Step S34: estimating the aging trend of electronic components according to the electronic component failure probability data, the electronic component heat accumulation data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data.

7. The electronic component fault management method according to claim 6, characterized in that: Step S32 includes the following steps: Step S321: Acquire rated current data of electronic components; Step S322: Calculating the frequency of occurrence of transient voltage on the circuit board based on the circuit failure probability data to obtain data on the frequency of occurrence of transient voltage on the circuit board; Step S323: Calculate the circuit board current surge based on the circuit board transient voltage frequency data and the electronic component short-circuit current data to obtain the electronic component current surge data; Step S324: performing current overload division on the rated current data of the electronic components according to the current surge data of the electronic components to obtain current overload data of the electronic components; Step S325: Calculating the growth of power loss of electronic components according to the current overload data of the electronic components to obtain the growth data of power loss of electronic components; Step S326: Detecting the continuous increase in component temperature based on the electronic component power loss growth data and the electronic component current surge data, and obtaining the electronic component temperature continuous increase data; Step S327: performing electronic component heat accumulation simulation on the electronic component temperature continuous increase data and the electronic component power loss growth data to obtain electronic component heat accumulation data.

8. The electronic component failure management method according to claim 6, characterized in that: Step S34 includes the following steps: Step S341: performing thermal expansion detection of electronic components according to heat accumulation data of electronic components to obtain thermal expansion data of electronic components; Step S342: Calculate the stress growth of the connection points according to the thermal expansion data of the electronic components to obtain the stress growth data of the connection points of the electronic components; Step S343: performing connection point failure prediction on the electronic component connection point stress growth data and the electronic component thermal expansion data to obtain connection point failure data; Step S344: estimating the electronic component function degradation according to the connection point failure data and the cross wiring electromagnetic radiation enhancement data to obtain the electronic component function degradation data; Step S345: estimating the aging trend of electronic components based on the electronic component function degradation data, the connection point failure data, and the electronic component failure probability data to obtain the electronic component aging trend data.

9. The electronic component failure management method according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: estimating the life attenuation of electronic components according to the electronic component aging trend data and the electronic component failure probability data to obtain the electronic component life attenuation data; Step S42: performing circuit board design defect analysis on the circuit board design data according to the electronic component life attenuation data and the electronic component aging trend data to obtain circuit board design defect data; Step S43: optimizing the circuit board design data according to the circuit board design defect data and the electronic component failure probability data to obtain circuit board design optimization data; Step S44: performing available performance enhancement calculation of electronic components according to the circuit board design optimization data to obtain available performance enhancement data of electronic components.

10. An electronic component, characterized in that: Used to execute the fault management method of the electronic component according to claim 1, the electronic component comprising: Circuit board cross wiring statistics module: obtain circuit board design data; perform circuit wiring analysis based on the circuit board design data to obtain circuit wiring data; perform cross wiring statistics on the circuit wiring data to obtain circuit board cross wiring data; Short-circuit fault detection module: Perform electromagnetic radiation enhancement detection based on the cross-wiring data of the circuit board to obtain the cross-wiring electromagnetic radiation enhancement data; perform circuit fault probability calculation based on the circuit board cross-wiring data and the cross-wiring electromagnetic radiation enhancement data to obtain circuit fault probability data; perform electronic component short-circuit fault detection based on the circuit fault probability data to obtain electronic component short-circuit fault data; Aging trend prediction module: calculate the electronic component failure probability based on the electronic component short-circuit failure data and circuit failure probability data to obtain the electronic component failure probability data; predict the electronic component aging trend based on the electronic component failure probability data and cross-wiring electromagnetic radiation enhancement data to obtain the electronic component aging trend data; Available performance enhancement calculation module: based on the electronic component aging trend data and the electronic component failure probability data, the circuit board design data is optimized to obtain the circuit board design optimization data; based on the circuit board design optimization data, the available performance enhancement calculation of the electronic components is performed to obtain the available performance enhancement data of the electronic components.

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