ESD circuit and chip
By designing an ESD circuit that includes a first -level discharge module and a secondary discharge module, the problem of insufficient communication uniformity of the transistor in the traditional ESD protection circuit is solved, and the more efficient static energy release and stronger chip protection capabilities are realized Essence
Patent Information
- Application Number
- CN202411715100.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-01-28
AI Technical Summary
The traditional ESD protection circuit has the problem of insufficient conductivity of at least some transistors, which affects the circuit performance.
A ESD circuit is designed, including the first -level discharge module and the secondary discharge module. The first -level discharge module provides a unit by discharging the MOS tube and bias signal to ensure that each discharge MOS tube is in a weak guide state when the electrostatic energy is leaked. The secondary discharge module further discharges the static energy at the pin of the chip pin and provides additional protection.
By opening the discharge MOS tube evenly, it improves the discharge of static energy, enhances the protection of chip -related structures, and solves the problem of insufficient uniformity of the traditional ESD protection circuit.
Smart Images
Figure CN119382486A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit technology, and in particular to an ESD circuit and a chip. Background Art
[0002] ESD (electrostatic discharge) protection is widely used in various fields that require stable operation of electronic equipment, especially in the electronics and electrical, IT and communications, and automotive industries. In the electronics industry, static electricity is one of the main causes of damage to electronic devices, so electrostatic protection measures are particularly important. ESD protection devices are widely used in various types of circuits, systems, and equipment, especially in highly integrated electronic devices. For example, in automotive electronic systems, due to the increase in chip integration and reduction in size, the sensitivity to ESD increases, so special attention needs to be paid to ESD protection. However, under many processes, traditional ESD protection circuits have problems such as insufficient conduction uniformity of at least some transistors, which affects the performance of the circuit. Summary of the invention
[0003] In view of this, the present application provides an ESD circuit and a chip to solve the problem of insufficient conduction uniformity of at least some transistors in conventional ESD protection circuits.
[0004] The present application provides an ESD circuit, the ESD circuit comprising a primary discharge module and a secondary discharge module; the primary discharge module comprises at least one discharge MOS tube, a bias signal providing unit and first resistors corresponding to each discharge MOS tube;
[0005] The drain of each of the discharge MOS tubes is connected to the chip pin, the gate is grounded through the corresponding first resistor, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit; the first end of the secondary discharge module is connected to the chip pin, and the second end is connected to the internal circuit of the chip;
[0006] The primary discharge module is used to discharge the electrostatic energy at the chip pins by connecting each of the discharge MOS tubes;
[0007] The secondary discharge module is used to further discharge the electrostatic energy at the chip pins;
[0008] The bias signal providing unit is used to provide a preset bias signal for each of the discharge MOS tubes, so that when the electrostatic energy passes through each of the discharge MOS tubes, each of the discharge MOS tubes is in a weak conduction state.
[0009] Optionally, the bias signal providing unit includes a Wilson current mirror and a nanoampere current branch; the nanoampere current branch is used to provide a nanoampere current; the input end of the Wilson current mirror is connected to the output end of the nanoampere current branch, and the output end serves as the signal providing end of the bias signal providing unit, connected to the substrate level of each of the discharge MOS tubes, for mirroring the nanoampere current, and providing the mirrored current as the preset bias signal to the substrate level of each of the discharge MOS tubes.
[0010] Optionally, the Wilson current mirror includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube; the source of the first MOS tube is connected to the chip pin, the drain is used as the output end of the Wilson current mirror, and the gate is respectively connected to the gate of the second MOS tube, the gate of the third MOS tube, the drain of the fourth MOS tube and the drain of the third MOS tube; the source of the second MOS tube and the source of the third MOS tube are respectively connected to the chip pin; the source of the fourth MOS tube is grounded, and the gate is respectively connected to the gate of the fifth MOS tube, the drain of the fifth MOS tube and the drain of the third MOS tube; the source of the fifth MOS tube is connected to the output end of the nanoampere current branch.
[0011] Optionally, the first MOS tube, the second MOS tube and the third MOS tube are PMOS tubes; the fourth MOS tube and the fifth MOS tube are NMOS tubes.
[0012] Optionally, the nanoampere current branch includes a second resistor; a first end of the second resistor serves as an output end of the nanoampere current branch, and a second end is grounded.
[0013] Optionally, the resistance of the second resistor is 100 MΩ.
[0014] Optionally, the secondary discharge module includes a third resistor and a jfet tube; the first end of the third resistor is connected to the chip pin, and the second end is connected to the source of the jfet tube; the gate of the jfet tube is respectively connected to the drain of the jfet tube and the internal circuit of the chip.
[0015] Optionally, the resistance range of the third resistor includes 1 kΩ-10 kΩ.
[0016] The present application also provides a chip, wherein the chip includes any one of the above-mentioned ESD circuits.
[0017] In the above-mentioned ESD circuit and chip of the present application, the bias signal providing unit can provide a preset bias signal for each discharge MOS tube, so that when the electrostatic energy is discharged through each discharge MOS tube, each discharge MOS tube is in a weak conduction state, so that when the ESD current passes through the discharge MOS tube, the discharge MOS tube can be evenly turned on to improve the discharge capacity of each discharge MOS tube; in addition, the secondary discharge module can further discharge the electrostatic energy at the chip pin when the energy discharge of the primary discharge module is incomplete, and protect the chip-related structure again, thereby strengthening the protection capacity of the chip-related structure. The above-mentioned ESD circuit can enhance the electrostatic discharge capacity from many aspects, thereby improving the protection capacity of the chip-related structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1 is a schematic diagram of the ESD circuit structure of an embodiment of the present application;
[0020] Figure 2 This is a schematic diagram of a discharge MOS tube according to an embodiment of the present application;
[0021] Figure 3 is a schematic diagram of the ESD circuit structure of another embodiment of the present application;
[0022] Figure 4 It is a schematic diagram of the ESD circuit structure of another embodiment of the present application. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0024] In a first aspect, the present application provides an ESD circuit, which is provided in a chip that needs electrostatic discharge protection. Figure 1As shown, the ESD circuit includes a primary discharge module 100 and a secondary discharge module 200; the primary discharge module 100 includes at least one discharge MOS tube N1, a bias signal providing unit 111 and first resistors R1 corresponding to each discharge MOS tube N1.
[0025] The drain of each discharge MOS tube N1 is connected to the chip pin PAD, the gate is grounded through the corresponding first resistor R1, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit 111. The first end of the secondary discharge module 200 is connected to the chip pin PAD, and the second end is connected to the internal circuit of the chip.
[0026] Optionally, the discharge MOS transistor N1 may be a P-substrate NMOS transistor, and its transistor structure may refer to Figure 2 Specifically, the discharge MOS tube N1 may include one discharge MOS tube, or may include multiple discharge MOS tubes, and the connection characteristics of each discharge MOS tube are consistent; for example, refer to Figure 3 As shown, the discharge MOS tube N1 includes a discharge MOS tube ESD1, the drain of the discharge MOS tube ESD1 is connected to the chip pin PAD, the gate is grounded through the first resistor R1, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit 111; for example, referring to Figure 4 As shown, the discharge MOS tube N1 includes n discharge MOS tubes, namely ESD1 to ESDn. The drain of each discharge MOS tube ESD1 is connected to the chip pin PAD, the gate is grounded through the corresponding first resistor R1, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit 111.
[0027] The primary discharge module 100 is used to discharge the electrostatic energy at the chip pin PAD by connecting each of the discharge MOS tubes N1.
[0028] The secondary discharge module 200 is used to further discharge the electrostatic energy at the chip pin PAD, so as to protect the chip-related structures again when the energy discharge of the primary discharge module 100 is incomplete, thereby enhancing the protection capability of the chip-related structures. Optionally, the secondary discharge module 200 can also clamp the voltage of its second end to below a preset voltage, that is, clamp the voltage input to the internal circuit of the chip to below a preset voltage, so as to enhance the protection function of the internal circuit of the chip. Optionally, the preset voltage can be set to a voltage value such as 5V.
[0029] The bias signal providing unit 110 is used to provide a preset bias signal for each of the discharge MOS tubes N1, so that when the electrostatic energy passes through each of the discharge MOS tubes N1, each of the discharge MOS tubes N1 is in a weak conduction state. In this way, when the ESD current passes through the discharge MOS tube N1, the discharge MOS tube N1 can be evenly turned on to improve the discharge capacity of each discharge MOS tube N1.
[0030] Optionally, the preset bias signal includes a bias voltage. The bias signal providing unit 110 can provide a small bias voltage, and the value range of the bias voltage is 0.6V-1V, for example, the preset bias signal can be 0.6V, 0.7V or 1V, etc. A preset bias signal is provided to the substrate of each discharge MOS tube N1, that is, a preset bias signal is provided to the parasitic diode of each discharge MOS tube N1, so that each discharge MOS tube N1 is in a weak conduction state, so that when the ESD current passes through each discharge MOS tube N1, each discharge MOS tube N1 can be evenly turned on, and the electrostatic energy discharge capability is improved.
[0031] In the above-mentioned ESD circuit, the bias signal providing unit 110 is used to provide a preset bias signal for each discharge MOS tube N1, so that when the electrostatic energy is discharged through each discharge MOS tube N1, each discharge MOS tube N1 is in a weak conduction state, so that when the ESD current passes through the discharge MOS tube N1, the discharge MOS tube N1 can be evenly turned on to improve the discharge capacity of each discharge MOS tube N1; in addition, the secondary discharge module 200 can further discharge the electrostatic energy at the chip pin when the energy discharge of the primary discharge module 100 is incomplete, and protect the chip-related structure again, thereby enhancing the protection capacity of the chip-related structure. The above-mentioned ESD circuit can enhance the electrostatic discharge capacity from many aspects, thereby improving the protection capacity of the chip-related structure.
[0032] In some embodiments, reference Figure 3 As shown, the bias signal providing unit 110 includes a Wilson current mirror 111 and a nanoampere-level current branch 112 .
[0033] The nanoampere current branch 112 is used to provide nanoampere current.
[0034] The input end of the Wilson current mirror 111 is connected to the output end of the nanoampere current branch 112, and the output end serves as the signal providing end of the bias signal providing unit 111, and is connected to the substrate level of each of the discharge MOS tubes N1, so as to perform mirror processing on the nanoampere current, and provide the mirrored current as the preset bias signal to the substrate level of each of the discharge MOS tubes N1, so that when the ESD current flows through the discharge MOS tube N1, each of the discharge MOS tubes N1 is in a weak conduction state.
[0035] This embodiment uses the Wilson current mirror 111 to perform mirror processing on the nanoampere level current, which can improve the linearity and reliability during the mirror processing, so as to provide a more stable and reliable small current signal or small voltage signal to the substrate level of the discharge MOS tube N1.
[0036] In some examples, the Wilson current mirror 111 includes a first MOS transistor P1, a second MOS transistor P2, a third MOS transistor P3, a fourth MOS transistor N2, and a fifth MOS transistor N3. Specifically, the first MOS transistor P1, the second MOS transistor P2, and the third MOS transistor P3 are PMOS transistors; the fourth MOS transistor N2 and the fifth MOS transistor N3 are NMOS transistors.
[0037] The source of the first MOS transistor P1 is connected to the chip pin PAD, the drain is used as the output end of the Wilson current mirror 111, and the gate is respectively connected to the gate of the second MOS transistor P2, the gate of the third MOS transistor P3, the drain of the fourth MOS transistor N2 and the drain of the third MOS transistor P3. The source of the second MOS transistor P2 and the source of the third MOS transistor P3 are respectively connected to the chip pin PAD. The source of the fourth MOS transistor N2 is grounded, and the gate is respectively connected to the gate of the fifth MOS transistor N3, the drain of the fifth MOS transistor N3 and the drain of the third MOS transistor P3. The source of the fifth MOS transistor N3 is connected to the output end of the nanoampere current branch 112.
[0038] Specifically, the nanoampere current branch 112 includes a second resistor R2; a first end of the second resistor R2 serves as an output end of the nanoampere current branch 112, and a second end is grounded.
[0039] Optionally, the resistance of the second resistor R2 is 100 MΩ, so that the current passing through the second resistor R2 is a nanoampere level current.
[0040] In this example, the resistance of the second resistor R2 is set to 100 MΩ, thereby providing a nA-level current branch, and using the Wilson current mirror 111 to provide a small bias voltage (such as 0.7 V) to the parasitic diode of the discharge MOS tube N1, so that the discharge MOS tube N1 is in a weak conduction state.
[0041] In some embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the secondary discharge module 200 includes a third resistor R3 and a jfet (junction field effect transistor) tube Jfet (also called jfetmos tube). Optionally, the jfet tube Jfet can be an N-type transistor.
[0042] The first end of the third resistor R3 is used as the first end of the secondary discharge module 200, connected to the chip pin, and the second end of the third resistor R3 is used as the second end of the secondary discharge module 200, connected to the source of the jfet tube Jfet. The gate of the jfet tube Jfet is respectively connected to the drain of the jfet tube Jfet and the internal circuit of the chip.
[0043] Optionally, the resistance range of the third resistor R3 includes 1 kΩ-10 kΩ.
[0044] In this embodiment, the secondary discharge module 200 can utilize the pinch-off characteristics of the jfet tube Jfet to pinch off the voltage near the internal circuit end of the chip to below 5V, thereby protecting the internal circuit of the chip from being affected, further improving the protection capability of the secondary discharge module 200.
[0045] In the above ESD circuit, the bias signal providing unit 110 is used to provide a preset bias signal for each discharge MOS tube N1, so that when the electrostatic energy is discharged through each discharge MOS tube N1, each discharge MOS tube N1 is in a weak conduction state, so that when the ESD current passes through the discharge MOS tube N1, the discharge MOS tube N1 can be evenly turned on to improve the discharge capacity of each discharge MOS tube N1; in addition, the secondary discharge module 200 can further discharge the electrostatic energy at the chip pin when the energy discharge of the primary discharge module 100 is incomplete, and protect the chip-related structure again, thereby strengthening the protection capacity of the chip-related structure; and the secondary discharge module 200 can use the pinch-off characteristics of the jfet tube Jfet to pinch off the voltage near the internal circuit end of the chip to below 5V, thereby protecting the internal circuit of the chip from being affected, and further improving the protection capacity of the secondary discharge module 200. The above ESD circuit can improve the protection capacity of the chip-related structure from many aspects.
[0046] The second aspect of the present application provides a chip, which includes at least one ESD circuit described in any of the above embodiments. Specifically, the ESD circuit can be located at the pins that need electrostatic discharge protection in the chip, and each pin that needs electrostatic discharge protection can be provided with an ESD circuit.
[0047] The above chip includes the ESD circuit described in any of the above embodiments, and has all the beneficial effects of the ESD circuit described in any of the above embodiments, which will not be described in detail here.
[0048] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding of this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementation of this specification shown herein.
[0049] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
[0050] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0051] In this application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the present application provides the above description. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.
Claims
1. An ESD circuit, characterized in that: The ESD circuit includes a primary discharge module and a secondary discharge module; the primary discharge module includes at least one discharge MOS tube, a bias signal providing unit and first resistors corresponding to each discharge MOS tube; The drain of each of the discharge MOS tubes is connected to the chip pin, the gate is grounded through the corresponding first resistor, the source is grounded, and the substrate is connected to the signal providing end of the bias signal providing unit; the first end of the secondary discharge module is connected to the chip pin, and the second end is connected to the internal circuit of the chip; The primary discharge module is used to discharge the electrostatic energy at the chip pins by connecting each of the discharge MOS tubes; The secondary discharge module is used to further discharge the electrostatic energy at the chip pins; The bias signal providing unit is used to provide a preset bias signal for each of the discharge MOS tubes, so that when the electrostatic energy passes through each of the discharge MOS tubes, each of the discharge MOS tubes is in a weak conduction state.
2. The ESD circuit according to claim 1, characterized in that: The bias signal providing unit includes a Wilson current mirror and a nanoampere current branch; The nanoampere current branch is used to provide nanoampere current; The input end of the Wilson current mirror is connected to the output end of the nanoampere current branch, and the output end serves as the signal providing end of the bias signal providing unit, connected to the substrate level of each of the discharge MOS tubes, for mirroring the nanoampere current, and providing the mirrored current as the preset bias signal to the substrate level of each of the discharge MOS tubes.
3. The ESD circuit according to claim 2, characterized in that: The Wilson current mirror comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube; The source of the first MOS tube is connected to the chip pin, the drain is used as the output end of the Wilson current mirror, and the gate is respectively connected to the gate of the second MOS tube, the gate of the third MOS tube, the drain of the fourth MOS tube and the drain of the third MOS tube; The source of the second MOS tube and the source of the third MOS tube are respectively connected to the chip pins; the source of the fourth MOS tube is grounded, and the gate is respectively connected to the gate of the fifth MOS tube, the drain of the fifth MOS tube and the drain of the third MOS tube; the source of the fifth MOS tube is connected to the output end of the nanoampere current branch.
4. The ESD circuit according to claim 3, characterized in that: The first MOS tube, the second MOS tube and the third MOS tube are PMOS tubes; the fourth MOS tube and the fifth MOS tube are NMOS tubes.
5. The ESD circuit according to claim 2, characterized in that: The nanoampere-level current branch includes a second resistor; The first end of the second resistor serves as the output end of the nanoampere level current branch, and the second end is grounded.
6. The ESD circuit according to claim 5, characterized in that: The resistance of the second resistor is 100 MΩ.
7. The ESD circuit according to claim 1, characterized in that: The secondary discharge module includes a third resistor and a jfet tube; The first end of the third resistor is connected to the chip pin, and the second end is connected to the source of the jfet tube; the gate of the jfet tube is respectively connected to the drain of the jfet tube and the internal circuit of the chip.
8. The ESD circuit according to claim 7, characterized in that: The resistance value of the third resistor ranges from 1 kΩ to 10 kΩ.
9. A chip, characterized in that: The chip comprises at least one ESD circuit according to any one of claims 1 to 8.