Generative heterogeneous logic optimization method based on critical path partitioning

Abstract

The present invention discloses a generative heterogeneous logic optimization method based on critical path partitioning. The method of the present invention comprises: firstly, converting a digital logic circuit into an AIG graph format, and using reinforcement learning to partition the AIG graph according to the critical path information of the circuit itself to obtain critical path-aware partitions to reduce the impact of partitioning on the timing performance caused by changes in the critical path; using the reinforcement learning method to automatically explore the optimized structure and optimized comprehensive flow suitable for the partition after the partition, and the reinforcement learning intelligent agent selects various structural optimization operators to optimize the partitions based on area delay; and merging the optimized partitions in the form of AIG. The present invention partitions the digital logic circuit for the critical path and uses reinforcement learning to explore the optimized structure and strategy based on area delay, thereby reducing the impact of the partition on the timing performance and jumping out of the local optimal solution to obtain a better global solution. At the same time, automatic exploration without manual intervention can reduce the labor cost in chip design.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic design automation, and in particular is a generative heterogeneous logic optimization method based on critical path partitioning. Background Art

[0002] In the context of increasingly complex chip structures, if the logic optimization stage in the chip design process can be optimized efficiently and targetedly, it will inevitably lead to a chip with a smaller area and lower optimization. Among them, the segmentation of various chip structural areas and the selection of logic synthesis structure have the greatest impact on the chip area delay and power consumption after logic optimization. Reasonable circuit segmentation methods can greatly reduce the impact on the timing performance of the chip itself, and targeted logic optimization processes can directly improve the performance of the chip's final area delay and power consumption.

[0003] Current logic optimization methods have defects. They usually adopt a single structure or heterogeneous but fixed optimization process. These methods do not deal with the heterogeneous characteristics of chips and do not fully explore the optimization space. Traditional circuit partitioning algorithms use traditional graph partitioning algorithms, which only contain circuit topology information but lack other information about the circuit itself; traditional logic optimization algorithms use fixed optimization processes and cannot target different circuit structures. Due to the large scale and complex structure of modern chips, traditional logic optimization methods cannot effectively handle them. Therefore, a graph partitioning algorithm that considers circuit information is urgently needed to divide the circuit and generate different optimization processes according to different partition structures for circuit logic optimization. Summary of the invention

[0004] The purpose of the present invention is to solve the problem that the traditional partitioning method lacks circuit information and the logic optimization cannot fully explore the optimization space. A generative heterogeneous logic optimization method based on critical path partitioning is provided. The method converts the digital logic circuit into the AIG graph format, and uses reinforcement learning to partition the AIG graph according to the critical path information of the circuit itself, and obtains the critical path-aware partition to reduce the change of the critical path caused by the partition and affect the timing performance; the partitioned circuit is automatically explored by the reinforcement learning method for the optimization structure and optimization synthesis flow suitable for the partition, and the reinforcement learning agent selects the most suitable optimization operator to optimize the partition with area and delay as the guide; the optimized partitions are merged in the form of AIG. The present invention partitions the digital logic circuit for the critical path and uses reinforcement learning to explore the optimization structure and strategy with area and delay as the guide, reduces the impact of the partition on the timing performance and jumps out of the local optimal solution to obtain a global better solution. At the same time, the automatic exploration can reduce the labor cost in chip design without manual intervention.

[0005] To solve the above problems, the present invention provides a generative heterogeneous logic optimization method based on critical path partitioning, comprising the following steps:

[0006] Step S1: construct a reinforcement learning partitioning agent model for the critical path of the digital logic circuit;

[0007] Step S2: partitioning the digital logic circuit by using a reinforcement learning graph partitioning agent model for a critical path of the digital circuit to obtain a plurality of partitioned circuits;

[0008] Step S3: multiple partitioned circuits automatically perform optimization space exploration using a reinforcement learning optimization model to obtain multiple optimized partitioned circuits;

[0009] Step S4: merging the optimized partitioned circuits to obtain the final optimization result.

[0010] In one implementation manner, step S1 specifically comprises:

[0011] S101: Constructing digital logic circuits

[0012] Obtain different digital logic circuits and construct a data set;

[0013] The digital logic circuits in the data set are converted into the AIG graph format to obtain the digital logic circuit transfer graph; according to the logic function description in the original digital logic circuit, its logic function is simplified into "logical AND" and "logical NOT" operations, which are represented by nodes and edges in the digital logic circuit transfer graph, that is, each node represents the "logical AND" function, and each edge represents the connection relationship between nodes. At the same time, the edge represents the "logical NOT" function when flipped, so as to realize the logic function of the digital circuit;

[0014] S102: Mark the critical path of the circuit:

[0015] Marking the circuit critical path on the digital logic circuit transfer diagram obtained in step S101; wherein the circuit critical path is the path with the longest delay in the digital logic circuit, that is, the path with the most levels in the digital logic circuit transfer diagram;

[0016] Then, all the critical path nodes are found on the digital logic circuit transfer diagram obtained in step S101, and the edges between these nodes are marked as critical paths, and finally a circuit representation diagram to be partitioned with critical path information is obtained;

[0017] The circuit critical path is obtained specifically by performing a depth-first search on all POs in the digital logic circuit, traversing the child nodes of each node in all paths under the PO, and if the child node is not a basic input PI and the level number is the level number of the parent node minus 1, it means that the child node belongs to the circuit critical path, otherwise it is considered that the child node does not belong to the circuit critical path, until all the critical path nodes are obtained;

[0018] S103: Training partition model:

[0019] The reinforcement learning A2C model is used to partition the circuit representation graph with key path information and calculate the single-step partition reward function. Update model parameters;

[0020] Single-step loss function during reinforcement learning A2C model training for:

[0021] Formula (1)

[0022] Formula (2)

[0023] in represents the model parameters, express Moment diagram status, represents the action chosen at time t, express exist The probability distribution under express Estimated value, represents the loss coefficient, 0< ≤1 is used to stabilize the training process; represents the discount factor, express The single-step reward function at the moment;

[0024] Single-step reward function at time t after introducing the circuit critical path for:

[0025] Formula (3)

[0026] Formula (4)

[0027] Formula (5)

[0028] in The state of the graph after executing a single-step partition operation. is the critical path factor; The number of times the critical path of the current partition operation is cut; is the partition normalization function; G is the graph state after partitioning, V 1 -V n represents partition 1 to partition n, vol is the capacity function of the partition, The function is the number of edges cut by the statistical partition; Q∈[1,n], deg(v) function is the degree function of the node;

[0029] S104: Repeat steps S101 to S103 for all digital logic circuits in the data set until the reinforcement learning A2C model converges, and obtains a reinforcement learning partitioning agent model for the critical path of the circuit.

[0030] In one embodiment, step 2 comprises the following sub-steps:

[0031] S201: Partition the digital logic circuit:

[0032] The digital logic circuit to be partitioned is converted into the AIG graph format, and then input into the trained reinforcement learning graph partitioning agent model for partitioning to obtain the graph partitioning information with critical paths;

[0033] S202: Partitioning the digital logic circuit:

[0034] Convert the graph partition information into node partition information, and then partition the original digital logic circuit;

[0035] Then, for each partition, each node of the original digital logic circuit is traversed, and a partition circuit is constructed according to the partition information of each node, specifically: if the current node itself is the PI or PO of the original digital logic circuit, it is added as a PI or PO in the partition circuit; if the current node is not a PI or PO and the fan-in node of the current node belongs to the partition of the current node, the current node is added to the partition circuit; if the current node is not a PI or PO and the fan-in node of the current node does not belong to the partition of the current node, the fan-in node of the current node is added as a PI in the partition circuit; if the current node is not a PI or PO and the fan-out node of the current node does not belong to the partition of the current node, the fan-out node of the current node is added as a PO in the new partition circuit; if the current node is not a PI or PO and the fan-out node of the current node belongs to the partition of the current node, the current node is added to the partition circuit.

[0036] In one embodiment, step 3 comprises the following sub-steps:

[0037] S301: Initialization:

[0038] Initialize each partition circuit, determine the optimization environment, and set the exploration iteration length;

[0039] S302: Optimization operator selection:

[0040] Extract the features of the partitioned circuit, pass the results of the normalized features of the partitioned circuit and the historical data of multiple optimization operators into the reinforcement learning A2C model, and obtain the most suitable optimization operator for the current partitioned circuit;

[0041] The characteristics of the partitioned circuit include the number of nodes and edges of the digital logic circuit conversion graph, the number of levels of the AIG graph corresponding to the circuit, the number of latches, the proportion of "logical AND" gates and "logical NOT" gates, the maximum fan-in and fan-out of the digital logic circuit after process mapping, and the average fan-in and fan-out of the logic nodes;

[0042] S303: Partition circuit optimization:

[0043] According to the selected optimization operator, the partition circuit is optimized, and the single-step optimization reward function is calculated to update the reinforcement learning optimization model;

[0044] The single-step optimization reward function used in the exploration process is:

[0045] Formula (6)

[0046] Formula (7)

[0047] in and They are the delay and area of ​​the partitioned circuit after process mapping under the specified process library. is the weight coefficient, which is used to adjust the model's pertinence to the optimization target; represents the circuit state at time k, Indicates the number of iterations;

[0048] S304: Repeat steps S302-S303 until the maximum number of iterations is reached, and finally multiple optimized partition circuits are obtained.

[0049] In one implementation manner, the step S4 is specifically:

[0050] According to the original node partition information, traverse the PO of each optimized partition circuit to determine whether the PO is the PO of the original digital logic circuit. If so, add the PO to the merged circuit. If not, it means that the PO is an internal node in the original digital logic circuit, and add the internal node to the merged circuit.

[0051] Traverse the internal nodes of each optimized partition circuit and add corresponding internal nodes to the merged circuit;

[0052] Traverse the PI of each optimized partition circuit to determine whether the PI is the PI of the original digital logic circuit. If so, add the PI to the merged circuit; if not, it means that the PI is an internal node in the original digital logic circuit, and add the internal node to the merged circuit.

[0053] The beneficial effects of the present invention are:

[0054] The generative heterogeneous logic optimization method based on critical path partitioning provided by the present invention, on the one hand, partitions the original circuit according to the reinforcement learning model for the critical path partitioning of the digital logic circuit obtained through digital logic circuit training to adapt to the multi-heterogeneous characteristics of modern chip design; on the other hand, the optimization space is automatically explored through the reinforcement learning optimization model. Different from the fixed process of traditional logic optimization, the present invention conducts a deeper level of area- and delay-oriented optimization space exploration, and does not need to rely on the optimization experience of R&D personnel, so as to obtain a better digital logic circuit at a lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is a flow chart of the generative heterogeneous logic optimization method based on critical path partitioning provided by the present invention.

[0056] Figure 2 This is a flowchart of the sub-steps of S1 in the generative heterogeneous logic optimization method based on critical path partitioning provided by the present invention.

[0057] Figure 3 This is a flowchart of the sub-steps of S2 in the generative heterogeneous logic optimization method based on critical path partitioning provided by the present invention.

[0058] Figure 4 This is a flowchart of the sub-steps of S3 in the generative heterogeneous logic optimization method based on critical path partitioning provided by the present invention.

[0059] FIG. 5 is a schematic diagram of the conversion between circuit and AIG graph structures in the generative heterogeneous logic optimization method based on critical path partitioning provided by the present invention.

[0060] FIG. 6 ( a ) is a schematic diagram of a circuit partitioning method in the generative heterogeneous logic optimization method based on critical path partitioning provided by the present invention.

[0061] FIG. 6 ( b ) is another schematic diagram of circuit partitioning in the generative heterogeneous logic optimization method based on critical path partitioning provided by the present invention. DETAILED DESCRIPTION

[0062] The principles and features of the generative heterogeneous logic optimization method based on critical path partitioning proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention, and are not used to limit the scope of the present invention. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0063] The present invention provides a generative heterogeneous logic optimization method based on critical path partitioning, and its solution flow chart is as follows: Figure 1 As shown, the generative heterogeneous logic optimization method based on critical path partitioning includes S1, S2, S3, and S4. The specific implementation of the present invention is described in detail below.

[0064] The present invention uses a reinforcement learning method to partition the circuit representation diagram to be partitioned based on the reinforcement learning A2C model, and optimizes the spatial exploration of the partitioned circuit. The A2C model is a deformation of the A3C model proposed by the Google DeepMind team at the 2016 ICML conference, and belongs to the prior art. The model consists of a critic network and an actor network, and updates the policy gradient through the advantage function. The model can better complete the digital logic circuit partition and optimization space exploration tasks through the design and adjustment of the reward function and the loss function.

[0065] A generative heterogeneous logic optimization method based on critical path partitioning specifically includes the following steps:

[0066] S1: Building a reinforcement learning partitioning model for critical paths in digital logic circuits

[0067] Construct a reinforcement learning graph partitioning model for digital logic circuits; the training data set is a Verilog file describing the digital logic circuit, which is converted into a graph format and then partitioned by a reinforcement learning agent for critical path partitioning, the partitioning quality is measured, and the model parameters are updated according to the partitioning results;

[0068] The step S1 includes the following sub-steps, and its flow chart is as follows Figure 2 As shown:

[0069] S101: Digital logic circuit diagram:

[0070] Obtain different digital logic circuits and construct a data set;

[0071] The digital logic circuits in the data set are converted into the AIG graph format to obtain the digital logic circuit conversion graph, which is recorded as the AIG graph; according to the logic function description in the original digital logic circuit, its logic function is simplified into "logical AND" and "logical NOT" operations, which are represented by nodes and edges in the AIG graph, that is, each node represents the "logical AND" function, and each edge represents the connection relationship between nodes. At the same time, the edge represents the "logical NOT" function when it is flipped, so as to realize the logic function of the digital circuit;

[0072] Figure 5 A schematic diagram of converting a circuit into an AIG diagram format is shown. Each node in the AIG diagram implements logic and functions, and each edge represents a connection relationship, where a solid line is a direct connection and a dotted line represents a logical flip connection;

[0073] In this embodiment, the open source tool abc is used to convert the Verilog file describing the digital logic circuit into the aiger text format, and then the python package pyaig and networks are used to generate the corresponding aig graph according to the node connection relationship and edge information described in the aiger text file;

[0074] S102: Mark the critical path of the circuit:

[0075] Mark the circuit critical path onto the graph obtained in step S101; wherein the circuit critical path is the path with the longest delay in the digital logic circuit, that is, the path with the most levels in the AIG graph;

[0076] The circuit critical path is obtained specifically by performing a depth-first search on all primary outputs (PO) in the digital logic circuit, traversing the child nodes of each node in all paths under the PO, and if the child node is not a primary input (PI) and the level number is the level number of the parent node minus 1, it means that the child node belongs to the critical path, otherwise it is considered that the child node does not belong to the critical path, until all the critical path nodes are obtained;

[0077] Then, corresponding nodes are found on the graph obtained in step S101 for all the critical path nodes, and the edges between these nodes are marked as critical paths, and finally a representation graph of the circuit to be partitioned with critical path information is obtained;

[0078] S103: Training partition model:

[0079] The reinforcement learning A2C model is used to partition the circuit representation graph with key path information and calculate the single-step partition reward function. Update the model parameters to obtain the required reinforcement learning partition model;

[0080] By introducing the critical path factor into the reward function of model training, the partition model considers the critical path of the circuit when performing the partition operation, so that the partition operation cuts the critical path as little as possible;

[0081] The partitioning operation is specifically as follows: in the initial state, all nodes in the graph obtained in step S101 are in the same partition, such as partition No. 0, and a strategy is calculated by the reinforcement learning partition model, and sampling is performed according to the strategy to re-determine the partition of each node, that is, a new partition number is assigned; after obtaining the node partition data, the reinforcement learning partition loss function is calculated for model parameter update;

[0082] The single-step loss function L in the reinforcement learning partition model training process is:

[0083]

[0084] in represents the model parameters, express Moment diagram status, represents the action chosen at time t, express exist The probability distribution under express Estimated value, Represents the loss coefficient, 0< ≤1 is used to stabilize the training process. Set to 0.1;

[0085] Represents the cumulative reward function, specifically:

[0086]

[0087] in represents the discount factor. If it is close to 0, then we have a "short-sighted" view of the training process, while if it is close to 1, actions that occur further in time are also relevant to the calculation of the reward. In this example, Set to 1, indicating that the reward of a single step is independent of time. express The single-step reward function at the moment;

[0088] Single-step reward function at time t after introducing the circuit critical path for:

[0089]

[0090]

[0091]

[0092] in is the current graph state; The state of the graph after executing a single-step partition operation; is the critical path factor, 1< ≤1; The number of times the critical path is cut for this partition operation, that is, whether the partition node and its edge are nodes and edges on the critical path; is the partition normalization function, which is used to define the partition quality; G is the graph state after partitioning, V 1 -V n represents partition 1 to partition n, vol is the capacity function of the partition, The function is to count the number of edges cut by the partition; Q∈[1,n], v is the number of edges belonging to VQ For partitioned nodes, the deg(v) function is the degree function of the node, that is, the number of all edges connected to the node is counted;

[0093] S104: Repeat steps S101 to S103 for all digital logic circuits in the data set until the reinforcement learning partitioning model converges, and obtains a partitioning agent model for the critical path of the circuit.

[0094] S2: partition the original digital logic circuit through a reinforcement learning graph partitioning agent model targeting the critical path of the digital circuit;

[0095] The step 2 includes the following sub-steps, and its flow chart is as follows Figure 3 As shown:

[0096] S201: Partition the digital logic circuit:

[0097] The digital logic circuit to be partitioned is converted into the AIG graph format, and then input into the trained reinforcement learning graph partitioning model for partitioning to obtain the graph partitioning information with critical paths;

[0098] S202: Partitioning the digital logic circuit:

[0099] Convert the graph partition information into node partition information, and then perform circuit partitioning on the original digital logic circuit to be partitioned;

[0100] The partition information of the nodes in the graph partition is stored in text format. The storage method is as follows: the partition information is stored according to the node order. For example, if the first node is the second partition, the first line of the text is 2; if the eighth node is the zeroth partition, the eighth line of the text is 0. The above operation is performed on all nodes of the AIG graph converted from the logic circuit to obtain the partition text.

[0101] Then read the partition text, traverse each node of the original digital logic circuit for each partition, and build a partition circuit according to the partition information of each node of the circuit, specifically: if the node itself is the PI or PO of the original circuit, add it as PI or PO in the partition circuit; if the node is not PI or PO and the fan-in node of the node belongs to the partition of the node, add the node to the partition circuit; if the node is not PI or PO and the fan-in node of the node does not belong to the partition of the node, add the fan-in node as PI in the partition circuit; if the node is not PI or PO and the fan-out node of the node does not belong to the partition of the node, add the fan-out node as PO in the new partition circuit; if the node is not PI or PO and the fan-out node of the node belongs to the partition of the node, add the node to the partition circuit.

[0102] S3: The partitioned circuit automatically explores the optimization space through the reinforcement learning exploration model;

[0103] In the step S3: traditional optimization schemes often use a single structure for optimization, and only exploring the optimization space of a single structure cannot optimize the circuit in detail; after the single-step optimization, the circuit structure changes, and the current optimization operator and optimization structure are not suitable for the structure after the circuit optimization, so a larger optimization space is introduced, and the optimization space includes 4 circuit representations, namely: AIG (And Inverter Graphs), MIG (Majority Inverter Graphs), XAG (Xor-AndGraphs) and XMG (Xor-Majority Graphs), and multiple optimization operators under the above four circuit representations, namely: rewrite, rewrite-z with zero gain, extraction refactor, extraction refactor-z with zero gain, substitution resub and balance;

[0104] The step 3 includes the following sub-steps, and its flow chart is as follows Figure 4 As shown:

[0105] S301: Initialization:

[0106] Initialize each partition circuit, determine the optimization environment, which includes the process library, timing constraints, and set the exploration iteration length;

[0107] S302: Optimization operator selection:

[0108] Extract the features of the partitioned circuit, pass the results of the normalized features of the partitioned circuit and the historical data of multiple optimization operators into the reinforcement learning A2C model, and obtain the most suitable optimization operator for the current partitioned circuit;

[0109] The characteristics of the partitioned circuit include the number of nodes and edges after the circuit is converted into a graph, the number of levels of the AIG graph corresponding to the circuit, the number of latches in the circuit, the proportion of "logical AND" gates and "logical NOT" gates in the circuit, the maximum fan-in and fan-out of the digital logic circuit after process mapping, and the average fan-in and fan-out of the logic nodes;

[0110] The partition feature extraction uses the stat command of the open source tool yosys and the print_stats command of the open source tool abc; the process mapping uses the map command of the open source tool abc;

[0111] S303: Partition circuit optimization:

[0112] According to the selected optimization operator, the partition circuit is optimized, and the single-step optimization reward function is calculated to update the reinforcement learning optimization model;

[0113] If the optimization operator belongs to a different structure, the circuit structure needs to be transformed. The transformation is performed using the open source tool mockturtle developed by EPFL.

[0114] The single-step optimization reward function used in the exploration process is:

[0115]

[0116]

[0117] in and They are respectively the delay and area of ​​the circuit after process mapping under the specified process library. is the weight coefficient, which is used to adjust the model's pertinence to the optimization target; represents the circuit state at time k, Indicates the number of iterations. The process mapping step is implemented using the map command of the open source tool abc;

[0118] S304: repeating steps S302-S303 until the maximum number of iterations is reached, and finally obtaining multiple optimized partition circuits;

[0119] Figure 6 The schematic diagram shows two different partitions of the same digital circuit. The partitioning method in Figure 6 (a) does not cut the critical path, while the critical path in the partitioning method in Figure 6 (a) is cut three times. The number of critical path cuts in the reward function is That is equal to .

[0120] In the step S4: according to the original node partition information, traverse the PO of each optimized partition circuit to determine whether the PO is the PO of the original digital logic circuit. If so, add the PO to the merged circuit. If not, it means that the PO is an internal node in the original circuit, and add the internal node to the merged circuit.

[0121] Traverse the internal nodes of each optimized partition circuit and add corresponding internal nodes to the merged circuit;

[0122] Traverse the PI of each optimized partition circuit to determine whether the PI is the PI of the original digital logic circuit. If so, add the PI to the merged circuit; if not, it means that the PI is an internal node in the original circuit, and add the internal node to the merged circuit;

[0123] According to the original partition information, traverse the PO of each optimized partition circuit to determine whether the PO is the PO of the original digital logic circuit. If so, add the PO to the merged circuit. If not, it means that the PO is an internal node in the original circuit, and add the internal node to the merged circuit.

[0124] Traverse the internal nodes of each optimized partition circuit and add corresponding internal nodes to the merged circuit;

[0125] Traverse the PI of each optimized partition circuit to determine whether the PI is the PI of the original digital logic circuit. If so, add the PI to the merged circuit; if not, it means that the PI is an internal node in the original circuit, and add the internal node to the merged circuit;

[0126] After the partition circuits are merged, an optimized circuit is obtained. In the open source process library ASAP7 and EPFL combinational logic circuit test examples, this embodiment improves the area, delay and area-delay product by 5.8%, 16.9% and 20.2% respectively. The area-delay product is the product of the area and delay of the digital logic circuit after process mapping, which reflects the quality of the overall circuit.

[0127] Table 1

[0128]

[0129] In summary, through the above-mentioned logic optimization method, the present invention can partition the digital logic circuit according to the key path information of the original digital logic circuit in view of the heterogeneous characteristics of the digital logic circuit, and obtain the circuit partitioning result with the least impact on the critical path; and automatically explore the best optimization structure and operator corresponding to the next state in each partition optimization space, rather than only optimizing under a single structure complete circuit. Compared with the traditional optimization method, it can achieve a deeper exploration of the optimization space, and realize the optimization structure and process for area and delay for a given digital logic circuit. At the same time, the automated exploration process does not require manual labor, which helps reduce the labor cost of chip design optimization. The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also regarded as the protection scope of the present invention.

Claims

1. A generative heterogeneous logic optimization method based on critical path partitioning, characterized in that: The method comprises: Step S1: construct a reinforcement learning partitioning agent model for the critical path of the digital logic circuit; Step S2: partitioning the digital logic circuit by using a reinforcement learning graph partitioning agent model for a critical path of the digital circuit to obtain a plurality of partitioned circuits; Step S3: multiple partitioned circuits automatically perform optimization space exploration using a reinforcement learning optimization model to obtain multiple optimized partitioned circuits; Step S4: merging each optimized partition circuit to obtain a final optimization result; Step S1 specifically includes: S101: Constructing digital logic circuits Obtain different digital logic circuits and construct a data set; The digital logic circuits in the data set are converted into AIG graph format to obtain the digital logic circuit transfer graph; according to the logic function description in the original digital logic circuit, its logic function is simplified into "logical AND" and "logical NOT" operations. In the digital logic circuit transfer graph, each node represents the "logical AND" function, and each edge represents the connection relationship between nodes. At the same time, the edge represents the "logical NOT" function when it is flipped; S102: Mark the critical path of the circuit: Marking the circuit critical path on the digital logic circuit transfer diagram obtained in step S101; wherein the circuit critical path is the path with the longest delay in the digital logic circuit, that is, the path with the most levels in the digital logic circuit transfer diagram; Then, all the critical path nodes are found on the digital logic circuit transfer diagram obtained in step S101, and the edges between these nodes are marked as critical paths, and finally a circuit representation diagram to be partitioned with critical path information is obtained; S103: Use the reinforcement learning A2C model to partition the circuit representation graph with key path information and calculate the single-step partition reward function Update model parameters; S104: Repeat steps S101 to S103 for all digital logic circuits in the data set until the reinforcement learning A2C model converges, and obtains a reinforcement learning partitioning agent model for the critical path of the digital logic circuit.

2. The method according to claim 1, characterized in that: In step S102, the critical path of the circuit is obtained specifically by performing a depth-first search on all POs in the digital logic circuit, traversing the child nodes of each node in all paths under the PO, and if the child node is not a basic input PI and the level number is the level number of the parent node minus 1, it means that the child node belongs to the critical path of the circuit, otherwise it is considered that the child node does not belong to the critical path of the circuit, until all critical path nodes are obtained.

3. The method according to claim 1, characterized in that: In step S103, the single-step loss function in the training process of the reinforcement learning A2C model is for: Formula (1) Formula (2) in represents the model parameters, express Moment diagram status, represents the action chosen at time t, express exist The probability distribution under express Estimated value, represents the loss coefficient; represents the discount factor, express The single-step reward function at the moment; Single-step reward function at time t after introducing the circuit critical path for: Formula (3) Formula (4) Formula (5) in The state of the graph after executing a single-step partition operation. is the critical path factor; The number of times the critical path of the current partition operation is cut; is the partition normalization function; G is the graph state after partitioning, V n represents partition n, is the capacity function of the partition, The function is to count the number of edges cut by the statistical partition; Q∈[1,n], deg(v) function is the degree function of the node.

4. The method according to claim 1, characterized in that: The step S2 comprises the following sub-steps: S201: Partition the digital logic circuit: The digital logic circuit to be partitioned is converted into the AIG graph format, and then input into the trained reinforcement learning graph partitioning agent model for partitioning to obtain the graph partitioning information with critical paths; S202: Partitioning the digital logic circuit: The graph partitioning information is converted into node partitioning information, and then the original digital logic circuit is partitioned; then each node of the original digital logic circuit is traversed for each circuit partition, and a partition circuit is constructed according to each node partition information.

5. The method according to claim 4, characterized in that: In step S202, the step of constructing a partition circuit according to each node partition information is as follows: Traverse each node of each circuit partition. If the current node itself is the PI or PO of the original digital logic circuit, add it as PI or PO in the partition circuit; if the current node is not PI or PO and the fan-in node of the current node belongs to the partition of the current node, add the current node to the partition circuit; if the current node is not PI or PO and the fan-in node of the current node does not belong to the partition of the current node, add the fan-in node of the current node as PI in the partition circuit; if the current node is not PI or PO and the fan-out node of the current node does not belong to the partition of the current node, add the fan-out node of the current node as PO in the new partition circuit; if the current node is not PI or PO and the fan-out node of the current node belongs to the partition of the current node, add the current node to the partition circuit.

6. The method according to claim 1, characterized in that: The step S3 comprises the following sub-steps: S301: Initialization: Initialize each partition circuit, determine the optimization environment, and set the exploration iteration length; S302: Optimization operator selection: Extract the features of the partitioned circuit, pass the results of the partitioned circuit feature standardization and the historical data of multiple optimization operators into the reinforcement learning optimization model, and obtain the most suitable optimization operator for the current partitioned circuit; S303: Partition circuit optimization: According to the selected optimization operator, the partition circuit is optimized, and the single-step optimization reward function is calculated to update the reinforcement learning optimization model; S304: Repeat steps S302-S303 until the maximum number of iterations is reached, and finally multiple optimized partition circuits are obtained.

7. The method according to claim 6, characterized in that: In step S302, the characteristics of the partitioned circuit include the number of nodes in the digital logic circuit graph, the number of edges, the number of levels of the AIG graph corresponding to the circuit, the number of latches, the proportion of "logical AND" gates and "logical NOT" gates, the maximum fan-in and fan-out of the digital logic circuit after process mapping, and the average fan-in and fan-out of the logic nodes.

8. The method according to claim 6, characterized in that: In step S303, the single-step optimization reward function is: Formula (6) Formula (7) in and They are the delay and area after process mapping of the partition circuit. is the weight coefficient; represents the circuit state at time k, Indicates the number of iterations.

9. The method according to claim 1, characterized in that: The step S4 specifically comprises: According to the original node partition information, traverse the PO of each optimized partition circuit to determine whether the PO is the PO of the original digital logic circuit. If so, add the PO to the merged circuit. If not, it means that the PO is an internal node in the original digital logic circuit, and add the internal node to the merged circuit. Traverse the internal nodes of each optimized partition circuit and add corresponding internal nodes to the merged circuit; Traverse the PI of each optimized partition circuit to determine whether the PI is the PI of the original digital logic circuit. If so, add the PI to the merged circuit; if not, it means that the PI is an internal node in the original digital logic circuit, and add the internal node to the merged circuit.

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