Word line decoding circuit for reducing high-voltage programming electric leakage

Abstract

The invention discloses a word line decoding circuit for reducing high-voltage programming electric leakage. The word line decoding circuit comprises a word line pre-decoding circuit controlled by a first control signal BA / RA and a second control signal PROG; the decoder receives the first control signal BA / RA and the second control signal PROG and outputs a control signal INSB; the control signal INSB is connected to the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube. The source electrode of the first PMOS tube is connected to a first voltage signal VDDI, the drain electrode of the first PMOS tube is connected to the source electrode of the second PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube and is connected with a word line WL to apply a driving signal; the grid electrode of the second PMOS tube is connected with a third driving signal GNDA33; and the source electrode of the first NMOS tube is connected with a second power supply signal VNEGC. According to the invention, the second PMOS tube is added in the circuit, and the Vgd of the original driving P tube is changed into GNDA33 and VNEGC, so that the electric leakage is reduced. In read, WL is selected to be equal to 1, WL is not selected to be equal to VNEGC (at the moment, VNEGC is equal to 0V), and the newly added second PMOS tube does not affect the function of the original module.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device design, and in particular to a word line decoding circuit for reducing high voltage programming leakage in a NVM memory. Background Art

[0002] In storage devices, the reading, writing, and erasing of storage cells all involve different operating voltages. Especially for the erasing operation, the programming voltage is often higher than the voltage that the power supply can provide. The internal charge pump PUMP circuit generates high voltage (higher than the power supply voltage or lower than 0V) as the erase voltage of the storage cell. After the high-voltage erase, the storage cell can be transformed from "0" to "1".

[0003] Pump circuit, also known as switched capacitor voltage converter, is a DC-DC converter that uses "flying" or "pumping" capacitors (not inductors or transformers) to store energy. It generates high voltage through the accumulation effect of capacitors on charge, causing current to flow from low potential to high potential, that is, charging the capacitor, removing the capacitor from the charging circuit to isolate the charged charge, and then connecting it to another circuit to transfer the isolated charge. A charge pump is a DC-DC converter that uses capacitors as energy storage elements. It is mostly used to generate an output voltage greater than the input voltage, or to generate a negative output voltage. The charge pump circuit uses "pumping capacitors" to boost the power supply voltage to the required erase voltage. FLASH products require a charge pump charging circuit to provide erase power. The PUMP circuit in the FLASH device uses multiple capacitors to complete the voltage boost.

[0004] When erasing or writing a cell in the memory, the high voltage generated by the charge pump is transmitted to the erase cell through a transmission path. There are various shutdown transistors on the path, and there is leakage current on the high voltage. According to the leakage current, a charge pump with corresponding driving force needs to be designed. The greater the leakage current, the greater the driving force, and the power consumption and area of ​​the charge pump will increase.

[0005] On a certain process platform, the EEPROM of the storage cell of the differential SONOS memory is designed. The external power supply VDDA33 of the memory IP has a voltage range of 1.62 to 3.6V. When performing high-voltage erasing, an internal power supply VDDI (about 1.5 to 2.3V) is required to prevent the 3.3V tube from exceeding the breakdown voltage BV.

[0006] When IP is being programmed, VNEG (-3.6V) is applied to all word lines WL. The schematic diagram of the word line decoding circuit is as follows: Figure 1As shown, the word line decoding circuit is directly related to the completion of the read, write and erase operations of the storage cell array and the speed of access. Among them, PROG=1, INSB=1, WL=VNEG_C. At this time, the state of the P0 tube, under high temperature, high pressure, and FF conditions, has a large GIDL leakage from VDDI to VNEG_C, and the current flows from the Sub of the P0 tube to the Drain end. Since there is a reading speed requirement when reading data from the Cell, the size of the P0 tube as a driver cannot be too small. The larger the size of the P0 tube, the greater the leakage current. The existence of this leakage current greatly increases the driving force requirements of the VNEG PUMP. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a word line decoding circuit which can reduce the leakage of high voltage programming.

[0008] In order to solve the above problems, a word line decoding circuit for reducing high voltage programming leakage according to the present invention comprises: A word line pre-decoding circuit controlled by a first control signal BA / RA and a second control signal PROG; The decoder receives the first control signal BA / RA and the second control signal PROG, and outputs a control signal INSB; The control signal INSB is connected to the gates of the first PMOS transistor and the first NMOS transistor; The source of the first PMOS tube is connected to the first voltage signal VDDI, the drain of the first PMOS tube is connected to the source of the second PMOS tube, the drain of the second PMOS tube is connected to the drain of the first NMOS tube and connected to the word line WL, and a driving signal is applied to the word line WL; The gate of the second PMOS tube is connected to the third driving signal GNDA33; The source of the first NMOS tube is connected to the second power signal VNEG_C.

[0009] Furthermore, the voltage range of the first voltage signal VDDI is 1.5-2.3V.

[0010] Furthermore, the second power signal VNEG_C is a negative voltage, and its value is -3.6V.

[0011] Furthermore, in the word line decoding circuit, when programming the storage cell, the control signal INSB is at a high level 1, the word line WL=VNEG_C, the gate of the second PMOS tube is connected to the third drive signal GNDA33, the second PMOS tube is disconnected, the VNEG_C voltage cannot be transmitted to the drain of the first PMOS tube, and the leakage current of the second PMOS tube is significantly reduced.

[0012] Furthermore, the voltage of the third driving signal GNDA33 is 0V.

[0013] Furthermore, the second power signal VNEG_C has a negative voltage value when the memory cell is in a programming state, and has a zero value when the memory cell is in a reading state.

[0014] The word line decoding circuit for reducing high voltage programming leakage of the present invention adds a second PMOS tube in the circuit to change the Vgd of the original driving P tube from the voltage difference between VDDI and VNEG_C to GNDA33 and VNEG_C, thereby reducing the leakage at that location. When reading, WL=1 is selected, and WL=VNEG_C is not selected (at this time VNEG_C=0V), and the newly added second PMOS tube does not affect the function of the original module. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit structure diagram of an existing word line decoding circuit.

[0016] Figure 2 It is a circuit structure schematic diagram of the word line decoding circuit provided by the present invention. DETAILED DESCRIPTION

[0017] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0018] It should be understood that the present invention can be implemented in different forms, and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layer and the zone may be exaggerated, and the same reference numerals represent the same elements from beginning to end. It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to " or "coupled to " other elements or layers, it can be directly on other elements or layers, adjacent to it, connected or coupled to other elements or layers, or there can be an intervening element or layer. On the contrary, when an element is referred to as "directly on ... ", "directly adjacent to ... ", "directly connected to " or "directly coupled to " other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, zones, layers and / or parts, these elements, components, zones, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0019] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below with reference to specific diagrams.

[0020] The present invention provides a new word line decoding circuit, which is aimed at some specific process platforms where the process cannot effectively control GIDL leakage. By adding a PCH3 tube in the circuit, that is, Figure 2 The P1 tube shown changes the Vgd of the P tube from the voltage difference between VDDI and VNEG_C to the voltage difference between GNDA33 and VNEG_C. The reduction in the voltage difference reduces the leakage at this location.

[0021] Circuit structure as Figure 2 As shown, it includes a word line pre-decoding circuit controlled by a first control signal BA / RA and a second control signal PROG. The first control signal BA / RA is an address signal, and the second control signal PROG is a programming signal of the memory cell.

[0022] The word line pre-decoding circuit receives the first control signal BA / RA and the second control signal PROG, that is, outputs a control signal INSB according to an address signal and a programming signal to determine the state of programming or reading a selected memory cell tube.

[0023] The control signal INSB is connected to the gates of the first PMOS transistor P0 and the first NMOS transistor N0.

[0024] The source of the first PMOS transistor P0 is connected to the first voltage signal VDDI, which is the internal power supply of the storage unit and has a voltage of 1.5 to 2.3 V. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor P1, and the drain of the second PMOS transistor P1 is connected to the drain of the first NMOS transistor and connected to the word line WL, and a driving signal is applied to the word line WL.

[0025] The gate of the second PMOS transistor P1 is connected to the third driving signal GNDA33, and the voltage of the third driving signal GNDA33 is 0V.

[0026] The source of the first NMOS transistor N0 is connected to a second power signal VNEG_C, which is a negative voltage with a voltage value of -3.6V.

[0027] When programming PROG to the memory cell, the programming voltage is high level 1, INSB=1, WL=VNEG_C (negative voltage), the gate of P1 tube is connected to GNDA33=0V, P1 tube is disconnected to isolate the word line WL from P0 tube, and the VNEG_C voltage cannot be transmitted to the drain end of P0 tube, that is, the node where P0 tube and P1 tube are connected in series. The GIDL leakage of P1 tube is significantly reduced.

[0028] When the storage cell state is read, WL=1 is selected, and WL=VNEG_C is not selected (at this time VNEG_C=0V). The newly added P1 tube does not affect the module function. In other words, after adding the P1 tube, the problem of GIDL leakage of the driver tube is solved, and the operation of the original circuit is not affected.

[0029] According to the existing circuit scheme, that is, Figure 1 In the circuit shown, the VNEG_C leakage generated by one row of word lines WL is about 10nA. If there are 1000 rows of word lines WL, the leakage is 10uA.

[0030] By adopting the circuit solution of the present invention, the VNEG_C leakage generated by one row of word lines WL is 80pA. If 1000 rows of word lines WL only have 80nA of leakage, the improvement effect is obvious.

[0031] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A word line decoding circuit for reducing high voltage programming leakage, characterized in that: The word line decoding circuit provides a driving voltage when the memory chip reads and writes data, and includes: A word line pre-decoding circuit controlled by a first control signal BA / RA and a second control signal PROG; The decoder receives the first control signal BA / RA and the second control signal PROG, and outputs a control signal INSB; The control signal INSB is connected to the gates of the first PMOS transistor and the first NMOS transistor; The source of the first PMOS tube is connected to the first voltage signal VDDI, the drain of the first PMOS tube is connected to the source of the second PMOS tube, the drain of the second PMOS tube is connected to the drain of the first NMOS tube and connected to the word line WL, and a driving signal is applied to the word line WL; The gate of the second PMOS tube is connected to the third driving signal GNDA33; The source of the first NMOS tube is connected to the second power signal VNEG_C.

2. The word line decoding circuit for reducing high voltage programming leakage as claimed in claim 1, characterized in that: The voltage range of the first voltage signal VDDI is 1.5-2.3V.

3. The word line decoding circuit for reducing high voltage programming leakage as claimed in claim 1, characterized in that: The second power signal VNEG_C is a negative voltage, and its value is -3.6V.

4. The word line decoding circuit for reducing high voltage programming leakage as claimed in claim 1, characterized in that: In the word line decoding circuit, when programming the storage unit, the control signal INSB is at a high level 1, the word line WL=VNEG_C, the gate of the second PMOS tube is connected to the third drive signal GNDA33, the second PMOS tube is disconnected, the VNEG_C voltage cannot be transmitted to the drain of the first PMOS tube, and the leakage current of the second PMOS tube is significantly reduced.

5. The word line decoding circuit for reducing high voltage programming leakage as claimed in claim 4, characterized in that: The voltage of the third driving signal GNDA33 is 0V.

6. The word line decoding circuit for reducing high voltage programming leakage as claimed in claim 3, characterized in that: The second power signal VNEG_C is a negative voltage when the memory cell is in a programming state, and is zero when the memory cell is in a reading state.

7. The word line decoding circuit for reducing high voltage programming leakage as claimed in claim 1, characterized in that: The first control signal BA / RA is a storage unit address signal.

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