Reconstruction wafer, wafer reconstruction method and preparation method of display panel

Abstract

The embodiment of the invention discloses a reconstructed wafer, a wafer reconstruction method and a preparation method of a display panel, and the method comprises the steps: removing a first substrate at one side of an epitaxial structure layer of a to-be-segmented wafer to obtain a first intermediate structure, and segmenting the first intermediate structure corresponding to the to-be-segmented wafer with a smaller size into a plurality of wafers, the wafer is bonded with the carrier with a larger size to obtain the reconstructed wafer, so that the small-size to-be-segmented wafer can be reconstructed into the large-size reconstructed wafer, and the size of the reconstructed wafer can meet the requirement of an advanced technological process. Besides, the first substrate is firstly removed, so that wafer defects obtained by wafer segmentation in subsequent steps can be reduced, ion pollution in the subsequent wafer reconstruction process and the preparation process of the display panel after the reconstructed wafer is obtained can be reduced, and the yield of the reconstructed wafer and the display panel can be improved. Toxic gas is easily generated on the first substrate containing gallium arsenide during cutting, and the first substrate is removed in advance, so that the production safety is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a reconstructed wafer, a wafer reconstructing method and a method for preparing a display panel. Background Art

[0002] Gallium arsenide-based epitaxial wafers have great application prospects in the field of light-emitting diodes.

[0003] The epitaxial growth technology of epitaxial wafers with smaller sizes (such as 4 inches or 6 inches) is more mature, but the epitaxial growth technology is relatively weak at larger sizes (such as 8 inches or 12 inches).

[0004] Some advanced process technologies are carried out on larger wafers, and the small size of epitaxial wafers limits the development of more advanced process technologies in the field of light-emitting diodes. Summary of the invention

[0005] The present invention provides a reconstructed wafer, a wafer reconstruction method and a method for preparing a display panel, so as to reconstruct a small-sized wafer to be divided into a large-sized reconstructed wafer, so that the reconstructed wafer can meet the requirements of advanced process technology.

[0006] According to one aspect of the present invention, there is provided a wafer reconstruction method, comprising:

[0007] The first substrate on one side of the epitaxial structure layer of the wafer to be divided is removed to obtain a first intermediate structure; the epitaxial structure layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are stacked, and the first semiconductor layer is located between the light-emitting layer and the first substrate; the material of the first substrate comprises gallium arsenide;

[0008] dividing the first intermediate structure into a plurality of wafers;

[0009] The wafer is bonded to a carrier to obtain a reconstructed wafer; wherein the area of ​​the carrier is larger than the area of ​​the wafer to be divided.

[0010] Optionally, removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure includes:

[0011] Bonding a side of the epitaxial structure layer of the wafer to be divided away from the first substrate to a second substrate; the second substrate is made of a different material from the first substrate;

[0012] The first substrate is removed.

[0013] Optionally, before removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain the first intermediate structure, the method further includes:

[0014] forming a current spreading layer on a side of the second semiconductor layer away from the first semiconductor layer;

[0015] Bonding a side of the epitaxial structure layer of the wafer to be divided away from the first substrate to the second substrate, comprising:

[0016] The current spreading layer is bonded to the second substrate by using the first bonding layer.

[0017] Optionally, the material of the second substrate is silicon, and the material of the first bonding layer is silicon dioxide.

[0018] Optionally, removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure includes:

[0019] removing the first substrate;

[0020] A plurality of ohmic contact structures are formed on a side of the first semiconductor layer away from the light emitting layer to obtain a first intermediate structure, and the material of the ohmic contact structure is a metal material.

[0021] Optionally, dividing the first intermediate structure into a plurality of wafers comprises:

[0022] Using a patterning process to open an isolation on one side of the first semiconductor layer to form an isolation groove that at least penetrates the epitaxial structure layer;

[0023] forming an insulating dielectric layer on a side of the first semiconductor layer away from the light emitting layer and on a sidewall of the isolation groove;

[0024] On a side of the second substrate away from the epitaxial structure layer, cutting is performed along a cutting path to divide the first intermediate structure into a plurality of wafers; wherein the cutting path corresponds to the position of the isolation groove.

[0025] Optionally, the width of the cutting road is smaller than the width of the corresponding isolation groove.

[0026] Optionally, the distance between adjacent wafers on the carrier is greater than the width of the cutting road, and the distance between adjacent wafers on the carrier is greater than the width of the isolation groove.

[0027] Optionally, a patterning process is used to open an isolation groove on one side of the first semiconductor layer to form an isolation groove that at least penetrates the epitaxial structure layer, including:

[0028] Using a graphic process to open isolation on one side of the first semiconductor layer, forming an isolation groove that penetrates the epitaxial structure layer and the first bonding layer between the epitaxial structure layer and the second substrate;

[0029] Cutting along a cutting path on a side of the second substrate away from the epitaxial structure layer to separate the first intermediate structure into a plurality of wafers includes:

[0030] The second substrate is cut along a cutting line on a side of the second substrate away from the epitaxial structure layer to separate the first intermediate structure into a plurality of wafers.

[0031] Optionally, bonding the wafer to a carrier to obtain a reconstructed wafer includes:

[0032] bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure;

[0033] Bonding a side of the first semiconductor layer of the second intermediate structure away from the second substrate to a third substrate;

[0034] The carrier and the second substrate are removed.

[0035] Optionally, bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure includes:

[0036] Bonding the second substrate of the wafer to the carrier via a second bonding layer to obtain a second intermediate structure; the second bonding layer includes a colloid;

[0037] Removing the carrier and the second substrate comprises:

[0038] removing the carrier and the second bonding layer;

[0039] The second substrate and the first bonding layer between the second substrate and the epitaxial structure layer are removed.

[0040] Optionally, bonding the wafer to a carrier to obtain a reconstructed wafer includes:

[0041] Bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier to obtain a third intermediate structure;

[0042] The second substrate is removed.

[0043] Optionally, bonding the wafer to a carrier to obtain a reconstructed wafer includes:

[0044] Removing defective wafers from a plurality of wafers;

[0045] bonding a plurality of non-defective wafers to a carrier to obtain a reconstructed wafer; and / or

[0046] Selecting a wafer with similar uniformity and consistency among multiple wafers;

[0047] The side of the epitaxial structure layer of a wafer with similar uniformity and consistency among the multiple wafers, which is away from the first substrate, is bonded to a carrier to obtain a reconstructed wafer.

[0048] Optionally, the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

[0049] According to another aspect of the present invention, there is provided a reconstructed wafer obtained by reconstructing the wafer using the wafer reconstruction method according to any embodiment of the present invention.

[0050] According to another aspect of the present invention, there is provided a method for preparing a display panel, comprising:

[0051] Patterning the epitaxial structure layers of multiple chips in the reconstructed wafer to form multiple light-emitting structures; wherein the reconstructed wafer is obtained by using the wafer reconstruction method of any embodiment of the present invention;

[0052] forming a conductive connection structure on one side of the light emitting structure;

[0053] The conductive connection structure is bonded to the driving substrate.

[0054] Optionally, in the reconstructed wafer, the wafer includes a third substrate and a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked on one side of the third substrate; the conductive connection structure is formed on a side of the second semiconductor layer away from the first semiconductor layer;

[0055] After bonding the conductive connection structure to the driving substrate, the method further includes:

[0056] removing the third substrate;

[0057] Rewiring is performed on a side of the first semiconductor layer away from the second semiconductor layer.

[0058] The reconstructed wafer, wafer reconstruction method and display panel preparation method of the embodiment of the present invention, by removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure, dividing the first intermediate structure corresponding to the smaller size of the wafer to be divided into multiple wafers, and bonding the wafers to a larger size carrier to obtain a reconstructed wafer, can achieve the reconstruction of the small size of the wafer to be divided into a large size of the reconstructed wafer, so that the size of the reconstructed wafer can meet the requirements of advanced process technology. In addition, first removing the first substrate can reduce the wafer defects obtained by wafer division in subsequent steps, and reduce ion contamination in the subsequent wafer reconstruction process and the display panel preparation process after obtaining the reconstructed wafer, which is beneficial to improve the yield of the reconstructed wafer and the display panel. In addition, the first substrate containing gallium arsenide is prone to produce toxic gases during cutting, and removing the first substrate in advance is beneficial to improve production safety.

[0059] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0061] Figure 1 is a flow chart of a wafer reconstruction method provided by an embodiment of the present invention;

[0062] Figure 2 It is a schematic diagram of the structure of the wafer to be divided;

[0063] Figure 3 yes Figure 2 A further detailed structural diagram of the wafer to be split;

[0064] Figure 4 is a flow chart of another wafer reconstruction method provided by an embodiment of the present invention;

[0065] Figure 5 is a schematic diagram of the structure after the wafer to be divided is bonded to the second substrate;

[0066] Figure 6 is a schematic diagram of the structure after the first substrate is removed;

[0067] Figure 7 is a schematic structural diagram of forming a plurality of ohmic contact structures on a side of the first semiconductor layer away from the light-splitting layer;

[0068] Figure 8 is a flow chart of another wafer reconstruction method provided by an embodiment of the present invention;

[0069] Fig. 9 is a schematic diagram of the structure after the isolation groove is formed;

[0070] Fig.10 is a top view after the first intermediate structure is divided into a plurality of wafers;

[0071] Fig.11 yes Fig.10 The cross-sectional view obtained by cutting along AA';

[0072] Fig.12 is a top view of a second intermediate structure obtained after bonding the second substrate of the wafer to the carrier;

[0073] Fig.13 yes Fig.12 The cross-sectional view obtained by cutting along BB';

[0074] Fig.14is a schematic structural diagram after a side of the first semiconductor layer of the second intermediate structure away from the second substrate is bonded to a third substrate;

[0075] Fig.15 is a schematic diagram of the structure after the carrier and the second bonding layer are removed;

[0076] Fig.16 is a schematic diagram of the structure after removing the second substrate and the second bonding layer;

[0077] Fig.17 is a flow chart of another wafer reconstruction method provided by an embodiment of the present invention;

[0078] Fig.18 It is a schematic diagram of the structure after bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier;

[0079] Fig.19 is a flow chart of a method for preparing a display panel provided by an embodiment of the present invention;

[0080] Fig. 20 is a schematic diagram of the structure after the light-emitting structure is formed;

[0081] Fig.21 is a schematic diagram of a structure after the conductive connection structure is bonded to the driving substrate;

[0082] Fig. 22 is a flow chart of another method for preparing a display panel provided by an embodiment of the present invention;

[0083] Fig.23 is a schematic diagram of the structure after the third substrate is removed;

[0084] Fig.24 It is a schematic diagram of the structure after the first semiconductor layer is rewired away from the second semiconductor layer. DETAILED DESCRIPTION

[0085] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0086] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0087] Figure 1 is a flowchart of a wafer reconstruction method provided by an embodiment of the present invention, referring to Figure 1 , the wafer reconstruction method comprises:

[0088] S110, removing the first substrate on one side of the epitaxial structure layer of the wafer to be split to obtain a first intermediate structure.

[0089] Figure 2 It is a schematic diagram of the structure of the wafer to be divided. Figure 3 yes Figure 2 A further detailed structural diagram of the wafer to be split is shown in Fig. Figure 2 and Figure 3 The wafer to be split includes a first substrate 10 and an epitaxial structure layer 20 on one side of the first substrate 10, wherein the epitaxial structure layer 20 includes a first semiconductor layer 21, a light emitting layer 22, and a second semiconductor layer 23 which are stacked, and the first semiconductor layer 21 is located between the light emitting layer 22 and the first substrate 10; the material of the first substrate 10 includes gallium arsenide, that is, the wafer to be split is a gallium arsenide-based wafer. The first semiconductor layer 21 is an N-type semiconductor layer, and the second semiconductor layer 23 is a P-type semiconductor layer; or the first semiconductor layer 21 is a P-type semiconductor layer, and the second semiconductor layer 23 is an N-type semiconductor layer. Taking the first semiconductor layer 21 as an N-type semiconductor layer and the second semiconductor layer 23 as a P-type semiconductor layer as an example, Figure 3As shown, the first semiconductor layer 21 may include an N-GaInP layer 211, an N-GaAs layer 212, and an N-AlInP layer 213 stacked from the first substrate 10 to the light-emitting layer 22; the second semiconductor layer 23 includes a P-AlInP layer 231 and a P-GaP layer 232 stacked from one side of the light-emitting layer 22. In an optional embodiment, the thickness of the first substrate 10, the N-GaInP layer 211, the N-GaAs layer 212, the N-AlInP layer 213, the light-emitting layer 22, the P-AlInP layer 231, and the P-GaP layer 232 are 250 μm, 0.2 μm, 0.08 μm, 0.26 μm, 0.2 μm, 0.17 μm, and 0.1 μm, respectively. Of course, the thickness of each structural layer of the wafer to be divided can be adjusted according to actual needs, and the embodiment of the present invention is not specifically limited here.

[0090] Specifically, the size of the wafer to be split meets the requirement for epitaxial growth, and the wafer to be split can be obtained by epitaxial growth. Since the technology of epitaxial growth is mature at a smaller size, in this embodiment, the wafer to be split can be a smaller wafer, for example, a 4-inch wafer or a 6-inch wafer. Among them, the first substrate 10 can be removed by wet etching, for example, ammonia water can be used to easily remove the first substrate 10, and a mixed solution of hydrochloric acid solution and phosphoric acid solution can also be used to remove the first substrate 10. The first intermediate structure obtained after the first substrate 10 is removed from the wafer to be split includes an epitaxial structure layer 20, but does not include the first substrate.

[0091] In some optional embodiments, the material of the first substrate 10 of the wafer to be divided may only include gallium arsenide. In other optional embodiments, the material of the first substrate 10 of the wafer to be divided includes other materials in addition to gallium arsenide. Since gallium arsenide is fragile, it is easy to cause defects in the wafer when the wafer is divided in the subsequent steps, and gallium arsenide is prone to ion contamination. In this step, the first substrate 10 is first removed, which can reduce the defects of the wafer obtained by wafer division in the subsequent steps, and reduce the ion contamination in the subsequent wafer reconstruction process and the display panel preparation process after the reconstructed wafer is obtained. Due to the high requirements for the chamber in the large-size process, the first substrate 10 is removed in advance to reduce the ion contamination in the chamber, which is beneficial to improve the yield of the reconstructed wafer and the display panel. In addition, the first substrate 10 containing gallium arsenide is prone to produce toxic gases during cutting, and removing the first substrate 10 in advance is beneficial to improve production safety.

[0092] S120, dividing the first intermediate structure into a plurality of wafers.

[0093] In this step, the wafer to be split is split into multiple chips, where a chip can be a part of the wafer to be split, also known as a die, which is an unpackaged semiconductor chip obtained by splitting the wafer to be split. When splitting the wafer to be split, an etching process and / or a cutting process can be used, and the cutting process can be a laser invisible cutting process or a plasma cutting process.

[0094] S130 , bonding the wafer to the carrier to obtain a reconstructed wafer.

[0095] The area of ​​the carrier is larger than the area of ​​the wafer to be divided.

[0096] In this step, the plurality of wafers obtained after the first intermediate structure is divided are bonded to a carrier, and the area of ​​the carrier is larger than the area of ​​the wafer to be divided, so as to achieve the reconstruction of the smaller wafer to be divided into a larger reconstructed wafer, so that the size of the reconstructed wafer can meet the requirements of advanced process technology. Exemplarily, the reconstructed wafer is a 12-inch wafer. Optionally, the reconstructed wafer can form a plurality of red light emitting devices in a subsequent process.

[0097] In some optional embodiments, the above S130 includes removing defective wafers from the plurality of wafers; and bonding the plurality of non-defective wafers to a carrier to obtain a reconstructed wafer. In this way, each wafer on the reconstructed wafer obtained after reconstruction can be a non-defective wafer, thereby improving the yield of the display panel prepared from the reconstructed wafer.

[0098] Among them, a defective wafer is a wafer including at least one of particle defects, scratch defects, bubble defects, crack and fracture defects, and lattice defects. A non-defective wafer is a wafer that does not include particle defects, scratch defects, bubble defects, crack and fracture defects, and lattice defects. The method of determining whether a wafer is a defective wafer or a non-defective wafer may include optical detection, electron beam detection, light scattering detection, etc.

[0099] In some optional embodiments, the above S130 may further include selecting a wafer with similar uniformity and consistency from a plurality of wafers; and bonding the plurality of wafers with similar uniformity and consistency to a carrier to obtain a reconstructed wafer.

[0100] Among them, the wafer with similar uniformity and consistency refers to the wavelength uniformity within a single wafer is less than 1nm, and the wavelength uniformity between different wafers is less than 3nm; and the particles included in the wafer are less than or equal to 20ea, wherein the diameter of the particles is greater than or equal to 15μm. In addition, multiple epitaxial structural layers with similar uniformity and consistency are bonded to the carrier on the side away from the first substrate to obtain a reconstructed wafer. It is necessary to ensure that when the reconstructed wafer is a blue light wafer, the blue light wavelength range is 455nm-465nm, when the reconstructed wafer is a green light wafer, the green light wavelength range is 520-540nm, and when the reconstructed wafer is a red light wafer, the red light wavelength range is 615nm-635nm, thereby improving the uniformity and consistency of the display panel prepared by the reconstructed wafer. In this way, the optoelectronic parameters (such as wavelength, brightness, typical parameters, etc.) of each wafer on the reconstructed wafer obtained by reconstruction can be uniform and consistent, such as controlling the average wavelength fluctuation range of each wafer within 1nm, thereby improving the uniformity and consistency of the display panel prepared by the reconstructed wafer.

[0101] The wafer reconstruction method of this embodiment removes the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure, divides the first intermediate structure corresponding to the smaller size of the wafer to be divided into multiple wafers, and bonds the wafers to a larger size carrier to obtain a reconstructed wafer. It can achieve the reconstruction of the small size of the wafer to be divided into a large size reconstructed wafer, so that the size of the reconstructed wafer can meet the requirements of advanced process technology. In addition, removing the first substrate first can reduce the defects of the wafers obtained by wafer division in subsequent steps, and reduce ion contamination in the subsequent wafer reconstruction process and the display panel preparation process after obtaining the reconstructed wafer, which is beneficial to improve the yield of the reconstructed wafer and the display panel. In addition, the first substrate containing gallium arsenide is prone to produce toxic gases during cutting, and removing the first substrate in advance is beneficial to improve production safety.

[0102] Figure 4 is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention, referring to Figure 4 , the wafer reconstruction method comprises:

[0103] S210, bonding a side of the epitaxial structure layer of the wafer to be divided away from the first substrate to a second substrate; the second substrate is made of a different material from the first substrate.

[0104] Figure 5Schematic diagram of the structure after the wafer to be split is bonded to the second substrate. Optionally, when the side of the epitaxial structure layer 20 of the wafer to be split away from the first substrate 10 is bonded to the second substrate 30: when the side of the epitaxial structure layer 20 of the wafer to be split away from the first substrate 10 does not include other structural layers, the epitaxial structure layer 20 can be bonded to the second substrate 30. When the side of the epitaxial structure layer 20 of the wafer to be split away from the first substrate 10 includes other structural layers, the other structural layers of the epitaxial structure layer 20 away from the first substrate 10 can be bonded to the second substrate 30. Reference Figure 2 , Figure 3 and Figure 5 Optionally, before S210, it further includes: forming a current spreading layer 40 on a side of the second semiconductor layer 23 away from the first semiconductor layer 21. Accordingly, the above S210 includes: bonding the current spreading layer 40 to the second substrate 30 using the first bonding layer 50. That is, referring to Figure 2 , Figure 3 and Figure 5 , the other structural layers on the side of the epitaxial structural layer 20 of the wafer to be divided away from the first substrate 10 may be the current spreading layer 40. Optionally, the material of the current spreading layer 40 may be indium tin oxide ITO. When forming the current spreading layer 40, it can be achieved by plating an ITO film on the side of the second semiconductor layer 23 away from the first semiconductor layer 21. Exemplarily, the thickness of the ITO film is less than 100nm, that is, the thickness of the current spreading layer 40 may be 30nm, 50nm, 80nm, or 100nm. The provision of the current spreading layer 40 can enable the second semiconductor layer 23 to form a reliable electrical connection with the circuit in the driving substrate after the display panel is subsequently formed and / or enable the current to be better spread on the surface of the second semiconductor layer 23.

[0105] Optionally, the second substrate 30 is a silicon substrate, and the material of the first bonding layer 50 is silicon dioxide. When bonding the wafer to be separated to the second substrate 30, silicon fusion bonding or thermal bonding may be used.

[0106] S220 , removing the first substrate.

[0107] Figure 6It is a schematic diagram of the structure after the first substrate is removed. Specifically, the first substrate is removed after the side of the epitaxial structure layer 20 of the wafer to be split away from the first substrate is bonded to the second substrate 30. When removing the first substrate, the surface where the second substrate 30 is located is placed at the corresponding process station position, that is, the second substrate 30 is in contact with the bearing structure of the station, and the current expansion layer 40 will not be in contact with the bearing structure of the process station, so as to avoid the surface of the current expansion layer 40 from being corroded or introduced with dirt during the removal of the first substrate and some subsequent process steps, thereby ensuring that the current expansion layer 40 has a good current expansion effect. In addition, the material of the second substrate 30 is silicon, which is not easy to break compared to gallium arsenide, and no ion pollution and toxic gas will be generated during cutting, which can reduce the ion pollution and toxic gas during the subsequent wafer splitting, extend the service life of the wafer reconstruction equipment, and improve production safety. In some optional embodiments, it can be Figure 6 The structure shown serves as a first intermediate structure.

[0108] In another optional embodiment of the present invention, after the above S220, the following S230 is further included, and the structure after S230 is used as the first intermediate structure.

[0109] S230 , forming a plurality of ohmic contact structures on a side of the first semiconductor layer away from the light-emitting layer to obtain a first intermediate structure, wherein the material of the ohmic contact structure is a metal material.

[0110] Figure 7 It is a structural schematic diagram of forming multiple ohmic contact structures on the side of the first semiconductor layer away from the splitting layer. Specifically, for gallium arsenide-based wafers, it is more difficult to form ohmic contact with the first semiconductor layer 21. In this step, multiple metal material ohmic contact structures 60 are formed on the side of the first semiconductor layer 21 away from the splitting layer, so that in the display panel structure prepared by the reconstructed wafer, the first semiconductor layer 21 can form a good ohmic contact with the conductive structure in the display panel through the ohmic contact structure 60, thereby improving the yield and display effect of the display panel. Optionally, the material of the ohmic contact structure 60 is a three-layer structure of gold, germanium and gold, in which the outer two layers are gold and the middle layer is germanium. Specifically, the ohmic contact structure 60 can be formed by annealing gold, germanium and gold at 400°C.

[0111] S240, dividing the first intermediate structure into a plurality of wafers.

[0112] S250 , bonding the wafer to the carrier to obtain a reconstructed wafer.

[0113] Figure 8 is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention, referring to Figure 8 , the wafer reconstruction method comprises:

[0114] S310, bonding the side of the epitaxial structure layer of the wafer to be divided away from the first substrate to the second substrate (see Figure 5 ).

[0115] S320, removing the first substrate (see Figure 6 ).

[0116] like Figure 7 As shown, after removing the first substrate, a plurality of ohmic contact structures 60 may be formed on a side of the first semiconductor layer 21 away from the light emitting layer 22 to obtain a first intermediate structure.

[0117] S330, using a patterning process to open an isolation on one side of the first semiconductor layer to form an isolation groove that at least penetrates the epitaxial structure layer.

[0118] Fig. 9 It is a schematic diagram of the structure after the isolation groove is formed. Fig. 9 The schematic diagram shows the situation that the isolation groove 70 penetrates the epitaxial structure layer 20. The isolation groove 70 can be formed by photolithography and etching processes. Since the second substrate 30 itself is relatively thick, it is not easy to etch through the second substrate 30 by photolithography and etching processes. In this step, it is sufficient to ensure that the isolation groove 70 formed at least penetrates the epitaxial structure layer 20. In this way, when the wafer to be divided is cut later, it is not necessary to use a cutting process to divide the epitaxial structure layer 20. The epitaxial structure layer 20 contains gallium arsenide material. Not using a cutting process on the epitaxial structure layer 20 can avoid the generation of toxic gases due to cutting the epitaxial structure layer 20.

[0119] S340, forming an insulating dielectric layer on a side of the first semiconductor layer away from the light emitting layer and on a sidewall of the isolation trench.

[0120] Continue to refer Fig. 9 The insulating dielectric layer 80 can be located on the side of the ohmic contact structure 60 away from the light emitting layer 22, the side of the first semiconductor layer 21 away from the light emitting layer 22, and the side and bottom of the isolation groove 70. By forming the insulating dielectric layer 80 on the sidewall of the isolation groove 70, the insulating dielectric layer 80 can protect the sidewall of the isolation groove 70 formed by the epitaxial structure layer 20, so that the epitaxial structure layer 20 will not be damaged in some process steps, thereby reducing the generation of defective wafers. Optionally, the material of the insulating dielectric layer 80 is silicon nitride.

[0121] S350, cutting along a cutting path on a side of the second substrate away from the epitaxial structure layer to divide the first intermediate structure into a plurality of wafers; wherein the cutting path corresponds to a position of the isolation groove.

[0122] Fig.10 is a top view after the first intermediate structure is divided into a plurality of wafers, Fig.11yes Fig.10 The cross-sectional view obtained by cutting along AA', refer to Fig.10 and Fig.11 Optionally, the cutting process for cutting the first intermediate structure can be a laser cutting process or a plasma cutting process. The cutting path corresponds to the position of the isolation groove 70 in the thickness direction of the wafer to be divided, so that after the first intermediate structure is cut from the side of the second substrate 30 away from the epitaxial structure layer 20, the cutting gap 90 obtained by cutting is connected to the isolation groove 70, and then the first intermediate structure is divided into multiple chips 01. Among them, the chip 01 can be a part of the wafer to be divided, also called a die, which is an unpackaged semiconductor chip obtained by dividing the wafer to be divided. In this step, the structural layer in the cutting first intermediate structure includes the structural layer that is not etched when the isolation is opened in S320, so that after cutting, the gap 90 formed by cutting can be connected to the isolation groove 70.

[0123] Optionally, the width of the cutting path is smaller than the width of the corresponding isolation groove 70. In this way, even if there is a certain error in cutting, the cutting gap 90 formed after cutting from the side of the second substrate 30 away from the epitaxial structure layer 20 can be connected to the isolation groove 70, so that the adjacent wafers 01 are completely separated, ensuring that the size of the separated wafers 01 meets the requirements.

[0124] In some optional embodiments of the present invention, S330 includes using a graphic process to open an isolation on one side of the first semiconductor layer 21 to form an isolation groove 70 that penetrates the epitaxial structure layer 20 and the first bonding layer 50 between the epitaxial structure layer 20 and the second substrate 30; correspondingly, S350 includes: on the side of the second substrate 30 away from the epitaxial structure layer 20, cutting the second substrate 30 along the cutting path to divide the first intermediate structure into multiple wafers 01. In this way, it can be ensured that when there is a current expansion layer 40 on the side of the second semiconductor layer 23 away from the light-emitting layer 22, the current expansion layer 40 will also be penetrated by the isolation groove 70, and accordingly, the insulating dielectric layer 80 will also protect the current expansion layer 40, further avoiding the generation of defective wafers 01.

[0125] S360, bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure.

[0126] Fig.12 is a top view of a second intermediate structure obtained after bonding the second substrate of the wafer to the carrier, Fig.13 yes Fig.12 The cross-sectional view obtained by cutting along BB' is shown in Figure 2. Fig.12 and Fig.13In this step, the total area of ​​the second intermediate structure obtained after bonding the second substrate 30 of the wafer 01 to the carrier 100 is larger than the area of ​​the wafer to be divided, so as to achieve the reconstruction of the small-sized wafer to be divided into a reconstructed wafer of a larger size. Optionally, S360 includes bonding the second substrate 30 of the wafer 01 to the carrier 100 through the second bonding layer 101 to obtain the second intermediate structure; the second bonding layer 101 includes a colloid, and the cost of the colloid material is relatively low. Using the colloid to bond the wafer 01 and the carrier 100 is conducive to cost saving. Since the epitaxial structure layer 20 includes gallium arsenide material, the epitaxial structure layer 20 is fragile, and the use of colloid for bonding is prone to deformation, warping and other problems. In this embodiment, the second substrate 30 of the wafer 01 is bonded to the carrier 100 through the colloid, so that even if the bonding causes deformation and / or warping, the impact on the epitaxial structure layer 20 will be small, so as to ensure the yield of the reconstructed wafer formed, and then ensure the yield of the display panel prepared by the reconstructed wafer. Since the carrier 100 and the second substrate 30 will be removed in subsequent steps, the deformation or warping of the carrier 100 and the second substrate 30 will have little impact on the reconstructed wafer.

[0127] After the wafer is reconstructed, the obtained reconstructed wafer needs to be subjected to subsequent advanced process, and the spacing between the wafers 01 must meet the corresponding process requirements. Therefore, optionally, when the wafer 01 is bonded to the carrier 100, the subsequent process requirements of multiple wafers 01 can be rearranged. Optionally, the distance between adjacent wafers 01 on the carrier 100 is greater than the width of the cutting road, and the distance between adjacent wafers 01 on the carrier 100 is greater than the width of the isolation groove 70, so as to meet the requirements of subsequent advanced process.

[0128] S370 , bonding the side of the first semiconductor layer of the second intermediate structure away from the second substrate to the third substrate.

[0129] Fig.14 is a schematic diagram of a structure after bonding the side of the first semiconductor layer of the second intermediate structure away from the second substrate to the third substrate, referring to Fig.14 Optionally, the side of the first semiconductor layer 21 of the second intermediate structure away from the second substrate 30 is bonded to the third substrate 102 through the third bonding layer 103. In the case where the side of the first semiconductor layer 21 away from the light emitting layer 22 includes an insulating dielectric layer 80, the insulating dielectric layer 80 on the second intermediate structure can be bonded to the third substrate 102 through the third bonding layer 103. The material of the third substrate 102 can be silicon, and the material of the third bonding layer 103 can be silicon dioxide. In this step, silicon melt bonding or thermal bonding can be used to bond the second intermediate structure to the third substrate 102.

[0130] S380 , removing the carrier and the second substrate.

[0131] Optionally, S380 includes removing the carrier 100 and the second bonding layer 101 ; and removing the second substrate 30 and the first bonding layer 50 between the second substrate 30 and the epitaxial structure layer 20 .

[0132] Fig.15 It is a schematic diagram of the structure after removing the carrier and the second bonding layer. Fig.16 It is a schematic diagram of the structure after removing the second substrate and the second bonding layer. The second substrate can be removed by chemical mechanical polishing and / or wet etching process. Since S340 forms an insulating dielectric layer 80 on the side wall of the isolation groove 70, the insulating dielectric layer 80 can protect the epitaxial structure layer 20 during the process of removing the second substrate and the second bonding layer, thereby improving the yield of the obtained reconstructed wafer and display panel.

[0133] In this embodiment, a reconstructed wafer is obtained after S310 - S380 .

[0134] Fig.17 is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention, referring to Fig.17 , the wafer reconstruction method comprises:

[0135] S410, bonding the side of the epitaxial structure layer of the wafer to be separated away from the first substrate to the second substrate (see Figure 5 ).

[0136] S420, removing the first substrate (see Figure 6 );

[0137] S430, using a graphic process to open an isolation on one side of the first semiconductor layer, forming an isolation groove that at least penetrates the epitaxial structure layer (see Fig. 9 ).

[0138] S440, forming an insulating dielectric layer on a side of the first semiconductor layer away from the light emitting layer and on a sidewall of the isolation trench.

[0139] S450, cutting along the cutting path on the side of the second substrate away from the epitaxial structure layer to divide the first intermediate structure into a plurality of wafers; wherein the cutting path corresponds to the position of the isolation groove (see Fig.10 ).

[0140] S460, bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier to obtain a third intermediate structure.

[0141] Fig.18It is a schematic diagram of the structure after bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier. In this step, by bonding one side of the first semiconductor layer 21 in the epitaxial structure layer 20 of the wafer to the carrier 100, before removing the second substrate 30 in the subsequent step, there is no need to turn the epitaxial structure layer 20 of the wafer onto the third substrate. When removing the second substrate 30, the carrier 100 can be used as the substrate on the first semiconductor layer side, which can save process steps and thus improve the efficiency of the wafer reconstruction process.

[0142] S470, removing the second substrate.

[0143] Specifically, in this step, the second substrate and the first bonding layer between the second substrate and the epitaxial structure layer may be removed together.

[0144] In this embodiment, a reconstructed wafer is obtained after S410 - S470 .

[0145] An embodiment of the present invention further provides a reconstructed wafer, which is reconstructed by using the wafer reconstruction method of any of the above embodiments of the present invention.

[0146] The embodiment of the present invention also provides a method for preparing a display panel. Fig.19 is a flow chart of a method for preparing a display panel provided by an embodiment of the present invention, with reference to Fig.19 , the method for preparing the display panel comprises:

[0147] S510, patterning the epitaxial structure layers of multiple chips in the reconstructed wafer to form multiple light-emitting structures.

[0148] The reconstructed wafer is obtained by using the wafer reconstruction method of any of the above embodiments of the present invention.

[0149] Fig. 20 02 is a schematic diagram of a structure after forming a light-emitting structure. After the epitaxial structure layer 20 of the wafer of the reconstructed wafer is patterned, a plurality of light-emitting structures 02 may be formed. Optionally, after patterning, the epitaxial structure layer 20 of each wafer is patterned into a plurality of light-emitting structures 02. Optionally, the cross section of the light-emitting structure 02 may be Fig. 20 The light emitting structure 02 may be a micro-light emitting device Micro-LED. An insulating layer may be provided between the light emitting structures 02.

[0150] S520 , forming a conductive connection structure on one side of the light emitting structure.

[0151] Continue to refer Fig. 20The orthographic projection of a portion of the conductive connection structure 104 on the driving substrate overlaps with the orthographic projection of the light emitting structure 02 on the driving substrate. The portion of the conductive connection structure 104 is electrically connected to the light emitting structure 02. The orthographic projection of the portion of the conductive connection structure 104 on the driving substrate is between the orthographic projections of the adjacent light emitting structure 02 on the driving substrate. When the light emitting structure 02 is bonded to the driving substrate, the conductive connection structure 104 can serve as a bonding structure.

[0152] S530 , bonding the conductive connection structure to the driving substrate.

[0153] Fig.21 This is a schematic diagram of the structure after the conductive connection structure is bonded to the drive substrate. Fig.21 After the conductive connection structure 104 is bonded to the conductive bonding structure 106 of the driving substrate 105, the light emitting structure 02 and the driving circuit in the driving substrate 105 are electrically connected through the conductive connection structure 104 and the conductive bonding structure 106, so that the driving substrate 105 can drive the light emitting structure 02. When bonding the conductive connection structure to the driving substrate, a hybrid bonding method can be used.

[0154] The method for preparing a display panel of this embodiment uses a reconstructed wafer obtained by the wafer reconstruction method of any of the above embodiments of the present invention to prepare a display panel, and has the beneficial effects of the wafer reconstruction method of any of the above embodiments of the present invention. In addition, since the reconstructed wafer obtained by the wafer reconstruction method has a larger size, it can meet the requirements of the display panel manufacturing process for the wafer size.

[0155] Based on the above embodiment, optionally, continue to refer to Fig. 20 and Fig.21 In the reconstructed wafer, the wafer includes a third substrate 102 and a first semiconductor layer 21, a light emitting layer 22, and a second semiconductor layer 23 stacked on one side of the third substrate 102; a conductive connection structure 104 is formed on a side of the second semiconductor layer 23 away from the first semiconductor layer 21. The side of the second semiconductor layer 23 away from the light emitting layer 22 may also include a current spreading layer 40, and the conductive connection structure 104 may be located on a side of the current spreading layer 40 away from the first semiconductor layer 21.

[0156] Fig. 22 is a flow chart of another method for preparing a display panel provided by an embodiment of the present invention, with reference to Fig. 22 Optionally, the method for preparing the display panel includes:

[0157] S610, patterning the epitaxial structure layers of multiple chips in the reconstructed wafer to form multiple light-emitting structures.

[0158] S620 , forming a conductive connection structure on one side of the light emitting structure.

[0159] Specifically, a conductive connection structure is formed on a side of the second semiconductor layer away from the first semiconductor layer. Fig. 20 and Fig.21 In the structure shown, when the side of the second semiconductor layer 23 away from the first semiconductor layer 21 includes the current spreading layer 40 , a conductive connection structure 104 is formed on the side of the current spreading layer 40 away from the first semiconductor layer 21 .

[0160] S630, bonding the conductive connection structure to the driving substrate.

[0161] S640, removing the third substrate.

[0162] Fig.23 is a schematic diagram of the structure after the third substrate is removed. When the third substrate is removed, the bonding layer between the third substrate and the wafer (i.e. Fig.21 The third bonding layer 103 is removed. Optionally, the material of the third substrate is silicon, and the material of the bonding layer between the third substrate and the wafer can be silicon dioxide. The third substrate and the bonding layer between the third substrate and the wafer can be removed by a chemical mechanical polishing process.

[0163] S650, performing rewiring on a side of the first semiconductor layer away from the second semiconductor layer.

[0164] Fig.24 is a schematic diagram of the structure after the first semiconductor layer is rewired away from the second semiconductor layer, refer to Fig.24 After removing the third substrate, a through hole 107 can be formed from the conductive connection structure 104 between the light emitting structures 02 to the side of the first semiconductor layer 21 away from the second semiconductor layer 23, and a conductive material is filled in the through hole 107. Then, rewiring is performed on the side of the first semiconductor layer 21 away from the second semiconductor layer 23, so that the first semiconductor layers 21 of each light emitting structure 02 are connected to each other to form a common electrode structure. During the rewiring process, a connection pad in the display panel can also be formed.

[0165] Optionally, in the above embodiments of the present invention, each chip can be used to form at least one display panel. In some optional embodiments, each chip can be used to form at least two display panels. Subsequently, the display panels corresponding to different chips can be divided, or different display panels corresponding to the same chip can be divided.

[0166] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0167] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A wafer reconstruction method, characterized in that: include: Removing the first substrate on one side of the epitaxial structure layer of the wafer to be split to obtain a first intermediate structure; The epitaxial structure layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are stacked, wherein the first semiconductor layer is located between the light emitting layer and the first substrate; and the material of the first substrate comprises gallium arsenide; dividing the first intermediate structure into a plurality of wafers; The chip is bonded to a carrier to obtain a reconstructed wafer; wherein the area of ​​the carrier is larger than the area of ​​the wafer to be divided.

2. The wafer reconstruction method according to claim 1, characterized in that: The step of removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure includes: Bonding a side of the epitaxial structure layer of the wafer to be divided away from the first substrate to a second substrate; the second substrate is made of a different material from the first substrate; The first substrate is removed.

3. The wafer reconstruction method according to claim 2, characterized in that: Before removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain the first intermediate structure, the method further includes: forming a current spreading layer on a side of the second semiconductor layer away from the first semiconductor layer; The step of bonding the epitaxial structure layer of the wafer to be divided away from the first substrate to the second substrate comprises: The current spreading layer and the second substrate are bonded by using a first bonding layer.

4. The wafer reconstruction method according to claim 3, characterized in that: The material of the second substrate is silicon, and the material of the first bonding layer is silicon dioxide.

5. The wafer reconstruction method according to any one of claims 1 to 4, characterized in that: The step of removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure includes: removing the first substrate; A plurality of ohmic contact structures are formed on a side of the first semiconductor layer away from the light-emitting layer to obtain the first intermediate structure, and the material of the ohmic contact structure is a metal material.

6. The wafer reconstruction method according to claim 2, characterized in that: The step of dividing the first intermediate structure into a plurality of wafers comprises: Using a patterning process to open an isolation groove on one side of the first semiconductor layer to form an isolation groove that at least penetrates the epitaxial structure layer; forming an insulating dielectric layer on a side of the first semiconductor layer away from the light emitting layer and on a sidewall of the isolation trench; On a side of the second substrate away from the epitaxial structure layer, cutting is performed along a cutting line to divide the first intermediate structure into a plurality of wafers; wherein the cutting line corresponds to a position of the isolation groove.

7. The wafer reconstruction method according to claim 6, characterized in that: The width of the scribe line is smaller than the width of the corresponding isolation groove.

8. The wafer reconstruction method according to claim 6, characterized in that: The distance between adjacent wafers on the carrier is greater than the width of the dicing road, and the distance between adjacent wafers on the carrier is greater than the width of the isolation groove.

9. The wafer reconstruction method according to claim 6, characterized in that: The method of using a patterning process to open an isolation groove on one side of the first semiconductor layer to form an isolation groove that at least penetrates the epitaxial structure layer includes: Using a patterning process to open an isolation on one side of the first semiconductor layer to form an isolation groove that penetrates the epitaxial structure layer and the first bonding layer between the epitaxial structure layer and the second substrate; Cutting along a cutting path on a side of the second substrate away from the epitaxial structure layer to divide the first intermediate structure into a plurality of wafers includes: The second substrate is cut along a cutting line on a side of the second substrate away from the epitaxial structure layer to divide the first intermediate structure into a plurality of wafers.

10. The wafer reconstruction method according to claim 2, characterized in that: The step of bonding the wafer to a carrier to obtain a reconstructed wafer comprises: Bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure; bonding a side of the first semiconductor layer of the second intermediate structure away from the second substrate to a third substrate; The carrier and the second substrate are removed.

11. The wafer reconstruction method according to claim 10, characterized in that: The step of bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure comprises: Bonding the second substrate of the wafer to the carrier via a second bonding layer to obtain the second intermediate structure; the second bonding layer includes a colloid; The removing the carrier and the second substrate comprises: removing the carrier and the second bonding layer; The second substrate and the first bonding layer between the second substrate and the epitaxial structure layer are removed.

12. The wafer reconstruction method according to claim 2, characterized in that: The step of bonding the wafer to a carrier to obtain a reconstructed wafer comprises: Bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier to obtain a third intermediate structure; The second substrate is removed.

13. The wafer reconstruction method according to claim 1, characterized in that: The step of bonding the wafer to a carrier to obtain a reconstructed wafer comprises: Removing defective wafers from the plurality of wafers; bonding a plurality of non-defective wafers to the carrier to obtain a reconstructed wafer; and / or Selecting a wafer with similar uniformity and consistency among multiple wafers; The side of the epitaxial structure layer of a wafer with similar uniformity and consistency among the multiple wafers, which is away from the first substrate, is bonded to a carrier to obtain a reconstructed wafer.

14. The wafer reconstruction method according to claim 1, characterized in that: The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

15. A reconstructed wafer, characterized in that: The wafer is reconstructed by using the wafer reconstruction method described in any one of claims 1 to 14.

16. A method for preparing a display panel, characterized in that: include: The epitaxial structure layers of the plurality of wafers in the reconstructed wafer are patterned to form a plurality of light-emitting structures; wherein the reconstructed wafer is obtained by the wafer reconstruction method according to any one of claims 1 to 13; forming a conductive connection structure on one side of the light emitting structure; The conductive connection structure is bonded to the driving substrate.

17. The preparation method according to claim 16, characterized in that: In the reconstructed wafer, the wafer includes a third substrate and the first semiconductor layer, the light emitting layer and the second semiconductor layer stacked on one side of the third substrate; The conductive connection structure is formed on a side of the second semiconductor layer away from the first semiconductor layer; After bonding the conductive connection structure to the drive substrate, the method further includes: removing the third substrate; Rewiring is performed on a side of the first semiconductor layer away from the second semiconductor layer.

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