PECVD deposited SiN wafer curvature compensation layer on substrate

Abstract

The invention relates to a PECVD (plasma enhanced chemical vapor deposition) method and equipment. A method of depositing silicon nitride onto a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD), a structure including a semiconductor substrate, and a PECVD apparatus for depositing silicon nitride onto a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) are provided.

Description

Technical Field

[0001] The present invention relates to a plasma enhanced chemical vapor deposition (PECVD) method, in particular to a method for depositing silicon nitride onto a semiconductor substrate by PECVD. The present invention also relates to an associated PECVD device. In addition, the present invention relates to a structure comprising a semiconductor substrate having a deposited silicon nitride layer. Background Art

[0002] Maintaining a relatively flat substrate is an important consideration during processing of semiconductor substrates. This is partly due to patterning requirements, but is also necessitated by the nature of the automated processes used to handle the substrates. As materials are removed or added to the substrate and thermally cycled, stresses can accumulate in the substrate, causing deformation of the substrate. This problem is exacerbated after the wafer thinning step because the stress of the deposited layers on the substrate causes greater deformation as the substrate thickness decreases.

[0003] It is known to balance the stress of several layers used in applications where multiple alternating layers of SiN and SiO are used to form devices, such as 3D memories. Several layers alternate between compressive and tensile stresses with the goal of balancing the net stress of many layers - perhaps more than 128 layers. Alternatively, materials can be deposited on opposite sides of the substrate to achieve a stress balancing effect. This can be achieved by conventional physical vapor deposition (PVD), chemical vapor deposition (CVD), or PECVD deposition. Compressive or tensile stress on one side of the substrate can be balanced by an equal compressive or tensile stress on the other side of the substrate.

[0004] High stress layers are highly undesirable. This is because they are prone to cracking and particle generation, which can lead to defects and reliability issues. Therefore, when using stress control layers, it is critical to carefully consider the material deposition technology and process.

[0005] In general, the front surface of a semiconductor substrate is processed to provide a number of desired structures. The front surface is sometimes referred to alternatively as the 'device surface' because the structures typically provide the desired functionality. After processing, the semiconductor substrate is typically divided by one of several known processes to provide a plurality of devices. In many cases, the structures on the device side are sensitive and the risk of damage to the structures means that contacting the device surface in the area of ​​the structures (for example, to perform further processing steps intended to reduce the stress experienced by the substrate) is not feasible. However, this stress can produce substrate warpage that may be so great that the substrate transport system and modules cannot handle the substrate without the risk of a mishandling event. Recovery from a mishandling often results in component damage and the system being vented to the atmosphere for cleaning and repair. Summary of the invention

[0006] The present invention seeks to address at least some of the above problems and needs in at least some of its embodiments. In particular, the present invention allows for the reduction of stress (stress experienced by a semiconductor substrate) using a process that does not require contact with structures formed on the front surface of the semiconductor substrate. In this way, the degree of bowing of the semiconductor substrate can be reduced.

[0007] According to a first aspect of the present invention, there is provided a method for depositing silicon nitride onto a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD), the method comprising the following steps:

[0008] Providing a semiconductor substrate having a front surface and a back surface, wherein the front surface includes a central region having one or more structures formed thereon and an edge region surrounding the central region;

[0009] positioning the front surface of the semiconductor substrate on a substrate support in a chamber, wherein the substrate support contacts only the edge region of the front surface of the semiconductor substrate; and

[0010] A silicon nitride layer stack is deposited onto the back surface of the semiconductor substrate by PECVD, wherein the silicon nitride layer stack comprises at least four silicon nitride layers alternating between tensile layers subjected to tensile stress and compressive layers subjected to compressive stress.

[0011] The silicon nitride layer stack may include at least eight silicon nitride layers. The silicon nitride layer stack may have a thickness of 3 microns or greater. The silicon nitride layer stack may have a thickness of 5 microns or greater. The silicon nitride layers may each have a thickness, and the thickness of the tensile layer may be greater than the thickness of the compressive layer. The thickness of the tensile layer may be at least twice that of the compressive layer. The thickness of the tensile layer may be at least four times that of the majority of the compressive layers. The thickness of the tensile layer may be in the range of 0.5 microns to 2.7 microns.

[0012] The silicon nitride layer stack may be deposited by PECVD using nitrogen, hydrogen, ammonia and silane as precursors. Other precursor mixtures may be used to deposit the SiN layer.

[0013] Prior to the step of depositing the silicon nitride layer stack, the semiconductor substrate may have a concave curvature when viewing the front surface of the semiconductor substrate. The silicon nitride layer stack may be deposited to reduce the concave curvature of the semiconductor substrate. The concave curvature of the semiconductor substrate may be reduced to less than 100 microns. The concave curvature of the semiconductor substrate may be reduced to about 20 microns.

[0014] The step of depositing the silicon nitride layer stack onto the rear surface of the semiconductor substrate by PECVD may be performed using a capacitively coupled parallel plate PECVD process. At least one gas inlet may be provided for introducing a gas or gas mixture into the chamber, and the semiconductor substrate may be positioned on the substrate support with the rear surface facing the at least one gas inlet. In one aspect, during the step of depositing the silicon nitride layer stack onto the rear surface of the semiconductor substrate, the plasma associated with the PECVD does not contact the front surface of the semiconductor substrate. The semiconductor substrate may have a peripheral edge, and the substrate support may contact the edge region of the front surface of the semiconductor substrate only in a region not exceeding 3 mm inward from the peripheral edge.

[0015] The semiconductor substrate may be a silicon substrate or a semiconductor wafer.

[0016] According to a second aspect of the present invention, there is provided a structure comprising:

[0017] A semiconductor substrate having a front surface and a back surface, wherein the front surface includes a central region and an edge region surrounding the central region;

[0018] one or more structures formed on the central region of the front surface of the semiconductor substrate; and

[0019] A silicon nitride layer stack is deposited onto the back surface of the semiconductor substrate, wherein the silicon nitride layer stack comprises at least four silicon nitride layers alternating between tensile layers subjected to tensile stress and compressive layers subjected to compressive stress.

[0020] The structure of the second aspect of the invention may be produced by the method according to the first aspect of the invention.

[0021] According to a third aspect of the present invention, there is provided a plasma enhanced chemical vapor deposition (PECVD) apparatus for depositing silicon nitride onto a semiconductor substrate by PECVD using the method according to the first aspect of the present invention, the apparatus comprising:

[0022] room;

[0023] a substrate support disposed within the chamber for supporting a substrate, wherein the substrate support contacts only an edge region of the substrate;

[0024] at least one gas inlet for introducing a gas or a gas mixture into the chamber;

[0025] a plasma device for generating and maintaining a plasma in the chamber; and

[0026] A controller is configured to control the apparatus to deposit a silicon nitride layer stack onto the semiconductor substrate by PECVD, wherein the silicon nitride layer stack includes at least four silicon nitride layers that alternate between tensile layers that are subjected to tensile stress and compressive layers that are subjected to compressive stress.

[0027] The plasma device may include at least one power supply device configured to supply an RF power signal to the at least one gas inlet.

[0028] For the avoidance of doubt, whenever reference is made herein to 'comprising' or 'including' and similar terms, the present invention is also to be construed as encompassing more restrictive terms such as 'consisting of' and 'consisting essentially of'.

[0029] Although the present invention has been described above, the present invention can be extended to any inventive combination of the features stated above or in the following description, drawings or claims. For example, any feature disclosed in relation to the first aspect of the present invention can be combined with any feature disclosed in relation to the second aspect of the present invention, and vice versa. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0031] Figure 1 is a schematic cross-sectional view of a PECVD apparatus;

[0032] Figure 2 is a cross-sectional view of an edge of a substrate support;

[0033] Figure 3 A semiconductor substrate having curvature is presented;

[0034] Figure 4 Shows stress and wafer bow at different thicknesses of a single SiN layer;

[0035] Figure 5 is a schematic diagram of a substrate having a stack of alternating tensile and compressive SiN layers;

[0036] Figure 6 Demonstrating the curvature of a single tensile SiN layer and the curvature of a SiN layer stack;

[0037] Figure 7 Demonstrating stress and wafer bow at different thicknesses of the SiN stack; and

[0038] Figure 8 Deflection plots extracted from a strain gauge are shown (a) before and b) after SiN stack deposition. DETAILED DESCRIPTION

[0039] Figure 1 A PECVD apparatus 1 is shown which can be used in conjunction with the present invention to process a semiconductor substrate 2. The semiconductor substrate 2 can be a silicon wafer or another suitable substrate having several structures formed on the central region of its front surface. The semiconductor substrate 2 is supported on substrate supports 3, 4. In this example, the substrate support comprises a substantially conventional wafer platen 3 having an attached metal wafer carrier 4. The wafer carrier 4 defines a central cavity having a diameter less than the diameter of the substrate 2. When processing a substrate in the form of a wafer having a diameter in the range of 150 mm to 300 mm, the central cavity may have a diameter 6 mm less than the diameter of the wafer. The substrate 2 is handled by a transport system having an edge gripping end effector (not shown) and is placed in the center of the substrate supports 3, 4 with the front (device) surface facing downward, i.e. facing the substrate supports 3, 4. The substrate 2 is held in position by a number of ceramic pins 5 located about 0.5 mm from the edge of the substrate 2. The wafer carrier 4 ensures that the substrate 2 is contacted only at its edge region, i.e., a peripheral region surrounding a central region where several structures are located. The edge region may correspond to a so-called 'edge exclusion' region, which is a peripheral band that typically extends from the edge of the wafer to an inner diameter of about 2 mm to 3 mm radially inwardly from the edge of the wafer.

[0040] The arrangement of the wafer carrier 4 avoids damage to the front surface of the substrate 2, which would otherwise be caused if a substrate having sensitive structures on its front surface were placed on a conventional wafer support 3. Such damage in turn can lead to yield losses and is therefore very undesirable. By contacting the substrate at its edge region, it is possible to safely handle the substrate and avoid damage to active and / or yielding areas of the front surface of the wafer.

[0041] We will now describe Figure 1 The other elements of the PECVD apparatus 1 of the present invention are shown in FIG. The precursor process gas passes through gas lines 6, 7 and valves 8, 9 and enters the showerhead gas inlet 10, where it expands and passes through an optional gas distribution plate 11 before entering the processing chamber 14 through a series of small openings 12 in the front surface of the showerhead 10. The exhaust gas passes through opening 13 to be removed by a pumping system (not shown). The process pressure in the chamber 14 is monitored and maintained by controlling the gas flow rate and pumping speed. In use, RF power is used to generate the plasma. The RF power is supplied by a high frequency (typically 13.56 MHz) RF power supply 15 and an associated matching unit 16 and a low frequency (typically 380 KHz) RF power supply 17 and an associated matching unit 18. The controller 19 controls the operation of the PECVD apparatus.

[0042] The substrate supports 3, 4 are grounded and resistive heating is used to control the substrate temperature. The chamber 14 is also grounded and made of aluminum or stainless steel. The showerhead 10 is made of aluminum and isolated from the chamber 14 by a ceramic break. In order to avoid the generation of unwanted plasma between the surface of the wafer carrier 4 and the front surface of the substrate 2, a gap of less than 0.7 mm is used. For the operating pressures and RF powers typically employed in ordinary use, this provides an effective dark space gap. Thus, deposition in the region of the central cavity and on the front surface of the substrate 2 is avoided.

[0043] Figure 2 Shows an adapter arrangement that can be used with a conventional wafer stage. Figure 2 In FIG. 1 , the substrate 20 is located in a raised position on the edge lift pins 22, with the central cavity 24 below the substrate 20 visible. Figure 2 In FIG. 2 , wafer carrier 26 and wafer platen 28 extend beyond the edge of substrate 20 due to the fact that the chamber used can accommodate wafers of up to 300 mm diameter. Figure 2 The adapter shown in is for 150 mm diameter wafers, but it will be appreciated that the invention is not limited to substrates of any particular size or shape. Apparatus suitable for performing the method of the invention includes an adapted SPTS Delta (RTM) PECVD system with edge contact adapter hardware, available from SPTS Technologies Limited, Newport, South Wales, United Kingdom. All exemplary examples described below are performed using this apparatus. Other PECVD systems may be used, such as other capacitively coupled parallel plate PECVD systems.

[0044] With physical contact made only on the periphery of the substrate, RF coupling to the substrate and heat transfer from the wafer support is reduced when compared to conventional wafer supports. This in turn modifies the properties of the deposited layer. Depositing highly tensile SiN using edge contact hardware is more difficult than using conventional full contact because the uneven plasma coupling tends to result in a more brittle layer with a reduced fracture threshold compared to what can be achieved using conventional planar supports. The inventors of the present case have utilized these different operating conditions to provide improved PECVD deposited SiN layers. Despite these difficulties, the inventors of the present case have devised a method to reduce concave warpage of a substrate by using a laminated SiN PECVD deposition process to achieve acceptable overall stress and acceptable bow. In some instances, concave warpage greater than 300 microns can be reduced to an acceptable bow of less than 100 microns. According to the present invention, a silicon nitride layer stack is deposited onto the back surface of a semiconductor substrate by PECVD, wherein the silicon nitride layer stack comprises at least four silicon nitride layers that alternate between tensile layers that are subjected to tensile stress and compressive layers that are subjected to compressive stress. This allows deposition to be performed to higher thicknesses and larger wafer bows to be corrected while maintaining the integrity of the structure formed on the front surface of the substrate.

[0045] Figure 3 A schematic representation of a wafer 30 is shown which is concave due to previous process steps when viewed from its front surface (device side) 30a carrying specific structures. Figure 3 As shown in FIG. 3 , the term 'concave' as used herein is understood to describe the appearance of a semiconductor substrate when viewing the front surface of the semiconductor substrate. A stack of SiN layers is deposited onto the back surface 30b of the wafer 30 by PECVD.

[0046] Examples

[0047] Two types of 150 mm diameter silicon test wafers were used: a master wafer (flat) with a warpage greater than 300 μm and a concave wafer. Wafer thickness was nominally 675 μm.

[0048] PECVD SiN film is not a pure Si3N4 layer, but is more accurately described as Si x N y H z Or SiN:H, because it contains a significant amount of H, possibly greater than 10 at%.

[0049] The high tensile stress films were deposited using the following parameters shown in Table 1:

[0050] Parameter (unit) value Pressure (torr) 2.6 Temperature(℃) 350 HF RF(kW) 15 <![CDATA[Flow rate of N2 gas (sccm)]]> 4000 <![CDATA[H2 gas flow rate (sccm)]]> 400 <![CDATA[NH3 gas flow rate (sccm)]]> 624 <![CDATA[SiH4 gas flow rate (sccm)]]> 240

[0051] Table 1: PECVD parameters for depositing tensile SiN

[0052] This resulted in the film properties shown in Table 2.

[0053] Deposition rate 425nm / min Refractive Index 1.8804 stress +436MPa Curvature (horizontal) -151μm Curvature (vertical) -150μm

[0054] Table 2: Film properties for tensile SiN at 2.7 μm

[0055] In Tables 2 and 4, the positive and negative signs of the tortuosity measurements are indicative of an increase or decrease in tortuosity deformation, respectively.

[0056] exist Figure 4 The SiN thickness on the silicon wafer using the above process conditions and edge contact hardware is compared. Wafer bow (mm) and stress (MPa) are plotted. It is well known that if the thickness increases beyond a certain value, the film begins to crack. The area below the dashed line (representing stress, marked by the black dashed line) is where the film shows no signs of cracking, and beyond those limits cracking is observed. Cracking occurs at thicknesses greater than about 2.7 μm, where a stress of +436 MPa only produces a bow of about 150 μm.

[0057] The rupture threshold is increased by depositing a stack of thin compressive SiN films and thick tensile SiN films (repeated to achieve the desired thickness and curvature requirements) to reduce the overall very high tensile stress of the SiN stack. This allows the deposited thickness to be significantly increased, exceeding the expected rupture threshold for a single tensile SiN layer at this stress. An O2 plasma treatment is used before the thin compressive SiN as an adhesion promoter. This process is proven to eliminate organic contaminants, thereby providing better layer interfaces. The process parameters for the compressive film are given in Table 3 below:

[0058] Parameter (unit) value Pressure (torr) 1.93 Temperature(℃) 350 HF RF(kW) 0.7 <![CDATA[Flow rate of N2 gas (sccm)]]> 3400 <![CDATA[H2 gas flow rate (sccm)]]> 1000 <![CDATA[NH3 gas flow rate (sccm)]]> 700 <![CDATA[SiH4 gas flow rate (sccm)]]> 350

[0059] Table 3: PECVD parameters for the deposition of compressed SiN

[0060] The film properties of the compressed SiN films can be found in Table 4.

[0061] Deposition rate 208nm / min Refractive Index 2.1104 stress -286MPa Curvature (horizontal) 5μm Curvature (vertical) 4μm

[0062] Table 4. Film properties of compressed SiN

[0063] The laminate structure used can be Figure 5 As can be seen in Figure 2, the curvature values ​​for a single tensile SiN membrane and a stack are shown in Figure 6The tensile SiN layer 52 having a thickness of 1 μm is alternated with the compressive SiN layer 53 having a thickness of 200 nm until the desired thickness and / or wafer bow requirement is achieved on the substrate 51 .

[0064] The thickness of the final compressive SiN layer 54 is 400 nm instead of 200 nm. This is done to provide an effective protective layer over the outermost tensile layer 52. The variation in thickness may allow for the desired curvature compensation. A ratio of tensile to compressive layer thickness of approximately 5 to 1 has been found to provide excellent results, with a maximum thickness of 2.5 microns at 400 MPa.

[0065] exist Figure 6 In FIG. 5 , it can be seen that the thickness of the SiN stack can exceed 6 microns, resulting in a bow of about 250 microns without breaking, while a single SiN layer breaks at a thickness of about 2.7 microns.

[0066] Figure 6 Wafer bow measured at different thicknesses using a strain gauge (FLX 3300LR) is shown. Bulk tensile SiN films exhibit larger wafer bow than stacks of alternating compressive and tensile SiN layers, since the overall bow of the stack is the sum of all layers, where the bow of the compressive layers is opposite to the bow of the tensile layers. Also marked on the graph is the critical thickness of 2.7 μm, which is the point at which micro-cracks are observed on the bulk SiN wafer. It is worth mentioning that cracks at this thickness can only be observed under a microscope, so the crack threshold for bulk SiN is less than 2.7 μm. Since the bow of the wafer is directly related to the thickness, the wafer bow increases almost linearly by further increasing the stack thickness, thereby meeting a wide range of end requirements. Available in Figure 7 The bending and stress values ​​for the SiN stack structure can be seen in Figure 2.

[0067] Figure 8 Deflection plots from a strain gauge are shown a) before stack deposition, where there is 238 μm of curvature, and b) after SiN stack deposition, where the curvature is successfully reduced to about 20 μm without cracking.

[0068] Both tensile and compressive PECVD SiN layers are deposited in the same process chamber. However, in principle, these steps can be performed in separate chambers or in a multi-wafer chamber.

Claims

1. A method for depositing silicon nitride onto a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD), the method comprising the following steps: Providing a semiconductor substrate having a front surface and a back surface, wherein the front surface includes a central region having one or more structures formed thereon and an edge region surrounding the central region; positioning the front surface of the semiconductor substrate on a substrate support in a chamber, wherein the substrate support contacts only the edge region of the front surface of the semiconductor substrate; and A silicon nitride layer stack is deposited onto the back surface of the semiconductor substrate by PECVD, wherein the silicon nitride layer stack comprises at least four silicon nitride layers alternating between tensile layers subjected to tensile stress and compressive layers subjected to compressive stress. The method of claim 1 , wherein the silicon nitride layer stack comprises at least eight silicon nitride layers.

3. The method of claim 1 or claim 2, wherein the silicon nitride layer stack has a thickness of 3 micrometers or more. The method of claim 3 , wherein the silicon nitride layer stack has a thickness of 5 micrometers or more.

5. The method of claim 1 or claim 2, wherein the silicon nitride layers each have a thickness, and the thickness of the tensile layer is greater than the thickness of the compressive layer.

6. The method of claim 1 or claim 2, wherein the tensile layer is at least twice as thick as the compressive layer.

7. The method of claim 1 or claim 2, wherein the tensile layer is at least four times thicker than a majority of the compressive layers.

8. The method of claim 1 or claim 2, wherein the thickness of the stretch layer is in the range of 0.5 microns to 2.7 microns.

9. The method according to claim 1 or claim 2, wherein the silicon nitride layer stack is deposited by PECVD using nitrogen, hydrogen, ammonia and silane as precursors.

10. The method of claim 1 or claim 2, wherein prior to the step of depositing the silicon nitride layer stack, the semiconductor substrate has a concave curvature when viewing the front surface of the semiconductor substrate.

11. The method of claim 1 or claim 2, wherein the step of depositing the silicon nitride layer stack onto the back surface of the semiconductor substrate by PECVD is performed using a capacitively coupled parallel plate PECVD process.

12. A method according to claim 1 or claim 2, wherein at least one gas inlet is provided for introducing a gas or a gas mixture into the chamber, and the semiconductor substrate is positioned on the substrate support, wherein the rear surface faces the at least one gas inlet.

13. The method of claim 1 or claim 2, wherein during the step of depositing a silicon nitride layer stack onto the back surface of the semiconductor substrate by PECVD, a plasma associated with the PECVD does not contact the front surface of the semiconductor substrate.

14. The method of claim 1 or claim 2, wherein the semiconductor substrate has a peripheral edge, and the substrate support contacts the edge region of the front surface of the semiconductor substrate only in a region no more than 3 mm inward from the peripheral edge.

15. A structure comprising: A semiconductor substrate having a front surface and a back surface, wherein the front surface includes a central region and an edge region surrounding the central region; one or more structures formed on the central region of the front surface of the semiconductor substrate; and A silicon nitride layer stack is deposited onto the back surface of the semiconductor substrate, wherein the silicon nitride layer stack comprises at least four silicon nitride layers alternating between tensile layers subjected to tensile stress and compressive layers subjected to compressive stress.

16. The structure of claim 15 produced using the method of claim 1.

17. A plasma enhanced chemical vapor deposition (PECVD) apparatus for depositing silicon nitride onto a semiconductor substrate by PECVD using the method according to claim 1, the apparatus comprising: room; a substrate support disposed within the chamber for supporting a substrate, wherein the substrate support contacts only an edge region of the substrate; at least one gas inlet for introducing a gas or a gas mixture into the chamber; a plasma device for generating and maintaining a plasma in the chamber; and A controller is configured to control the apparatus to deposit a silicon nitride layer stack onto the semiconductor substrate by PECVD, wherein the silicon nitride layer stack includes at least four silicon nitride layers that alternate between tensile layers that are subjected to tensile stress and compressive layers that are subjected to compressive stress.

18. The plasma enhanced chemical vapor deposition (PECVD) apparatus of claim 17, wherein the plasma device comprises at least one power supply device configured to supply an RF power signal to the at least one gas inlet.

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