Data processing apparatus, method of operating data processing apparatus, and electronic device

Abstract

The embodiment of the invention provides a data processing device, an operation method thereof and electronic equipment. The data processing apparatus includes: a sensor configured to generate a voltage signal or a current signal based on a collected external signal; the oscillator is coupled with the sensor, and the oscillator is configured to generate an input pulse signal based on the voltage signal or the current signal; and the neural network processor is coupled to the oscillator, and the neural network processor is configured to process the input pulse signal to generate an output pulse signal.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of data processing hardware, and more particularly to a data processing device and an operating method thereof, and an electronic device. Background Art

[0002] A neural network is a computing system that performs inferences and learns patterns in data by processing continuous signals with configurable circuit parameters, often without task-specific programming. For example, a neural network can learn to recognize an object in a picture or image.

[0003] In recent years, with the advancement of neuromorphic computing and bionic sensing technology, spiking neural networks (SNNs) have been widely studied to simulate the cerebral cortex. SNNs have the characteristics of high speed and low power consumption on dedicated hardware. Therefore, how to improve the integration and compatibility of spiking neural network related hardware has become an urgent problem to be solved in the industry. Summary of the invention

[0004] The present disclosure provides a data processing device and an operating method thereof, and an electronic device.

[0005] In a first aspect, the present disclosure provides a data processing device, comprising:

[0006] A sensor, wherein the sensor is configured to: generate a voltage signal or a current signal based on a collected external signal;

[0007] an oscillator, the oscillator being coupled to the sensor, the oscillator being configured to: generate an input pulse signal based on the voltage signal or the current signal;

[0008] A neural network processor is coupled to the oscillator, and the neural network processor is configured to: process the input pulse signal to generate an output pulse signal.

[0009] In some embodiments, the oscillator comprises:

[0010] a current control circuit, the current control circuit being coupled to an input terminal of the oscillator and an output node of the oscillator respectively, the current control circuit being configured to: control a control current flowing through the output node based on the voltage signal or the current signal;

[0011] A gate, the gate being coupled to the output node and the voltage terminal respectively, and the gate being configured to: control the output node to charge or discharge based on the control current and the voltage provided by the voltage terminal to generate the input pulse signal;

[0012] A regulating circuit is coupled between the voltage terminal and the current control circuit, and is configured to: regulate characteristic parameters of the input pulse signal, wherein the characteristic parameters include at least one of amplitude and frequency.

[0013] In some embodiments, the regulating circuit comprises:

[0014] a first sub-regulating circuit, the first sub-regulating circuit being coupled between the current control circuit and the output node, the first sub-regulating circuit being configured to: regulate the amplitude of the input pulse signal;

[0015] The second sub-regulation circuit is connected in parallel with the gate between the voltage terminal and the output node, and the second sub-regulation circuit is configured to: regulate the frequency of the input pulse signal.

[0016] In some embodiments, the first sub-regulation circuit includes at least one adjustable resistor; and the second sub-regulation circuit includes at least one adjustable capacitor.

[0017] In some embodiments, the current control circuit includes a current mirror circuit, the current mirror circuit includes a plurality of branches connected in parallel, and the plurality of branches are coupled to the output node; the branch includes at least one control transistor, and the gate of the control transistor is used to receive a control signal;

[0018] The current control circuit is further configured to: based on the control signal, turn on the corresponding branch to control the control current flowing through the output node.

[0019] In a second aspect, the present disclosure provides an operating method of a data processing device, comprising:

[0020] Generate a voltage signal or a current signal based on the collected external signal;

[0021] generating an input pulse signal based on the voltage signal or the current signal;

[0022] The input pulse signal is processed to generate an output pulse signal.

[0023] In some embodiments, generating an input pulse signal based on the voltage signal or the current signal includes:

[0024] Based on the voltage signal or the current signal, controlling a control current flowing through an output node;

[0025] Based on the control current and the voltage provided by the voltage terminal, controlling the output node to charge or discharge to generate the input pulse signal;

[0026] Adjust the characteristic parameters of the input pulse signal, wherein the characteristic parameters include at least one of amplitude and frequency.

[0027] In some embodiments, adjusting the characteristic parameter of the input pulse signal includes:

[0028] The amplitude of the input pulse signal is adjusted by at least one adjustable resistor; and / or the frequency of the input pulse signal is adjusted by at least one adjustable capacitor.

[0029] In some embodiments, controlling the control current flowing through the output node based on the voltage signal or the current signal includes:

[0030] Based on the control signal, the corresponding branch in the current mirror circuit is turned on to control the control current flowing through the output node; wherein the current mirror circuit includes a plurality of branches connected in parallel, and the plurality of branches are all coupled to the output node.

[0031] In a third aspect, the present disclosure provides an electronic device, comprising the data processing device described in any one of the above embodiments.

[0032] In the disclosed embodiment, the oscillator generates an input pulse signal based on a voltage signal or a current signal generated by a sensor, and the neural network processor processes the input pulse signal to generate an output pulse signal. In other words, the oscillator can generate an input pulse signal based on a received voltage signal, or can generate an input pulse signal based on a received current signal. In this way, on the one hand, the data processing device can be adapted to piezoelectric sensors and resistance sensors at the same time, and has good compatibility; on the other hand, the oscillator can realize the function of an artificial afferent neuron, which is conducive to improving the integration of the data processing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a data processing device provided in an embodiment of the present disclosure;

[0034] Figure 2 A schematic diagram of an oscillator in a data processing device provided by an embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram of a current control circuit and a regulating circuit in a data processing device provided by an embodiment of the present disclosure;

[0036] Figure 4 A flowchart of a method for operating a data processing device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0038] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0039] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0040] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0042] In some embodiments, bionic intelligent robots have received extensive attention due to the advancement of neuromorphic computing and bionic sensing technology. Bionic intelligent robots are mainly designed to simulate biological perception systems, with the characteristics of effective information processing and rapid response. The biological perception system consists of sensory receptors, afferent neurons, and cerebral cortex. Spiking neural networks are a computational model that imitates the structure and function of biological perception and nervous systems.

[0043] Spiking neural networks have been widely studied to simulate the cerebral cortex. Resistive random access memory (RRAM), phase change memory (PCM), ferroelectric field effect transistors (FeFETs) and semiconductor nanotransistors are considered to be important components of artificial spiking neural networks due to their synaptic plasticity.

[0044] Unlike the pulse signals required by spiking neural networks, external stimuli such as light, sound, smell, and pressure are usually transmitted in the form of continuous analog signals. Therefore, it is necessary to design artificial afferent neurons that convert continuous analog signals into pulse signals to facilitate information transmission between bionic sensors and spiking neural networks. Specifically, afferent neurons are mainly responsible for converting analog signals received by sensors (such as external images, sounds, and temperature) into pulse signals.

[0045] In some embodiments, a ring oscillator can be used as an afferent neuron to convert the voltage signal output by the piezoelectric sensor into a pulse signal to drive the synaptic device. However, the ring oscillator usually requires a large number of metal oxide semiconductor field effect transistors, and the circuit structure is extremely complex, which limits the application of afferent neurons in high-density neuromorphic smart chips. In addition, the above-mentioned ring oscillator can only receive voltage signals but not current signals, so it is only applicable to piezoelectric sensors and cannot be adapted to resistive sensors.

[0046] like Figure 1 As shown, the present disclosure provides a data processing device 100, including: a sensor 110, wherein the sensor 110 is configured to generate a voltage signal V1 or a current signal I1 based on a collected external signal; an oscillator 120, wherein the oscillator 120 is coupled to the sensor 110, wherein the oscillator 120 is configured to generate an input pulse signal S1 based on the voltage signal V1 or the current signal I1; and a neural network processor 130, wherein the neural network processor 130 is coupled to the oscillator 120, wherein the neural network processor 130 is configured to process the input pulse signal S1 to generate an output pulse signal S2.

[0047] In the embodiment of the present disclosure, the data processing device 100 may include any relevant circuits and hardware for constructing a spiking neural network. In a spiking neural network, information transmission between neurons is not through continuous analog signals, but through discrete pulse signals. Exemplarily, the data processing device 100 may include a sensor 110, an oscillator 120, and a neural network processor 130.

[0048] The sensor 110 is used to collect external signals to generate a voltage signal V1 or a current signal I1. Exemplarily, the sensor 110 includes but is not limited to a piezoelectric sensor, a resistance sensor, a temperature sensor, an acoustic sensor, an image sensor, and the like. In this way, the sensor 110 can generate analog signals including a voltage signal V1 and a current signal I1 based on the collected external signals such as pressure, displacement, acceleration, audio, and image. It is understandable that the sensor 110 can also be replaced by any data / information input unit and used to passively receive data / information to be processed (not used to actively collect data / information), for example, to receive image information, audio information, and the like to be processed.

[0049] The oscillator 120 is used to convert the voltage signal V1 or current signal I1 output by the sensor 110 into an input pulse signal S1 to realize the function of afferent neurons. It should be noted that conventional oscillators generally generate oscillation signals (i.e., pulse signals) based on digital inverter circuits or coupled inductive capacitor circuits, which require a large area, and conventional oscillators are usually used to convert received current signals into pulse signals, and cannot adapt to piezoelectric sensors that output voltage signals. The oscillator 120 in the present disclosure can realize the oscillation function by components such as a gate, so the voltage signal V1 can be converted into an input pulse signal S1, and the current signal I1 can be converted into an input pulse signal S1, so as to adapt to piezoelectric sensors and resistance sensors at the same time.

[0050] The neural network processor 130 is used to process the input pulse signal S1 to generate an output pulse signal S2. The neural network processor 130 includes but is not limited to a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a microcontroller (MCU), a microprocessor, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The neural network processor 130 can be used to run a pulse neural network model, thereby training the neural network model based on external information, or performing calculations based on external information to generate corresponding results. Exemplarily, the neural network processor 130 can be used to implement multiple spiking neurons in a spiking neural network. For example, the spiking neuron receives the input pulse signal S1 generated by the oscillator 120 (afferent neuron), performs weighted summation through synaptic weights, and transmits the output pulse signal S2 to the next level of spiking neuron when the membrane potential of the spiking neuron exceeds a threshold. It should be noted that the output pulse signal S2 can be output to the neural network processor 130 or to other neural network processors, and the present disclosure does not impose too many restrictions.

[0051] It is understandable that the oscillator 120 in the present disclosure can generate the input pulse signal S1 based on the received voltage signal V1, or can generate the input pulse signal S1 based on the received current signal I1. In this way, on the one hand, the data processing device 100 can be adapted to both the piezoelectric sensor and the resistance sensor, and has good compatibility; on the other hand, the oscillator 120 can realize the function of the artificial afferent neuron by components such as the gate, which is conducive to improving the integration of the data processing device 100.

[0052] In some embodiments, the data processing device 100 may include multiple sensors 110 and multiple oscillators 120 . The connection relationship between the oscillators 120 and the sensors 110 may be one-to-one or one-to-many, and the present disclosure does not impose any additional limitations.

[0053] In some embodiments, Figure 2As shown, the oscillator 120 includes: a current control circuit 121, the current control circuit 121 is respectively coupled to the input terminal N1 of the oscillator 120 and the output node N2 of the oscillator 120, and the current control circuit 121 is configured to: control the control current I2 flowing through the output node N2 based on the voltage signal V1 or the current signal I1; a gate 122, the gate 122 is respectively coupled to the output node N2 and the voltage terminal Vin, and the gate 122 is configured to: control the charging or discharging of the output node N2 based on the control current I2 and the voltage provided by the voltage terminal to generate the input pulse signal S1; an adjustment circuit 123, the adjustment circuit 123 is coupled between the voltage terminal Vin and the current control circuit 121, and the adjustment circuit 123 is configured to: adjust the characteristic parameters of the input pulse signal S1, and the characteristic parameters include at least one of amplitude and frequency.

[0054] In the embodiment of the present disclosure, the oscillator 120 includes a current control circuit 121, a gate 122 and a regulating circuit 123. The current control circuit 121 is used to regulate the control current I2 flowing through the output node N2 based on the continuous voltage signal V1 or the continuous current signal I1, where the control current I2 is proportional to the current flowing through the gate 122. Exemplarily, the current control circuit 121 can be implemented by circuits such as a current mirror circuit and a discharge circuit.

[0055] The gate 122 switches back and forth between the on state and the off state based on the control current I2 and the voltage provided by the voltage terminal, thereby controlling the output node N2 to charge or discharge to generate an oscillation signal, that is, the input pulse signal S1. Exemplarily, the gate 122 includes any one of an ovonic threshold switching (OTS), a tunnel diode, a polysilicon diode, a varistor type selector, a selector based on doped chalcogenide, and a selector based on doped hafnium oxide. In a specific embodiment, the gate 122 is a bidirectional threshold switch, and the material of the gate 122 includes Zn a Te b ,Ge a Te b , Nb a O b Or Si a As b Te c etc., where a, b, and c represent stoichiometric numbers.

[0056] The regulating circuit 123 is coupled between the voltage terminal Vin and the current control circuit 121. The regulating circuit 123 may include a plurality of sub-circuits, each of which may be composed of devices such as capacitors and resistors. The regulating circuit 123 may be used to adjust the characteristic parameters of the input pulse signal S1. For example, the regulating circuit 123 may include at least one resistor connected in series with the current control circuit 121 to adjust the voltage of the output node N2, that is, the amplitude of the input pulse signal S1; or, the regulating circuit 123 may include at least one capacitor connected in parallel with the gate 122 to adjust the frequency of the input pulse signal S1. In other embodiments, the regulating circuit 123 may also include other components, such as transistors, diodes, etc., and be used to adjust the characteristic parameters of the input pulse signal S1, such as the pulse width and duty cycle.

[0057] In this way, the oscillator 120 can generate an oscillation signal (i.e., the input pulse signal S1) through the gate 122, which has the advantages of simple structure, easy implementation, high integration, etc. In addition, the adjustment circuit 123 can also adjust the characteristic parameters of the input pulse signal S1 to flexibly meet the actual application requirements of the pulse neural network.

[0058] In some embodiments, Figure 3 As shown, the current control circuit 121 includes a current mirror circuit, which includes a plurality of branches 124 connected in parallel, and the plurality of branches 124 are all coupled to the output node N2; the branch 124 includes at least one control transistor 125, and the gate of the control transistor 125 is used to receive a control signal C1; the current control circuit 121 is also configured to: based on the control signal C1, turn on the corresponding branch 124 to control the control current I2 flowing through the output node N2.

[0059] In the embodiment of the present disclosure, the current control circuit 121 includes a current mirror circuit, and the gate 122 includes a bidirectional threshold switch. The current mirror circuit is used to receive the voltage signal V1 or the current signal I1, and generate the control current I2 based on the voltage signal V1 or the current signal I1. It can be understood that the magnitude of the control current I2 determines the magnitude of the frequency of the input pulse signal S1.

[0060] Exemplarily, the current mirror circuit amplifies or reduces the current signal I1 in proportion to the required control current I2 for output, that is, I2=n×I1, where n can be greater than 1, less than 1 or equal to 1, and the output control current I2 is connected to one end of the gate 122 connected to the output node N2, thereby realizing the control of the magnitude of the current flowing through the gate 122. It should be noted that once the current magnitude of the current signal I1 is determined, the output control current I2 is a steady current. In addition, the current mirror circuit can also generate the control current I2 based on the voltage signal V1, and the current magnitude of the control current I2 changes with the voltage magnitude of the voltage signal V1. It should be noted that once the voltage magnitude of the voltage signal V1 is determined, the output control current I2 is a steady current. In this way, the current mirror circuit can generate the control current I2 based on the received analog signal (voltage signal V1 or current signal I1).

[0061] In some embodiments, the voltage provided by the voltage terminal Vin is greater than the threshold voltage of the gate 122, and the control current I2 output by the current mirror circuit is greater than the threshold current of the gate 122 and less than the holding current Ihold of the gate 122. When the voltage across the gate 122 is greater than the threshold voltage, the gate 122 switches from the off state to the on state, and after the on state, the voltage across the gate 122 drops sharply. Under the control of the current mirror circuit, the control current I2 flowing through the gate 122 is greater than the threshold current of the gate 122 and less than the holding current of the gate 122; when the voltage across the gate 122 drops to less than the threshold voltage, the gate 122 switches from the on state to the off state, and when the gate 122 is in the off state, the voltage across the gate 122 rises to greater than the threshold voltage, and the gate 122 switches from the off state to the on state again. In this way, the gate 122 is repeatedly turned on and off under the combined effect of the control current I2 and the voltage provided by the voltage terminal Vin to control the charging or discharging of the output node N2, thereby outputting an oscillation signal, namely, the input pulse signal S1.

[0062] In some embodiments, the current mirror circuit includes a plurality of branches 124 connected in parallel, and the output node N2 is coupled to each branch 124. For example, Figure 3As shown, each branch 124 includes at least one control transistor 125, and the gate of the control transistor 125 is used to receive the control signal C1, where the control signal C1 can be generated by the neural network processor 130 or other logic circuits. Multiple control signals C1 correspond to a branch 124 respectively, and are used to control the branch 124 to be turned on. In this way, at least one branch 124 among the multiple branches 124 can be turned on in response to the corresponding control signal C1, so that the size of the control current I2 can be adjusted. In other words, the present disclosure can control the corresponding branch 124 to be turned on through one or more control signals C1, thereby adjusting the size of the control current I2.

[0063] In some embodiments, the number of control transistors 125 in any two branches 124 is different; and / or the resistance values ​​of the control transistors 125 in any two branches 124 are different. In this way, the resistance values ​​of any two branches 124 when turned on can be different, which is conducive to more flexible adjustment of the control current I2 to adjust the characteristic parameters of the input pulse signal S1.

[0064] In some embodiments, Figure 3 As shown, the regulating circuit 123 includes: a first sub-regulating circuit 126, the first sub-regulating circuit 126 is coupled between the current control circuit 121 and the output node N2, and the first sub-regulating circuit 126 is configured to: adjust the amplitude of the input pulse signal S1; a second sub-regulating circuit 127, the second sub-regulating circuit 127 is connected in parallel with the gate 122 between the voltage terminal Vin and the output node N2, and the second sub-regulating circuit 127 is configured to: adjust the frequency of the input pulse signal S1.

[0065] In the embodiment of the present disclosure, the first sub-regulation circuit 126 is connected in series between the current control circuit 121 and the output node N2. The first sub-regulation circuit 126 may include devices such as resistors and transistors. The first sub-regulation circuit 126 may adjust the voltage of the output node N2 through the series voltage division effect, thereby adjusting the amplitude of the input pulse signal S1. It is understandable that the first sub-regulation circuit 126 may include one or more resistors, and one or more transistors and other devices. Multiple resistors and multiple transistors may be arranged in series or in parallel to meet the designed resistance value.

[0066] The second sub-regulation circuit 127 is connected in parallel with the gate 122 between the voltage terminal Vin and the output node N2. The second sub-regulation circuit 127 may include devices such as capacitors and transistors. The second sub-regulation circuit 127 may use the parasitic capacitance of the capacitor or transistor to adjust the charging and discharging rate of the output node N2, thereby adjusting the frequency (period) of the input pulse signal S1. It is understandable that the second sub-regulation circuit 127 may include one or more capacitors and one or more transistors. Multiple capacitors and multiple transistors may be arranged in series or in parallel to meet the designed capacitance.

[0067] In some embodiments, the regulating circuit 123 may further include a third sub-regulating circuit ( Figure 3 Similar to the first sub-regulation circuit 126, the third sub-regulation circuit may also include components such as resistors and transistors. The third sub-regulation circuit may regulate the voltage of the output node N2 through a series voltage division effect, thereby regulating the amplitude of the input pulse signal S1.

[0068] In some embodiments, Figure 3 As shown, the first sub-regulation circuit 126 includes at least one adjustable resistor; and the second sub-regulation circuit 127 includes at least one adjustable capacitor.

[0069] In the embodiment of the present disclosure, the first sub-regulation circuit 126 may include at least one adjustable resistor, so as to more flexibly adjust the amplitude of the input pulse signal S1. Exemplarily, the adjustable resistor may be implemented by a MOS resistor. The second sub-regulation circuit 127 may include at least one adjustable capacitor, so as to more flexibly adjust the frequency of the input pulse signal S1. Exemplarily, the adjustable capacitor may be implemented by a MOS capacitor. In this way, the MOS resistor and the MOS capacitor may further reduce the occupied area of ​​the oscillator 120 and improve the integration of the data processing device 100.

[0070] In summary, the data processing device provided by the present disclosure can utilize the relaxation resonance of the gate (such as a bidirectional threshold switch) to realize the transformation of a continuous voltage signal or a continuous current signal into a pulse signal (i.e., an input pulse signal), thereby simulating the basic functions of artificial afferent neurons; and due to the high-density integration characteristics of the gate, the application of electronic afferent neurons in high-density neuromorphic smart chips can be solved. Secondly, since the gate can realize a high-density array architecture, the artificial afferent neurons based thereon can realize the characteristics of a higher integration density. Finally, the artificial neurons based on the gate can not only receive voltage signals, but also current signals, so they can be adapted to piezoelectric sensors and resistive sensors at the same time, and have good compatibility.

[0071] like Figure 4 As shown, the present disclosure provides an operating method of a data processing device, comprising the following steps:

[0072] Step S10: generating a voltage signal or a current signal based on the collected external signal;

[0073] Step S20, generating an input pulse signal based on the voltage signal or the current signal;

[0074] Step S30: Process the input pulse signal to generate an output pulse signal.

[0075] It should be understood that Figure 4 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 4 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0076] The present disclosure can generate an input pulse signal based on a received voltage signal or a received current signal, so that it can be adapted to both piezoelectric sensors and resistance sensors, and has good compatibility.

[0077] In some embodiments, the generating of the input pulse signal based on the voltage signal or the current signal includes: controlling the control current flowing through the output node based on the voltage signal or the current signal; controlling the charging or discharging of the output node based on the control current and the voltage provided by the voltage terminal to generate the input pulse signal; and adjusting the characteristic parameters of the input pulse signal, wherein the characteristic parameters include at least one of amplitude and frequency.

[0078] In some embodiments, adjusting the characteristic parameters of the input pulse signal includes: adjusting the amplitude of the input pulse signal through at least one adjustable resistor; and / or adjusting the frequency of the input pulse signal through at least one adjustable capacitor.

[0079] In some embodiments, controlling the control current flowing through the output node based on the voltage signal or the current signal includes: based on the control signal, turning on the corresponding branch in the current mirror circuit to control the control current flowing through the output node; wherein the current mirror circuit includes a plurality of the branches connected in parallel, and the plurality of the branches are all coupled to the output node.

[0080] The present disclosure provides an electronic device, comprising the data processing device according to any one of the above embodiments.

[0081] The data processing device involved in the embodiments of the present disclosure can be used in various electronic devices. The electronic device can be implemented by one or more application-specific integrated circuits (ASICs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, memories, and other electronic components. Electronic devices include, but are not limited to, mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, and any other suitable electronic devices.

[0082] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0083] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0084] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A data processing device, characterized in that: include: A sensor, wherein the sensor is configured to: generate a voltage signal or a current signal based on a collected external signal; an oscillator, the oscillator being coupled to the sensor, the oscillator being configured to: generate an input pulse signal based on the voltage signal or the current signal; A neural network processor is coupled to the oscillator, and the neural network processor is configured to: process the input pulse signal to generate an output pulse signal.

2. The data processing device according to claim 1, characterized in that: The oscillator comprises: a current control circuit, the current control circuit being coupled to an input terminal of the oscillator and an output node of the oscillator respectively, the current control circuit being configured to: control a control current flowing through the output node based on the voltage signal or the current signal; A gate, the gate being coupled to the output node and the voltage terminal respectively, and the gate being configured to: control the output node to charge or discharge based on the control current and the voltage provided by the voltage terminal to generate the input pulse signal; A regulating circuit is coupled between the voltage terminal and the current control circuit, and is configured to: regulate characteristic parameters of the input pulse signal, wherein the characteristic parameters include at least one of amplitude and frequency.

3. The data processing device according to claim 2, characterized in that: The regulating circuit comprises: a first sub-regulating circuit, the first sub-regulating circuit being coupled between the current control circuit and the output node, the first sub-regulating circuit being configured to: regulate the amplitude of the input pulse signal; The second sub-regulation circuit is connected in parallel with the gate between the voltage terminal and the output node, and the second sub-regulation circuit is configured to: regulate the frequency of the input pulse signal.

4. The data processing device according to claim 3, characterized in that: The first sub-regulation circuit includes at least one adjustable resistor; the second sub-regulation circuit includes at least one adjustable capacitor.

5. The data processing device according to claim 2, characterized in that: The current control circuit includes a current mirror circuit, the current mirror circuit includes a plurality of branches connected in parallel, and the plurality of branches are all coupled to the output node; the branch includes at least one control transistor, and the gate of the control transistor is used to receive a control signal; The current control circuit is further configured to: based on the control signal, turn on the corresponding branch to control the control current flowing through the output node.

6. A method for operating a data processing device, characterized in that: include: Generate a voltage signal or a current signal based on the collected external signal; generating an input pulse signal based on the voltage signal or the current signal; The input pulse signal is processed to generate an output pulse signal.

7. The operating method according to claim 6, characterized in that: The step of generating an input pulse signal based on the voltage signal or the current signal comprises: Based on the voltage signal or the current signal, controlling a control current flowing through an output node; Based on the control current and the voltage provided by the voltage terminal, controlling the output node to charge or discharge to generate the input pulse signal; Adjust the characteristic parameters of the input pulse signal, wherein the characteristic parameters include at least one of amplitude and frequency.

8. The operating method according to claim 7, characterized in that: The step of adjusting the characteristic parameters of the input pulse signal comprises: The amplitude of the input pulse signal is adjusted by at least one adjustable resistor; and / or the frequency of the input pulse signal is adjusted by at least one adjustable capacitor.

9. The operating method according to claim 7, characterized in that: The controlling the control current flowing through the output node based on the voltage signal or the current signal includes: Based on the control signal, the corresponding branch in the current mirror circuit is turned on to control the control current flowing through the output node; wherein the current mirror circuit includes a plurality of branches connected in parallel, and the plurality of branches are all coupled to the output node.

10. An electronic device, characterized in that: A data processing device comprising any one of claims 1 to 5.

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