Semiconductor structure and forming method thereof
By designing closely arranged column and trench structures in the semiconductor structure, forming multi-layer stacked electrode layers and dielectric layers, the problem of difficulty in designing interconnect plugs by multi-layered electrode plates is solved, and high integration and low Cost semiconductor structure.
Patent Information
- Application Number
- CN202310945583.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-28
- Publication Date
- 2025-02-14
AI Technical Summary
As the number of layers of deep trench capacitors increases, the design of multi-layer plate-induced interconnect plugs becomes difficult, affecting the integration of the semiconductor structure.
A semiconductor structure is designed in which multiple columns are closely arranged, and trenches are formed between adjacent columns, forming a multi-layer stacked electrode layer and dielectric layer. The electrode layer covers the trench and the column surface and fills the trench. The dielectric layer is located at between adjacent electrode layers.
Through the tightly arranged column and trench structure, the area occupied is saved, the integration of the semiconductor structure is improved, and the electrical connection of the multi-layer electrode layer is simplified, reducing the formation cost.
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Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] Deep Trench Capacitor (DTC) is widely used in antenna matching, RF filtering and IC decoupling, especially in applications with height and volume restrictions. It has very high stability and extremely low leakage current under high bias voltage, and plays a vital role in some industrial fields.
[0003] Silicon-based capacitors are replacing ceramic capacitors in the smartphone AP and PMIC terminal markets with their irreplaceable advantages such as miniaturization, high stability, and low ESR / ESL. High-density DTCs increase the effective area of capacitors through three-dimensional structural design, thereby increasing capacitance density.
[0004] The most common design at present is a planar structure with vertical slots parallel or perpendicular to each other. The area of the capacitor unit cell is changed by changing the length of the vertical slots, and then the structure with different customer requirements is constructed by connecting the unit cells in parallel. In this structural design, the interconnect plug (CT) is generally located outside the cell by etching the electrode plate to expose the lower electrode plate for leading out the CT.
[0005] As the number of DTC layers increases, the number of electrode layers will also increase, and the design of CT leads with multiple electrode layers will become difficult. Summary of the invention
[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to saving occupied area and improving the integration of the semiconductor structure.
[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a plurality of pillars protruding from the substrate, the top view of the pillars is a polygon, and the sides of adjacent pillars are arranged relatively; a plurality of grooves, each groove surrounds a pillar, and the plurality of grooves are connected; a plurality of stacked electrode layers, in which the bottom electrode layer covers the surfaces of the grooves and the surfaces of the pillars, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, and the plurality of electrode layers fill the grooves; a dielectric layer, located between adjacent electrode layers.
[0008] Optionally, a plurality of columns extending along a first direction constitute a column group, the plurality of columns include a plurality of column groups arranged in parallel along a second direction, the number of electrode layers is n, and in the n adjacent column groups, the surface of each electrode layer in the n electrode layers is exposed on the columns of each column group, and the first direction is perpendicular to the second direction.
[0009] Optionally, among the n adjacent column groups, the surfaces of the first to nth electrode layers are exposed in sequence on the column groups arranged in sequence along the second direction.
[0010] Optionally, the semiconductor structure also includes: a plurality of interconnection plugs, which are located on the electrode layer exposed on the pillars and electrically connected to the corresponding electrode layers; a plurality of interconnection lines, which extend along a first direction and are located on top of the interconnection plugs on the corresponding pillar groups, and the interconnection lines located on top of the interconnection plugs on the same electrode layer are connected in parallel.
[0011] Optionally, among the plurality of interconnection lines, interconnection lines located on top of interconnection plugs of electrode layers spaced apart from each other are connected in parallel.
[0012] Optionally, the top view polygon of the column is a hexagon.
[0013] Optionally, the semiconductor structure further includes: a through-hole interconnection structure; a plurality of columns forming a hexagonal honeycomb-shaped column unit, and the plurality of column units forming a ring structure surrounding the through-hole interconnection structure.
[0014] Optionally, the dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; the material of the electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.
[0015] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate and a material layer located on the substrate; forming a plurality of grooves penetrating the material layer, and the remaining material layer forms a plurality of pillars protruding from the substrate, the top view of the pillars is a polygon, the sides of adjacent pillars are arranged relatively to each other, each groove surrounds the pillar, and the plurality of grooves are connected; forming a plurality of stacked electrode layers and dielectric layers, wherein the bottom electrode layer of the multi-layer electrode layer covers the surfaces of the grooves and the surfaces of the pillars, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, the multi-layer electrode layers fill the grooves, and the dielectric layers are located between adjacent electrode layers.
[0016] Optionally, in the step of forming columns, a plurality of columns extending along a first direction constitute a column group, and the plurality of columns include a plurality of column groups arranged in parallel along a second direction, and the first direction is perpendicular to the second direction; in the step of forming electrode layers, the number of electrode layers is n, and in the n adjacent column groups, the surface of each electrode layer in the n electrode layers is exposed on the columns of each column group.
[0017] Optionally, in the step of forming the electrode layer, among the n adjacent column groups, the surfaces of the first to n electrode layers are exposed in sequence on the column groups arranged in sequence along the second direction.
[0018] Optionally, the step of forming a multi-layer stacked electrode layer includes: forming n electrode material layers stacked in sequence; etching back part of the electrode material layer so that in n adjacent column groups, the surface of each electrode layer in the n electrode layers is exposed on the columns of each column group.
[0019] Optionally, after forming a multi-layer stacked electrode layer and a dielectric layer, the formation method also includes: forming a plurality of interconnection plugs, which are located on the electrode layer exposed on the pillars and are electrically connected to the corresponding electrode layers; forming a plurality of interconnection lines on top of the interconnection plugs, the interconnection lines extending along a first direction and located on top of the interconnection plugs on the corresponding pillar groups, and the interconnection lines located on top of the interconnection plugs on the same electrode layer are connected in parallel.
[0020] Optionally, in the step of forming a plurality of interconnection lines, the interconnection lines located on top of the interconnection plugs of the electrode layers spaced apart from each other are connected in parallel.
[0021] Optionally, in the step of forming a plurality of columns, the top-view polygonal shape of the columns is a hexagon.
[0022] Optionally, in the step of providing a substrate, a through-hole interconnection structure penetrating the material layer is formed in the material layer; in the step of forming a plurality of columns, the plurality of columns constitute a hexagonal honeycomb-shaped column unit, and the plurality of column units form a ring structure surrounding the through-hole interconnection structure.
[0023] Optionally, in the step of forming a multi-layer stack of electrode layers and dielectric layers, each electrode layer and dielectric layer is formed by an atomic layer deposition process.
[0024] Optionally, in the step of forming a multi-layer stacked electrode layer and a dielectric layer, the dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN, and the material of the electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.
[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0026] In the semiconductor structure provided by the embodiment of the present invention, a plurality of pillars protrude from the substrate, the top view morphology of the pillars is a polygon, the sides of adjacent pillars are arranged relatively, each of the plurality of grooves surrounds the pillar, the plurality of grooves are connected, and in the multi-layer electrode layer, the bottom electrode layer covers each surface of the groove and the surface of the pillar, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, and the multi-layer electrode layer fills the groove; in the embodiment of the present invention, the top view morphology of the pillars is a polygon, the sides of adjacent pillars are arranged relatively, each of the plurality of grooves surrounds the pillar, and the plurality of grooves are connected, then the plurality of pillars are closely arranged, and grooves can be formed between adjacent pillars to provide spatial positions for capacitors formed by the electrode layers, thereby increasing the flexibility of the arrangement of the capacitor structure, and forming a deep trench capacitor (DTC) structure between the closely arranged adjacent pillars, which is beneficial to saving the occupied area and improving the integration of the semiconductor structure.
[0027] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a plurality of grooves are formed through the material layer, and the remaining material layer forms a plurality of columns protruding from the substrate. The top view morphology of the column is a polygon, and the sides of adjacent columns are arranged relatively, each groove surrounds the column, and multiple grooves are connected to form a multi-layer stacked electrode layer and a dielectric layer. In the multi-layer electrode layer, the bottom electrode layer covers each surface of the groove and the surface of the column, and the remaining electrode layers are stacked in sequence on the bottom electrode layer. The multi-layer electrode layer fills the groove, and the dielectric layer is located between adjacent electrode layers; in the embodiment of the present invention, the top view morphology of the column is a polygon, and the sides of adjacent columns are arranged relatively, each groove in the multiple grooves surrounds the column, and the multiple grooves are connected, so that the multiple columns are closely arranged, and grooves can be formed between adjacent columns to provide spatial positions for capacitors formed by the electrode layer, thereby increasing the flexibility of the arrangement of the capacitor structure, and forming a deep trench capacitor structure between closely arranged adjacent columns, which is beneficial to saving occupied area and improving the integration of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 to Figure 2 It is a schematic diagram of the structure of a semiconductor structure;
[0029] Figures 3 to 6 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;
[0030] Figures 7 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0031] At present, the integration level of semiconductor structures needs to be improved. The reasons why the integration level needs to be improved are analyzed in combination with a semiconductor structure.
[0032] Figure 1 to Figure 2It is a structural diagram of a semiconductor structure.
[0033] Combined with reference Figure 1 to Figure 2 , Figure 2 for Figure 1 A cross-sectional view of one of the trenches, the semiconductor structure comprises: a substrate (not shown), a first direction (such as Figure 1 The device region includes a device region and lead regions on both sides of the device region; a plurality of grooves 20 located in the substrate of the device region, wherein some of the grooves extend along a first direction and are arranged in parallel along a second direction, and the remaining grooves extend along the second direction and are arranged in parallel along the first direction, and the first direction is perpendicular to the second direction; a plurality of stacked electrode layers 11, wherein the bottom electrode layer 11 of the multi-layer electrode layers 11 covers the surfaces of the grooves 20 and the substrate surface, and the remaining electrode layers 11 are stacked in sequence on the bottom electrode layer 11, and the multi-layer electrode layers 11 fill the grooves 20, and in any lead region, the surfaces of the electrode layers 11 adjacent to each other are exposed on the substrate, and in another lead region, the surfaces of the remaining electrode layers 11 adjacent to each other are exposed on the substrate; a dielectric layer (not shown) located between adjacent electrode layers 11; an interconnect plug 30 extending and arranged on the electrode layer 11 exposed in the lead region, and electrically connected to the corresponding electrode layer 11.
[0034] Each electrode layer 11 in the groove 20 is used to form a deep trench capacitor (DTC) structure. In order to load an electrical signal to the electrode layer 11, an interconnect plug 30 needs to be formed on each electrode layer 11 so that the electrode layer 11 is electrically connected to the outside. In order to form the interconnect plug 30 on each electrode layer 11, it is necessary to additionally form a lead area on both sides of the device area, and etch each electrode layer 11 in the lead area so that each electrode layer 11 can expose the surface, thereby forming an interconnect plug 30 on each electrode layer 11, resulting in the DTC structure occupying too much area, affecting the integration of the semiconductor structure.
[0035] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a plurality of pillars protruding from the substrate, the top view of the pillars is a polygon, and the sides of adjacent pillars are arranged relatively to each other; a plurality of grooves, each groove surrounds a pillar, and the plurality of grooves are connected; a plurality of stacked electrode layers, in which the bottom electrode layer covers each surface of the groove and the surface of the pillar, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, and the plurality of electrode layers fill the grooves; a dielectric layer, located between adjacent electrode layers.
[0036] In the embodiment of the present invention, the top view morphology of the pillar is a polygon, the sides of adjacent pillars are arranged relatively, each of the multiple grooves surrounds the pillar, and the multiple grooves are connected, so the multiple pillars are closely arranged, and grooves can be formed between adjacent pillars to provide a spatial position for the capacitor formed by the electrode layer, thereby increasing the flexibility of the arrangement of the capacitor structure, and forming a deep trench capacitor (DTC) structure between the closely arranged adjacent pillars, which is beneficial to saving the occupied area and improving the integration of the semiconductor structure.
[0037] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figures 3 to 6 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.
[0038] Combined with reference Figures 3 to 6 The semiconductor structure includes: a substrate 100; a plurality of pillars 110 protruding from the substrate 100, the top view of the pillars 110 is a polygon, and the sides of adjacent pillars 110 are arranged relatively; a plurality of grooves 200, each groove 200 surrounds the pillars 110, and the plurality of grooves 200 are connected; a plurality of stacked electrode layers 201, in which the bottom electrode layer 201 covers each surface of the grooves 200 and the surface of the pillars 110, and the remaining electrode layers 201 are stacked in sequence on the bottom electrode layer 201, and the plurality of electrode layers 201 fill the grooves 200; a dielectric layer 260, located between adjacent electrode layers 201.
[0039] in, Figure 4 for Figure 3 The cross-sectional view along the AA direction is for clarity. Figure 3 and Figure 5 The interconnections are shown only as wireframes.
[0040] The substrate 100 is used to provide a process platform for forming a semiconductor structure.
[0041] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.
[0042] The pillars 110 are used to form a groove 200 with the base 100 .
[0043] In the present embodiment, the top view of the pillars 110 is a polygon, and the sides of adjacent pillars 110 are arranged relative to each other, so that the opposite sides of adjacent pillars 110 constitute the grooves 200, and the side walls of the outermost pillars 110 constitute the grooves 200, that is, the grooves 200 surround the pillars 110 to form connected grooves 200, so that the arrangement of the grooves 200 is relatively dense and compact, saving the occupied area, which is correspondingly beneficial to improving the capacitance density of the deep trench capacitor (DTC) structure formed in the grooves 200, and improving the performance of the semiconductor structure.
[0044] In this embodiment, the top view of the pillar 110 is a hexagonal polygon.
[0045] The top-view polygon of the column 110 is a hexagon, and each corner of the column 110 is an obtuse angle, so that the column 110 is easy to form, and the electrode layer 201 formed in the groove 200 around the hexagon is easy to form. Moreover, the sides of adjacent columns 110 are relatively arranged, so each hexagonal column 110 can be compactly adjacent to each other to form a tight honeycomb morphology. There is almost no additional unused area between each hexagonal column 110, which is conducive to further making the arrangement of the groove 200 dense and compact, further saving the occupied area, and further helping to improve the integration of the semiconductor structure.
[0046] refer to Figure 6 In this embodiment, the semiconductor structure further includes: a through-hole interconnection structure 600 .
[0047] The through-hole interconnection structure 600 is used to realize longitudinal electrical connection of wafers and realize longitudinal stacking of wafers. In this embodiment, the through-hole interconnection structure 600 is a through-silicon-via (TSV) structure.
[0048] In this embodiment, the plurality of pillars 110 constitute a hexagonal honeycomb-shaped pillar unit, and the plurality of pillar units form a ring structure surrounding the through-hole interconnection structure 600 .
[0049] Compared with a square structure in which a plurality of square grooves form a surrounding through-hole interconnection structure, in the present embodiment, a plurality of pillars 110 form a hexagonal honeycomb-shaped pillar unit, and a plurality of pillar units form a ring structure surrounding the through-hole interconnection structure 600. The honeycomb-shaped pillar units are arranged more compactly, and the ring structure formed by a plurality of pillar units saves more occupied area, which is beneficial to improving the integration of the semiconductor structure.
[0050] The groove 200 is used to provide a space for forming the electrode layer 201 and the dielectric layer 260 .
[0051] In this embodiment, the trench 200 is a deep trench structure with a large depth-to-width ratio, and the electrode layer 201 and the dielectric layer 260 formed in the trench 200 constitute a deep trench capacitor (DTC) structure.
[0052] The electrode layer 201 is used as an electrode plate constituting a capacitor structure.
[0053] In this embodiment, among the multi-layer electrode layers 201, the bottom electrode layer 201 covers various surfaces of the groove 200 and the surface of the pillar 110, and the remaining electrode layers 201 are stacked in sequence on the bottom electrode layer 201, and the multi-layer electrode layers 201 fill the groove 200. That is, in the groove 200, the multi-layer electrode layers 201 are stacked in a direction perpendicular to the side wall of the groove 200 to form a DTC structure.
[0054] In this embodiment, the material of the electrode layer 201 is a conductive material. As an example, the material of the electrode layer 201 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.
[0055] The dielectric layer 260 is used as an insulating layer in forming a capacitor structure and is used to isolate adjacent electrode layers 201 .
[0056] In this embodiment, the material of the dielectric layer 260 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material is conducive to increasing the capacitance value of the capacitor structure and correspondingly increasing the capacitance density.
[0057] Specifically, the dielectric layer 260 is a high-k dielectric layer formed by stacking, that is, the dielectric layer 260 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the dielectric layer 260 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.
[0058] In this embodiment, the dielectric layer 260 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, according to process requirements, the material of the dielectric layer can also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.
[0059] In this embodiment, the top view of the pillar 110 is a polygon, the sides of adjacent pillars 110 are arranged relatively to each other, each groove 200 in the multiple grooves 200 surrounds the pillar 110, and the multiple grooves 200 are connected, so the multiple pillars 110 are closely arranged, and grooves 200 can be formed between adjacent pillars 110 to provide a spatial position for the capacitor formed by the electrode layer 201, thereby increasing the flexibility of the arrangement of the capacitor structure, and forming a deep trench capacitor structure between the closely arranged adjacent pillars 110, which is beneficial to saving the occupied area and improving the integration of the semiconductor structure.
[0060] In this embodiment, along the first direction (such as Figure 3 A plurality of columns 110 extending in a direction Y (shown in the middle) form a column group 111, and the plurality of columns 110 include a plurality of columns extending in a direction Y (shown in the middle) and ... Figure 3 A plurality of column groups 111 are arranged in parallel (as shown in the X direction), the number of layers of the electrode layer 201 is n, and in the n adjacent column groups 111, the surface of each electrode layer 201 in the n electrode layers 201 is exposed on the columns 110 of each column group 111, and the first direction is perpendicular to the second direction.
[0061] In n adjacent column groups 111 , the surface of each electrode layer 201 in the n electrode layers 201 is exposed on the column 110 of each column group 111 , and the exposed surface of the electrode layer 201 is used to contact the interconnection plug, so as to load the electrical signal to the corresponding electrode layer 201 through the interconnection plug.
[0062] In the present embodiment, the columns 110 surround a groove 200, and the surface of the corresponding electrode layer 201 is exposed on each column 110, that is, the electrical signal loading of each electrode layer 201 can be realized above the column 110, without requiring additional area for electrical connection of the electrode layer 201, which is beneficial to saving occupied area, and moreover, the plurality of columns 110 are regularly arranged into a plurality of column groups 111, the columns 110 of each column group 111 expose the same electrode layer 201, and the columns in each column group 111 are arranged and extended along a first direction, then the electrode layer 201 on the columns 110 of each column group 111 can be easily electrically connected to the interconnection line extending along the first direction at the same time, the connection method is simple, and it is beneficial to the realization of the capacitor structure.
[0063] In this embodiment, among the n adjacent column groups 111 , the columns 111 sequentially arranged along the second direction sequentially expose the surfaces of the first to nth electrode layers 201 .
[0064] Among the n adjacent column groups 111, the surfaces of the 1st to nth electrode layers 201 are exposed in sequence on the column groups 111 arranged in sequence along the second direction, so the arrangement of the electrode layers 201 exposed on the column groups 111 is regular, which is conducive to the regular arrangement of the interconnection lines formed above the column groups 111 and the electrode layers 201 corresponding to each other, so that the semiconductor structure has a regular structure, and the structural design and formation are easy to achieve.
[0065] Specifically, in this embodiment, Figure 3 An example is shown in which the number of electrode layers 201 is 2, and in two adjacent column groups 111, the surface of the first electrode layer 210 and the surface of the second electrode layer 220 in the two electrode layers 201 are exposed on the columns 110 of each column group 111; Figure 5 An example in which the number of electrode layers 201 is 4 is shown. Among the four adjacent column groups 111, the surfaces of the first to fourth electrode layers 201 are exposed in sequence on the column groups 111 arranged in sequence along the second direction, specifically, the surfaces of the first electrode layer 210, the second electrode layer 220, the third electrode layer 230 and the fourth electrode layer 240 are exposed in sequence.
[0066] In this embodiment, the semiconductor structure further includes: a plurality of interconnect plugs 300 , which are located on the electrode layer 201 exposed on the pillars 110 and are electrically connected to the corresponding electrode layer 201 .
[0067] The interconnection plug 300 is used to load an electrical signal to the corresponding electrode layer 201 .
[0068] In this embodiment, the plurality of interconnection plugs 300 are located on the electrode layer 201 exposed on the pillars 110 , so there is no need to form an additional area to etch the electrode layer 201 specifically for forming the interconnection plugs 300 , which is beneficial for saving the occupied area of the semiconductor structure.
[0069] In this embodiment, the interconnection plug 300 is made of tungsten. In other embodiments, the interconnection plug may also be made of cobalt or ruthenium.
[0070] In this embodiment, the semiconductor structure further includes: a plurality of interconnection lines 400 extending along a first direction and located on top of the interconnection plugs 300 on the corresponding column group 111 , and the interconnection lines 400 located on top of the interconnection plugs 300 on the same electrode layer 201 are connected in parallel.
[0071] The interconnection line 400 is used to be electrically connected to the interconnection plug 300 , so as to load an electrical signal to the corresponding electrode layer 201 through the interconnection plug 300 .
[0072] In this embodiment, the interconnection line 400 extends along the first direction and is located on the top of the interconnection plug 300 on the corresponding column group 111. The columns 110 of the same column group 111 expose the same electrode layer 201, so that the same interconnection line 400 can load electrical signals for the same electrode layer 201. Moreover, the interconnection lines 400 located on the top of the interconnection plugs 300 on the same electrode layer 201 are connected in parallel, so that the same electrode layers 201 in the multiple electrode layers 201 can all be loaded with the same electrical signal, thereby realizing the basic function of the deep trench capacitor structure.
[0073] In this embodiment, the material of the interconnection line 400 is tungsten. In other embodiments, the material of the interconnection line may also be cobalt or ruthenium.
[0074] In this embodiment, among the plurality of interconnection lines 400 , the interconnection lines 400 located on top of the interconnection plugs 300 of the electrode layers 201 separated by layers are connected in parallel.
[0075] When the interconnection lines 400 located on top of the interconnection plugs 300 of the electrode layers 201 spaced apart from each other are connected in parallel, the same electrical signal is loaded on the adjacent electrode layers 201 spaced apart, thereby enabling a potential difference between the adjacent electrode layers 201 while simplifying the electrical connection lines of the multi-layer electrode layers 201, making the electrical connection structure of the multi-layer electrode layers 201 simple and easy to implement, which is beneficial to saving the formation cost of the semiconductor structure.
[0076] Specifically, in conjunction with reference Figure 3 and Figure 5 In this embodiment, the interconnection lines 400 located on top of the interconnection plugs 300 of the electrode layer 201 of the spacer layer are connected in parallel by electrically connecting the metal wires 500 extending along the second direction to the interconnection lines 400 located on top of the interconnection plugs 300 of the electrode layer 201 of the spacer layer.
[0077] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 7 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0078] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.
[0079] refer to Figure 7 , providing a substrate 100 and a material layer 180 located on the substrate 100.
[0080] The substrate 100 is used to provide a process platform for forming a semiconductor structure.
[0081] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.
[0082] The material layer 180 is used to provide a process platform for forming a capacitor structure.
[0083] In this embodiment, the material layer 180 and the substrate 100 are an integral structure, and the material of the material layer 108 is also silicon.
[0084] In this embodiment, in the step of providing the substrate 100, a through-hole interconnection structure 600 (eg, Fig.10 shown).
[0085] The through-hole interconnection structure 600 is used to realize longitudinal electrical connection of wafers and realize longitudinal stacking of wafers. In this embodiment, the through-hole interconnection structure 600 is a through-silicon-via (TSV) structure.
[0086] Combined with reference Figures 8 to 10 , Fig. 9 yes Figure 8 In the cross-sectional view along the AA direction, a plurality of grooves 200 are formed penetrating the material layer 180, and the remaining material layer 180 forms a plurality of pillars 110 protruding from the substrate 100. The top view of the pillars 110 is polygonal, and the sides of adjacent pillars 110 are arranged relatively to each other. Each groove 200 surrounds the pillar 110, and the plurality of grooves 200 are interconnected.
[0087] The pillars 110 are used to form a groove 200 with the base 100 .
[0088] In the present embodiment, the top view of the pillars 110 is a polygon, and the sides of adjacent pillars 110 are arranged relative to each other, so that the opposite sides of adjacent pillars 110 constitute the grooves 200, and the side walls of the outermost pillars 110 constitute the grooves 200, that is, the grooves 200 surround the pillars 110 to form connected grooves 200, so that the arrangement of the grooves 200 is relatively dense and compact, saving the occupied area, which is correspondingly beneficial to improving the capacitance density of the deep trench capacitor (DTC) structure formed in the grooves 200, and improving the performance of the semiconductor structure.
[0089] In this embodiment, in the step of forming the pillar 110, the pillars 110 are formed along the first direction (eg Figure 8 A plurality of columns 110 extending in a direction Y (shown in the middle) form a column group 111, and the plurality of columns 110 include a plurality of columns extending in a direction Y (shown in the middle) and ... Figure 8A plurality of column groups 111 are arranged in parallel (as shown in the X direction), and the first direction is perpendicular to the second direction.
[0090] A plurality of columns 110 extending along the first direction constitute a column group 111, and the plurality of columns 110 include a plurality of column groups 111 arranged in parallel along the second direction. The arrangement regularity of the plurality of columns 110 is good, which is conducive to making the arrangement of the plurality of columns 110 more compact, thereby saving occupied area.
[0091] In this embodiment, in the step of forming a plurality of pillars 110 , the top-view polygonal shape of the pillars 110 is a hexagon.
[0092] The top-view polygon of the column 110 is a hexagon, and each corner of the column 110 is an obtuse angle, so that the column 110 is easy to form, and also makes it easy to form an electrode layer subsequently formed in the groove 200 around the hexagon. Moreover, the sides of adjacent columns 110 are arranged relatively, so each hexagonal column 110 can be compactly adjacent to each other to form a tight honeycomb morphology. There is almost no extra unused area between each hexagonal column 110, which is conducive to further making the arrangement of the groove 200 dense and compact, further saving the occupied area, and further helping to improve the integration of the semiconductor structure.
[0093] refer to Fig.10 In this embodiment, in the step of forming a plurality of pillars 110 , the plurality of pillars 110 constitute a hexagonal honeycomb-shaped pillar unit, and the plurality of pillar units form a ring structure surrounding the through-hole interconnection structure 600 .
[0094] Compared with a square structure in which a plurality of square grooves form a surrounding through-hole interconnection structure, in the present embodiment, a plurality of pillars 110 form a hexagonal honeycomb-shaped pillar unit, and a plurality of pillar units form a ring structure surrounding the through-hole interconnection structure 600. The honeycomb-shaped pillar units are arranged more compactly, and the ring structure formed by a plurality of pillar units saves more occupied area, which is beneficial to improving the integration of the semiconductor structure.
[0095] The groove 200 is used to provide a space for the subsequent formation of an electrode layer and a dielectric layer 26 .
[0096] In this embodiment, the trench 200 is a deep trench structure with a large depth-to-width ratio, and the electrode layer and the dielectric layer subsequently formed in the trench 200 constitute a deep trench capacitor (DTC) structure.
[0097] Combined with reference Figures 11 to 13 , Fig.12 for Fig.11The cross-sectional view along the AA direction forms a multi-layer stacked electrode layer 201 and a dielectric layer 260. Among the multi-layer electrode layers 201, the bottom electrode layer 201 covers the surfaces of the grooves 200 and the surfaces of the pillars 110, and the remaining electrode layers 201 are stacked in sequence on the bottom electrode layer 201. The multi-layer electrode layers 201 fill the grooves 200, and the dielectric layer 260 is located between adjacent electrode layers 201.
[0098] The electrode layer 201 is used as an electrode plate constituting a capacitor structure.
[0099] In this embodiment, among the multi-layer electrode layers 201, the bottom electrode layer 201 covers various surfaces of the groove 200 and the surface of the pillar 110, and the remaining electrode layers 201 are stacked in sequence on the bottom electrode layer 201, and the multi-layer electrode layers 201 fill the groove 200. That is, in the groove 200, the multi-layer electrode layers 201 are stacked in a direction perpendicular to the side wall of the groove 200 to form a DTC structure.
[0100] In this embodiment, the material of the electrode layer 201 is a conductive material. As an example, the material of the electrode layer 201 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.
[0101] The dielectric layer 260 is used as an insulating layer in forming a capacitor structure and is used to isolate adjacent electrode layers 201 .
[0102] In this embodiment, the material of the dielectric layer 260 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material is conducive to increasing the capacitance value of the capacitor structure and correspondingly increasing the capacitance density.
[0103] Specifically, the dielectric layer 260 is a high-k dielectric layer formed by stacking, that is, the dielectric layer 260 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the dielectric layer 260 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.
[0104] In this embodiment, the dielectric layer 260 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, according to process requirements, the material of the dielectric layer can also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.
[0105] In this embodiment, the top view of the pillar 110 is a polygon, the sides of adjacent pillars 110 are arranged relatively to each other, each groove 200 in the multiple grooves 200 surrounds the pillar 110, and the multiple grooves 200 are connected, so the multiple pillars 110 are closely arranged, and grooves 200 can be formed between adjacent pillars 110 to provide a spatial position for the capacitor formed by the electrode layer 201, thereby increasing the flexibility of the arrangement of the capacitor structure, and forming a deep trench capacitor structure between the closely arranged adjacent pillars 110, which is beneficial to saving the occupied area and improving the integration of the semiconductor structure.
[0106] In this embodiment, in the step of forming the electrode layer 201 , the number of electrode layers 201 is n, and in n adjacent column groups 111 , the column 110 of each column group 111 exposes the surface of each electrode layer 201 in the n electrode layers 201 .
[0107] In n adjacent column groups 111 , the surface of each electrode layer 201 in the n electrode layers 201 is exposed on the column 110 of each column group 111 , and the exposed surface of the electrode layer 201 is used to contact the interconnection plug, so as to load the electrical signal to the corresponding electrode layer 201 through the interconnection plug.
[0108] In the present embodiment, the columns 110 surround a groove 200, and the surface of the corresponding electrode layer 201 is exposed on each column 110, that is, the electrical signal loading of each electrode layer 201 can be realized above the column 110, without requiring additional area for electrical connection of the electrode layer 201, which is beneficial to saving occupied area, and moreover, the plurality of columns 110 are regularly arranged into a plurality of column groups 111, the columns 110 of each column group 111 expose the same electrode layer 201, and the columns in each column group 111 are arranged and extended along a first direction, then the electrode layer 201 on the columns 110 of each column group 111 can be easily electrically connected to the interconnection line extending along the first direction at the same time, the connection method is simple, and it is beneficial to the realization of the capacitor structure.
[0109] In this embodiment, in the step of forming the electrode layer 201 , among the n adjacent column groups 111 , the columns 111 sequentially arranged along the second direction sequentially expose the surfaces of the first to n electrode layers 201 .
[0110] Among the n adjacent column groups 111, the surfaces of the 1st to nth electrode layers 201 are exposed in sequence on the column groups 111 arranged in sequence along the second direction, so the arrangement of the electrode layers 201 exposed on the column groups 111 is regular, which is conducive to the regular arrangement of the interconnection lines formed above the column groups 111 and the electrode layers 201 corresponding to each other, so that the semiconductor structure has a regular structure, and the structural design and formation are easy to achieve.
[0111] Specifically, in this embodiment, Fig.11 An example is shown in which the number of electrode layers 201 is 2, and in two adjacent column groups 111, the surface of the first electrode layer 210 and the surface of the second electrode layer 220 in the two electrode layers 201 are exposed on the columns 110 of each column group 111; Fig.13 An example in which the number of electrode layers 201 is 4 is shown. Among the four adjacent column groups 111, the surfaces of the first to fourth electrode layers 201 are exposed in sequence on the column groups 111 arranged in sequence along the second direction, specifically, the surfaces of the first electrode layer 210, the second electrode layer 220, the third electrode layer 230 and the fourth electrode layer 240 are exposed in sequence.
[0112] Specifically, in this embodiment, the step of forming a multi-layer stacked electrode layer 201 includes: forming n layers of electrode material layers stacked in sequence; etching back part of the electrode material layer so that in the n adjacent column groups 111, the surface of each electrode layer 201 in the n layers of electrode layer 201 is exposed on the column 110 of each column group 111.
[0113] After forming n electrode material layers stacked in sequence, a portion of the electrode material layers is etched back, which is beneficial for making the morphology of the formed electrode layer 201 more accurate.
[0114] In this embodiment, in the step of forming the multi-layer stacked electrode layer 201 and the dielectric layer 260 , each electrode layer 201 and each dielectric layer 260 is formed by an atomic layer deposition process.
[0115] The electrode layer 201 and the dielectric layer 260 formed by the atomic layer deposition process have good thickness uniformity and good step coverage capability, so that the electrode layer 201 and the dielectric layer 260 can conformally cover the bottom and side walls of the groove 200 well, and it is also beneficial to make the thickness uniformity of the electrode layer 201 and the dielectric layer 260 better.
[0116] Continue to combine references Figures 11 to 13 After forming a multi-layer stacked electrode layer 201 and a dielectric layer 260 , the forming method further includes: forming a plurality of interconnect plugs 300 , which are located on the electrode layer 201 exposed on the pillars 110 and are electrically connected to the corresponding electrode layer 201 .
[0117] The interconnection plug 300 is used to load an electrical signal to the corresponding electrode layer 201 .
[0118] In this embodiment, the plurality of interconnection plugs 300 are located on the electrode layer 201 exposed on the pillars 110 , so there is no need to form an additional area to etch the electrode layer 201 specifically for forming the interconnection plugs 300 , which is beneficial for saving the occupied area of the semiconductor structure.
[0119] In this embodiment, the interconnection plug 300 is made of tungsten. In other embodiments, the interconnection plug may also be made of cobalt or ruthenium.
[0120] In this embodiment, a plurality of interconnection lines 400 are formed on top of the interconnection plug 300. The interconnection lines 400 extend along the first direction and are located on top of the corresponding interconnection plug 300 on the column group 111. The interconnection lines 400 located on top of the interconnection plug 300 on the same electrode layer 201 are connected in parallel.
[0121] The interconnection line 400 is used to be electrically connected to the interconnection plug 300 , so as to load an electrical signal to the corresponding electrode layer 201 through the interconnection plug 300 .
[0122] In this embodiment, the interconnection line 400 extends along the first direction and is located on the top of the interconnection plug 300 on the corresponding column group 111. The columns 110 of the same column group 111 expose the same electrode layer 201, so that the same interconnection line 400 can load electrical signals for the same electrode layer 201. Moreover, the interconnection lines 400 located on the top of the interconnection plugs 300 on the same electrode layer 201 are connected in parallel, so that the same electrode layers 201 in the multiple electrode layers 201 can all be loaded with the same electrical signal, thereby realizing the basic function of the deep trench capacitor structure.
[0123] In this embodiment, the material of the interconnection line 400 is tungsten. In other embodiments, the material of the interconnection line may also be cobalt or ruthenium.
[0124] In this embodiment, in the step of forming a plurality of interconnection lines 400 , the interconnection lines 400 located on top of the interconnection plugs 300 of the electrode layers 201 separated by spaced layers are connected in parallel.
[0125] When the interconnection lines 400 located on top of the interconnection plugs 300 of the electrode layers 201 spaced apart from each other are connected in parallel, the same electrical signal is loaded on the adjacent electrode layers 201 spaced apart, thereby enabling a potential difference between the adjacent electrode layers 201 while simplifying the electrical connection lines of the multi-layer electrode layers 201, making the electrical connection structure of the multi-layer electrode layers 201 simple and easy to implement, which is beneficial to saving the formation cost of the semiconductor structure.
[0126] Specifically, in conjunction with reference Fig.11 and Fig.13 In this embodiment, by forming a metal wire 500 extending along the second direction, the metal wire 500 is electrically connected to the interconnection wire 400 on top of the interconnection plug 300 of the electrode layer 201 of the phase-separated layer, thereby realizing parallel connection of the interconnection wire 400 on top of the interconnection plug 300 of the electrode layer 201 of the phase-separated layer.
[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A plurality of columns protruding from the base, wherein the columns are polygonal in top view, and the sides of adjacent columns are arranged opposite to each other; A plurality of grooves, each of which surrounds the column, and a plurality of the grooves are connected; A plurality of stacked electrode layers, wherein the bottom electrode layer covers each surface of the groove and the surface of the pillar, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, and the plurality of electrode layers fill the groove; The dielectric layer is located between adjacent electrode layers.
2. The semiconductor structure according to claim 1, wherein: A plurality of the columns extending and arranged along the first direction constitute a column group, and the plurality of the columns include a plurality of column groups arranged in parallel along the second direction. The number of electrode layers is n. In the n adjacent column groups, the surface of each electrode layer in the n electrode layers is exposed on the columns of each column group, and the first direction is perpendicular to the second direction.
3. The semiconductor structure according to claim 2, wherein: Among the n adjacent pillar groups, the pillar groups sequentially arranged along the second direction sequentially expose the surfaces of the first to n electrode layers.
4. The semiconductor structure according to claim 2, characterized in that The semiconductor structure further comprises: a plurality of interconnect plugs, which are located on the electrode layers exposed on the pillars and are electrically connected to the corresponding electrode layers; A plurality of interconnection lines extend along the first direction and are located on top of interconnection plugs on corresponding pillar groups, and the interconnection lines located on top of interconnection plugs on the same electrode layer are connected in parallel.
5. The semiconductor structure according to claim 4, characterized in that Among the plurality of interconnection lines, the interconnection lines located on top of the interconnection plugs of the electrode layers separated by the layers are connected in parallel.
6. The semiconductor structure according to claim 1, wherein: The top view polygon of the column is a hexagon.
7. The semiconductor structure according to claim 6, wherein: The semiconductor structure further comprises: a through-hole interconnect structure; The plurality of columns form a hexagonal honeycomb column unit, and the plurality of column units form a ring structure surrounding the through-hole interconnection structure.
8. The semiconductor structure according to claim 1, wherein: The dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; The material of the electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.
9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate and a material layer on the substrate; A plurality of grooves are formed through the material layer, and the remaining material layer forms a plurality of pillars protruding from the substrate, wherein the pillars are polygonal in top view, and the sides of adjacent pillars are arranged oppositely, each of the grooves surrounds the pillar, and a plurality of the grooves are connected; A multi-layer stacked electrode layer and a dielectric layer are formed, wherein the bottom electrode layer covers the surfaces of the grooves and the surfaces of the pillars, and the remaining electrode layers are stacked in sequence on the bottom electrode layer. The multi-layer electrode layers fill the grooves, and the dielectric layer is located between adjacent electrode layers.
10. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming the pillars, a plurality of the pillars extending and arranged along a first direction constitute a pillar group, and the plurality of the pillars include a plurality of pillar groups arranged in parallel along a second direction, and the first direction is perpendicular to the second direction; In the step of forming the electrode layer, the number of the electrode layer is n, and in the n adjacent column groups, the surface of each electrode layer in the n electrode layers is exposed on the columns of each column group.
11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming the electrode layer, among the n adjacent column groups, the column groups sequentially arranged along the second direction sequentially expose the surfaces of the first to n electrode layers.
12. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming a multi-layer stacked electrode layer includes: forming n layers of electrode material layers stacked in sequence; Part of the electrode material layer is etched back so that in n adjacent pillar groups, the pillars of each pillar group respectively expose the surface of each electrode layer in the n electrode layers.
13. The method for forming a semiconductor structure according to claim 10, wherein: After forming a multi-layer stack of electrode layers and dielectric layers, the forming method further comprises: forming a plurality of interconnect plugs, which are located on the electrode layers exposed on the pillars and are electrically connected to the corresponding electrode layers; A plurality of interconnection lines are formed on the top of the interconnection plugs. The interconnection lines extend along the first direction and are located on the top of the interconnection plugs on the corresponding pillar groups. The interconnection lines located on the top of the interconnection plugs on the same electrode layer are connected in parallel.
14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a plurality of interconnection lines, the interconnection lines located on top of the interconnection plugs of the electrode layers spaced apart from each other are connected in parallel.
15. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming a plurality of the pillars, the top view polygonal shape of the pillars is a hexagon.
16. The method for forming a semiconductor structure according to claim 15, wherein: In the step of providing the substrate, a through-hole interconnection structure penetrating the material layer is formed in the material layer; In the step of forming a plurality of the pillars, the plurality of pillars constitute a hexagonal honeycomb-shaped pillar unit, and the plurality of pillar units form a ring structure surrounding the through-hole interconnection structure.
17. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming a multi-layer stack of electrode layers and dielectric layers, each electrode layer and dielectric layer is formed by an atomic layer deposition process.
18. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming a multi-layer stacked electrode layer and a dielectric layer, the dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN, and the material of the electrode layer includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.