Anti-interference power-on reset circuit, low dropout regulator, power management chip and data conversion chip

Abstract

The embodiment of the invention provides an anti-interference power-on reset circuit which can be commonly used for a low dropout regulator, a power management chip and a data conversion chip. According to the anti-interference power-on reset circuit, the feedback circuit is adopted, so that the change of the output voltage influences the generation of the output voltage through the feedback circuit; according to the reset circuit, the bias voltage and the reference voltage generated based on the power supply voltage are adopted, when the bias voltage and reference voltage circuit works, the normal working voltage value of the POR circuit can be controlled, and the POR circuit is reset to work normally, so that the problem that when the power supply is powered on slowly and the power supply voltage is relatively low, the POR starts to reset, and the reset time is short is solved. The chip is in a wrong working state, and the circuit reset function is lost. Compared with the prior art, the invention has the following beneficial effects: by adopting the feedback circuit and the bias circuit and the reference circuit based on the power supply voltage, when the burr fluctuation exists on the power supply, the POR output state is kept unchanged, the anti-interference capability is strong, the feedback circuit is simple in structure, and the cost is low. And the method is easy and can control when the POR circuit starts to work at a relatively high voltage value.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an anti-interference power-on reset circuit, a low voltage drop linear regulator, a power management chip and a data conversion chip. Background Art

[0002] Power-on reset (POR) circuits are widely used in various functional circuits. When the power is turned on or restarted after power failure, the POR circuit generates a POR enable signal to set the initial state of modules with memory functions such as latches, registers, and triggers, thereby ensuring that the circuit system enters a normal working state.

[0003] However, when the chip is working normally, due to the interference of high-frequency noise or the sudden change of load current, the power signal will produce an upward or downward spike, thereby generating a false reset signal, affecting the normal operation of the entire chip. Therefore, anti-interference ability is an important indicator of POR circuit performance. Therefore, a POR circuit with strong anti-interference ability is needed. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides an interference-resistant power-on reset circuit, a low voltage drop linear regulator, a power management chip and a data conversion chip, which solve the problem of false reset of the POR circuit in the prior art.

[0005] In a first aspect, according to an embodiment of the present invention, there is provided an anti-interference power-on reset circuit, comprising: a first PMOS field effect transistor, whose drain and source are connected to a power supply voltage, and whose gate is connected to a first node; a second PMOS field effect transistor, whose source is connected to the power supply voltage, whose drain is connected to a second node, and whose gate is connected to a bias circuit; a first NMOS field effect transistor, whose source is grounded, whose drain is connected to the second node, and whose gate is connected to the first node; a second NMOS field effect transistor, whose source is grounded, whose drain is connected to the first node, and whose gate is connected to an output node, wherein: A first inverter and a Schmitt trigger inverter are also connected in series between the output node and the second node; a third NMOS field effect transistor, a fourth NMOS field effect transistor and a fifth NMOS field effect transistor are connected in parallel, and their gates are all connected to the reference voltage generating circuit, the drain of the third NMOS field effect transistor is connected to the first node, the source of the third NMOS field effect transistor is connected to the drain of the fourth NMOS field effect transistor, the source of the fourth NMOS field effect transistor is connected to the drain of the fifth NMOS field effect transistor, and the source of the fifth NMOS field effect transistor is grounded.

[0006] According to an embodiment of the present invention, the bias circuit and the reference voltage generating circuit operate when the power supply voltage is greater than a preset threshold operating voltage.

[0007] According to an embodiment of the present invention, the preset threshold voltage is adjustable.

[0008] According to an embodiment of the present invention, the bias circuit and the reference voltage generating circuit are bandgap reference circuits.

[0009] According to an embodiment of the present invention, the preset threshold operating voltage is 2V.

[0010] According to an embodiment of the present invention, the bias voltage is smaller than a difference between the power supply voltage and a turn-on voltage of the second PMOS field effect transistor.

[0011] According to an embodiment of the present invention, the bias voltage is 1V.

[0012] In a second aspect, according to another embodiment of the present invention, a low voltage dropout linear regulator is provided, comprising an anti-interference power-on reset circuit as described in the first aspect.

[0013] In a third aspect, according to another embodiment of the present invention, there is provided a power management chip, comprising a low voltage dropout linear regulator as described in the second aspect.

[0014] In a fourth aspect, according to another embodiment of the present invention, there is provided a data conversion chip, including a digital-to-analog conversion circuit or an analog-to-digital conversion circuit, including an anti-interference power-on reset circuit as described in the first aspect.

[0015] The technical principle of the present invention is: a feedback circuit is adopted so that the change of the output voltage affects the generation of the output voltage through the feedback circuit; a bias voltage and a reference voltage generated based on the power supply voltage are adopted to control the normal working voltage value of the POR circuit. When the bias voltage and the reference voltage circuit are working, the POR circuit is reset to work normally, which solves the problem that when the power supply is powered on slowly and the power supply voltage is low, the POR starts to reset, causing the chip to be in an erroneous working state and losing the circuit reset function. Compared with the prior art, the present invention has the following beneficial effects: by adopting a feedback circuit and a bias circuit and a reference circuit based on the power supply voltage, when there is a burr fluctuation on the power supply, the POR output state remains unchanged, has the characteristics of strong anti-interference ability, has a simple feedback circuit structure, and is easy to control when the POR circuit starts to work, and works at a relatively high voltage value. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 4 is a schematic diagram of a power-on reset circuit according to an embodiment of the present invention.

[0017] Figure 2 1 is an input and output timing diagram of a power-on reset circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0019] As described in the background technology, there is a problem of false reset of the POR circuit in the prior art. In order to solve the above problem, Figure 1 As shown, an embodiment of the present invention provides an anti-interference power-on reset circuit, comprising: a first PMOS field effect transistor, whose drain and source are connected to a power supply voltage, and whose gate is connected to a first node; a second PMOS field effect transistor, whose source is connected to the power supply voltage, whose drain is connected to a second node, and whose gate is connected to a bias circuit; a first NMOS field effect transistor, whose source is grounded, whose drain is connected to the second node, and whose gate is connected to the first node; a second NMOS field effect transistor, whose source is grounded, whose drain is connected to the first node, and whose gate is connected to an output node, wherein the output A first inverter and a Schmitt trigger inverter are also connected in series between the output node and the second node; the third NMOS field effect transistor, the fourth NMOS field effect transistor and the fifth NMOS field effect transistor are connected in parallel, and their gates are all connected to the reference voltage generation circuit, the drain of the third NMOS field effect transistor is connected to the first node, the source of the third NMOS field effect transistor is connected to the drain of the fourth NMOS field effect transistor, the source of the fourth NMOS field effect transistor is connected to the drain of the fifth NMOS field effect transistor, and the source of the fifth NMOS field effect transistor is grounded. Due to the use of the feedback circuit, when there is a glitch fluctuation on the power supply, the POR output state remains unchanged, has a strong anti-interference ability, and the feedback circuit structure is simple.

[0020] According to an embodiment of the present invention, the bias circuit and the reference voltage generating circuit operate when the power supply voltage is greater than a preset threshold operating voltage. Figure 1When the circuit is just started, the initial state of all nodes (N1, N2) and the output voltage (POR) is 0, and the drain source and substrate of the first PMOS field effect tube MP1 are shorted to the power supply VDD, and the capacitor is used. When the power supply voltage (VDD) changes from low to high, due to the presence of the capacitor, the potential of the first node N1 changes from low to high, the first NMOS field effect tube MN1 is turned on, the second node N2 is low, the POR output is low, and the second NMOS field effect tube MN2 is turned off. When the VDD voltage changes from low to high until it is greater than the preset threshold operating voltage (for example, 2.0V), as the reference voltage generation circuit and the bias voltage circuit establish work, the vref voltage increases from 0V to 1.2V, and the vbp voltage increases from 0V to the preset value voltage (less than the difference between the power supply voltage and the turn-on voltage of the second PMOS field effect tube (VDD-VTH), for example, 1.0V). At this time, the third NMOS field effect transistor, the fourth NMOS field effect transistor and the fifth NMOS field effect transistor MN3-MN5 are turned on, the voltage of the first node N1 gradually decreases, the second node N2 gradually increases to VDD, the POR voltage jumps from a low level to VDD (via the Schmitt trigger inverter and the inverter), and the second NMOS field effect transistor MN2 is turned on, further pulling down the level of the first node N1 to a low level. According to an embodiment of the present invention, the preset threshold voltage is adjustable, so that it is easy to control when the POR circuit can work normally. When the bias voltage and the reference voltage circuit work, the POR circuit resets to work normally, which solves the problem that when the power supply is slowly powered on, when the power supply voltage is low, the POR starts to reset, causing the chip to be in an erroneous working state and lose the circuit reset function.

[0021] In addition, when the power supply voltage VDD fluctuates, the POR output waveform is as follows: Figure 2 As shown. When the power supply voltage VDD is suddenly higher than the normal working voltage, due to the existence of the capacitor first PMOS field effect tube MP1, the voltage of the first node N1 increases, but through the feedback circuit second NMOS field effect tube MN2, the POR output is high at the last moment, the second NMOS field effect tube MN2 is turned on, and the first node N1 is still low. Avoid the first NMOS field effect tube MN1 from turning on and affecting the potential of the second node N2, thereby eliminating the impact on the POR output level. If there is no such feedback circuit, when the power supply voltage is suddenly higher than the normal working voltage, the potential of the first node N1 becomes high, the first NMOS field effect tube MN1 is turned on, the second node N2 becomes low, and the POR becomes low.

[0022] When the power supply voltage VDD is suddenly lower than the normal working voltage, the voltage of the first node N1 is pulled down due to the existence of the capacitor first PMOS field effect tube MP1; however, in normal working, the potential of the first node N1 is low, so it does not affect the POR output level. Combined with the aforementioned control of the working voltage of the POR circuit, only when the power supply voltage drops to the preset threshold working voltage, the POR circuit will enter the non-working state and non-reset state, while in other states, the POR circuit maintains a stable output reset state.

[0023] According to another embodiment of the present invention, a low voltage dropout linear regulator is provided, comprising the anti-interference power-on reset circuit as described above.

[0024] According to another embodiment of the present invention, a power management chip is provided, comprising the low voltage dropout linear regulator as described above.

[0025] According to another embodiment of the present invention, there is provided a data conversion chip, including a digital-to-analog conversion circuit or an analog-to-digital conversion circuit, including an anti-interference power-on reset circuit as described above.

[0026] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. An anti-interference power-on reset circuit, characterized in that: include: A first PMOS field effect transistor, a drain and a source of which are connected to a power supply voltage, and a gate of which is connected to a first node; a second PMOS field effect transistor, whose source is connected to the power supply voltage, whose drain is connected to the second node, and whose gate is connected to the bias circuit; A first NMOS field effect transistor, whose source is grounded, whose drain is connected to the second node, and whose gate is connected to the first node; A second NMOS field effect transistor, whose source is grounded, whose drain is connected to the first node, and whose gate is connected to the output node, wherein a first inverter and a Schmitt trigger inverter are further connected in series between the output node and the second node; The third NMOS field effect transistor, the fourth NMOS field effect transistor and the fifth NMOS field effect transistor connected in parallel have their gates connected to the reference voltage generating circuit, the drain of the third NMOS field effect transistor is connected to the first node, the source of the third NMOS field effect transistor is connected to the drain of the fourth NMOS field effect transistor, the source of the fourth NMOS field effect transistor is connected to the drain of the fifth NMOS field effect transistor, and the source of the fifth NMOS field effect transistor is grounded.

2. The anti-interference power-on reset circuit according to claim 1, characterized in that: The bias circuit and the reference voltage generating circuit operate when the power supply voltage is greater than a preset threshold operating voltage.

3. The anti-interference power-on reset circuit according to claim 2, characterized in that: The preset threshold operating voltage is 2V.

4. The anti-interference power-on reset circuit according to claim 2, characterized in that: The bias circuit and the reference voltage generating circuit are bandgap reference circuits.

5. The anti-interference power-on reset circuit according to claim 2, characterized in that: The bias voltage is smaller than a difference between the power supply voltage and a turn-on voltage of the second PMOS field effect transistor.

6. The anti-interference power-on reset circuit according to claim 5, characterized in that: The bias voltage is 1V.

7. A low voltage dropout linear regulator, characterized in that: An anti-interference power-on reset circuit comprising any one of claims 1-6.

8. A power management chip, characterized in that: A low voltage drop linear regulator comprising the one described in claim 7.

9. A data conversion chip, comprising a digital-to-analog conversion circuit or an analog-to-digital conversion circuit, characterized in that: An anti-interference power-on reset circuit comprising any one of claims 1-6.

Images