Wiring board

Abstract

Provided is a wiring board having high quality. A wiring board according to an embodiment includes: a core substrate including a glass substrate, a through hole penetrating the substrate, and a via conductor formed in the through hole; a resin insulating layer formed on the core substrate and having a first surface, a second surface, and an opening for the via conductor; a first conductor layer formed on a first surface of the resin insulating layer; and a via conductor formed within the opening and electrically connected to the via conductor. The first conductor layer and the via conductor are formed of a seed layer and a plated layer formed on the seed layer, the seed layer being formed by sputtering. The resin insulating layer is formed of a resin and inorganic particles, the inorganic particles including first inorganic particles partially embedded in the resin and second inorganic particles embedded in the resin, the first inorganic particles being formed of a first portion protruding from the resin and a second portion embedded in the resin, the first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a wiring substrate. Background Art

[0002] Patent Document 1 discloses a multilayer substrate having a core made of glass.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-133473

[0004] [Problem of Patent Document 1]

[0005] Patent Document 1 controls the light transmittance of a first insulating layer made of glass. Patent Document 1 describes a method of controlling the light transmittance by including a colorant in the first insulating layer. It is considered that it is difficult for the first insulating layer made of glass to evenly include a colorant. Summary of the invention

[0006] The wiring substrate of the present invention comprises: a core substrate having a glass substrate, a through hole penetrating the substrate, and a through-hole conductor formed in the through hole; a resin insulating layer formed on the core substrate, having a first surface, a second surface on the side opposite to the first surface, and an opening for a through-hole conductor reaching from the first surface to the second surface; a first conductor layer formed on the first surface of the resin insulating layer; and a through-hole conductor formed in the opening and electrically connected to the through-hole conductor. The first conductor layer and the through-hole conductor are formed by a seed layer and a plating layer formed on the seed layer, and the seed layer is formed by sputtering. The resin insulating layer is formed by a resin and inorganic particles, the inorganic particles include a first inorganic particle partially buried in the resin and a second inorganic particle buried in the resin, the first inorganic particle is formed by a first portion protruding from the resin and a second portion buried in the resin, and the first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface.

[0007] In a wiring substrate of an embodiment of the present invention, the core substrate includes a glass substrate. The glass substrate has excellent flatness. Therefore, the first surface of the resin insulating layer has excellent flatness. The first surface has excellent smoothness. The embodiment can form fine wiring on the first surface of the resin insulating layer. In the embodiment, almost no recess is formed on the first surface of the resin insulating layer. Therefore, in the case of forming a seed layer on the resin insulating layer by sputtering, even if the thickness of the sputtering film is thin, the embodiment can form a continuous seed layer. As a result, when the seed layer is removed, the embodiment can reduce the etching amount. The embodiment can form fine wiring on the resin insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1It is a cross-sectional view schematically showing a wiring substrate according to the embodiment.

[0009] Figure 2 This is an enlarged cross-sectional view schematically showing a part of the wiring substrate according to the embodiment.

[0010] Figure 3A This is an enlarged cross-sectional view schematically showing a part of the wiring substrate according to the embodiment.

[0011] Figure 3B It is an enlarged cross-sectional view schematically showing a part of the inner wall surface.

[0012] Figure 3C is an enlarged cross-sectional view schematically showing a part of the seed layer.

[0013] Figure 4 This is a cross-sectional photograph schematically showing a part of the wiring substrate according to the embodiment.

[0014] Figure 5A It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0015] Figure 5B It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0016] Figure 5C It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0017] Figure 5D It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0018] Figure 5E It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0019] Fig. 5F It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0020] Figure 5G It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0021] Figure 5H It is an enlarged cross-sectional view schematically showing the method for manufacturing a wiring substrate according to the embodiment.

[0022] Fig.5I It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0023] Figure 5J It is an enlarged cross-sectional view schematically showing the method for manufacturing a wiring substrate according to the embodiment.

[0024] Figure 5K It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0025] Figure 5L It is an enlarged cross-sectional view schematically showing the method for manufacturing a wiring substrate according to the embodiment.

[0026] Figure 5M It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to an embodiment.

[0027] Figure 6 It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to a modified example.

[0028] Figure 7 It is a cross-sectional view schematically showing a method for manufacturing a wiring substrate according to a modified example.

[0029] Description of symbols

[0030] 2: Wiring substrate; 3: Core substrate; 4: Substrate; 5F: Front; 5B: Back; 6: Through hole; 8: Through-hole conductor; 10F, 10B: Conductor layer; 11F, 11B: Conductor layer; 14F, 14B: Pad; 20F, 20B: First resin insulating layer; 22F, 22B: First surface; 24F, 24B: Second surface; 26F: First opening; 27F: Inner wall surface; 30F, 30B: First conductor layer; 30Fa: Seed layer; 30Fb: Plating layer; 32F, 32B: First signal wiring; 34F, 34B: Second signal wiring; 36F: Pad; 40F, 40B: First via conductor; 60, 60a, 60b: First film; 62, 62a, 62b: Front end; 70, 70a, 70b: Second film; 72, 72a, 72b: rear end; 80: resin; 90: inorganic particles; 91: first inorganic particles; 92: second inorganic particles; 93: third inorganic particles; 93a: flat portion; 93b: exposed surface; 120F, 120B: second resin insulating layer; 122F, 122B: first surface; 124F, 124B: second surface; 126F: second opening; 127F: inner wall surface; 130F, 130B: second conductor layer; 130Fa: seed layer; 130Fb: electroplating layer; 132F, 132B: first signal wiring; 134F, 134B: second signal wiring; 136F: pad; 140F, 140B: second via conductor; 300F: front side build-up layer; 300B: back side build-up layer. DETAILED DESCRIPTION

[0031] [Implementation Method]

[0032] Figure 1It is a cross-sectional view showing the wiring board 2 according to the embodiment. Figure 2 and Figure 3A 2 is an enlarged cross-sectional view showing a portion of the wiring substrate 2 according to the embodiment. Figure 1 As shown, wiring substrate 2 includes core substrate 3 , front-side build-up layer 300F, and back-side build-up layer 300B.

[0033] The core substrate 3 has a substrate 4, a through hole 6 and a through-hole conductor 8. The substrate 4 has a front side 5F and a back side 5B on the opposite side of the front side 5F. The substrate 4 is made of glass. The through hole 6 penetrates the substrate 4. The shape of the through hole 6 is roughly cylindrical. The diameter of the through hole 6 is roughly constant. The shape of the through hole 6 can also be roughly a truncated cone. The shape of the through hole 6 can also be a shape obtained by connecting two roughly cones. The two cones are a cone on the front side and a cone on the back side. The bottom surface of the cone on the front side is located on the front side 5F, and the bottom surface of the cone on the back side is located on the back side 5B. In this case, the side surface of the through hole 6 is formed by a surface that tapers from the front side 5F toward the back side 5B and a surface that tapers from the back side 5B toward the front side 5F.

[0034] The through-hole conductor 8 is formed in the through-hole 6. The through-hole conductor 8 is mainly formed of copper. The through-hole conductor 8 includes a seed layer 10a formed on the inner wall surface of the through-hole 6 and a plating layer 10b formed on the seed layer 10a. The plating layer 10b fills the through-hole 6. The seed layer 10a is formed by chemical plating. The through-hole conductor 8 has an upper end 8F and a lower end 8B. The surface of the upper end 8F and the front surface 5F are substantially in the same plane. The surface of the lower end 8B and the back surface 5B are substantially in the same plane. The upper end 8F is exposed from the front surface 5F. The lower end 8B is exposed from the back surface 5B.

[0035] The front side build-up layer 300F is formed on the front side 5F of the substrate 4. The front side build-up layer 300F has a front side via conductor that penetrates the resin insulation layer on the front side, the conductor layer on the front side, and the resin insulation layer on the front side. The conductor layer on the front side and the via conductor on the front side are electrically connected to the through-hole conductor 8. The resin insulation layer on the front side and the conductor layer on the front side are alternately stacked. Figure 1 The resin insulation layers on the front side of the image are the first resin insulation layer 20F and the second resin insulation layer 120F. The conductor layers on the front side are the first conductor layer 30F and the second conductor layer 130F. The via-hole conductors on the front side are the first via-hole conductor 40F and the second via-hole conductor 140F.

[0036] The first resin insulating layer 20F has a first surface 22F and a second surface 24F opposite to the first surface 22F. The first resin insulating layer 20F is formed on the front surface 5F of the substrate 4 so that the second surface 24F faces the front surface 5F. Figure 1In the example, the second surface 24F is in contact with the front surface 5F. The second surface 24F is in contact with a portion of the upper end 8F. There is no conductor circuit between the front surface 5F and the second surface 24F. No conductor circuit is formed on the front surface 5F. The first resin insulating layer 20F has a first opening 26F that reaches the upper end 8F of the through-hole conductor 8. The first opening 26F has an opening on the first surface 22F (top opening) and an opening on the second surface 24F (bottom opening). The shapes of the top opening and the bottom opening are roughly circular. The bottom opening can expose the upper end 8F and the front surface 5F at the same time. In this case, the front surface 5F around the upper end 8F is exposed. The bottom opening can also expose a portion of the upper end 8F and the front surface 5F around a portion of it (first example). The bottom opening can also expose all of the upper end 8F and the front surface 5F around the upper end 8F (second example). As Figure 1 As shown, the bottom opening can expose only the upper end 8F (third example). In the first example, the second example and the third example, two examples can be mixed. The first example, the second example and the third example can also be mixed. Preferably, the first example and the third example are mixed. In this case, the upper ends 8F of several through-hole conductors 8 are exposed at the opening of the first example, and the upper ends 8F of the remaining through-hole conductors 8 are exposed at the opening of the third example. The first resin insulating layer 20F is formed by a resin 80 and a plurality of inorganic particles 90 dispersed in the resin 80. The resin 80 is an epoxy resin. Examples of resins are thermosetting resins and photocurable resins. The inorganic particles 90 are glass particles. The inorganic particles 90 can also be aluminum oxide. The content of the inorganic particles 90 in the first resin insulating layer 20F is 75wt% or more.

[0037] like Figure 1 and Figure 2 As shown, the inorganic particles 90 include first inorganic particles 91 partially embedded in the resin 80 and second inorganic particles 92 embedded in the resin 80. The second inorganic particles are completely embedded in the resin 80. The first inorganic particles 91 and the second inorganic particles 92 are spherical in shape. Figure 2 As shown, first inorganic particles 91 are formed of first portions 91a protruding from resin 80 and second portions 91b buried in resin 80. First surface 22F of first resin insulating layer 20F is formed of upper surface 80R of resin 80 and exposed surface 91aR of first portion 91a exposed from upper surface 80R of resin 80.

[0038] The ratio R of the volume of the first part 91a to the volume of the first inorganic particle 91 (the volume of the first part 91a / the volume of the first inorganic particle 91) is greater than 0 and is less than 0.4. The ratio R is preferably less than 0.2. The ratio R is more preferably less than 0.1. The ratio R is most preferably less than 0.05. When the first part 91a protrudes from the resin 80, the first surface 22F of the first resin insulating layer 20F has tiny bumps. However, the upper surface 80R of the resin 80 is not rough. The upper surface 80R of the first surface 22F of the resin 80 forming the first resin insulating layer 20F is roughly flat. The upper surface 80R of the resin 80 has almost no concave portion. Therefore, the first surface 22F has almost no concave portion. The arithmetic mean roughness (Ra) of the first surface 22F is less than 0.08μm. The roughness Ra of the first surface 22F is preferably less than 0.05μm. The roughness Ra of the first surface 22F is more preferably less than 0.03μm. The arithmetic mean roughness (Ra) of the upper surface 80R of the resin 80 forming the first surface 22F of the first resin insulating layer 20F is less than 0.08 μm. The roughness Ra of the upper surface 80R of the resin 80 is preferably 0.05 μm or less. The roughness Ra of the upper surface 80R of the resin 80 is more preferably 0.03 μm or less.

[0039] like Figure 3A As shown, the inorganic particles 90 further include a third inorganic particle 93 forming an inner wall surface of an opening (an opening for a via conductor). The shape of the third inorganic particle 93 is obtained by cutting a sphere in a plane. The shape of the third inorganic particle 93 is obtained by cutting the second inorganic particle 92 in a plane. The shape of the third inorganic particle 93 is roughly a spherical segment. The shape of the third inorganic particle 93 is different from the shape of the second inorganic particle 92. The shape of the third inorganic particle 93 is different from the shape of the first inorganic particle 91. The shape of the first inorganic particle 91 is the same as the shape of the second inorganic particle 92.

[0040] Figure 4 FIG. 2 is a cross-sectional photograph showing an example of the inner wall surface 27F of the first opening 26F. Figure 3A and Figure 4 As shown, the inner wall surface 27F of the first opening 26F is formed by the resin 80 and the third inorganic particles 93. The third inorganic particles 93 have a flat portion 93a. The flat portion 93a forms the inner wall surface 27F. The inner wall surface 27F is formed by the resin 80 and the flat portion 93a. The flat portion 93a and the surface of the resin 80 forming the inner wall surface 27F form a substantially common surface. No irregularities are formed on the resin 80 forming the inner wall surface 27F. The surface of the resin 80 forming the inner wall surface 27F is smooth. No irregularities are formed on the exposed surface 93b of the flat portion 93a (the surface forming the inner wall surface 27F). The exposed surface 93b of the flat portion 93a is smooth. The inner wall surface 27F is smoothly formed. The arithmetic mean roughness (Ra) of the inner wall surface 27F is less than 1.0 μm. As shown Figure 4As shown, a step 28 is formed at the boundary between the surface 80a of the resin 80 and the flat portion 93a of the third inorganic particle 93. The amount of the step 28 is preferably less than 3.0 μm. The amount of the step 28 is more preferably less than 1.5 μm. The amount of the step 28 is further preferably less than 0.5 μm. For example, the distance between the exposed surface 93b and the surface 80a of the resin 80 (the surface forming the inner wall surface 27F) represents the amount of the step 28. The exposed surface 93b protrudes relative to the surface 80a of the resin 80. Alternatively, the exposed surface 93b is recessed relative to the surface 80a of the resin 80. Preferably protruding.

[0041] The flat portion 93a of the third inorganic particle 93 substantially coincides with a surface obtained by extending a surface (a surface forming the inner wall surface 27F) 80a of the resin 80 formed around the third inorganic particle 93. Figure 1 and Figure 3A The flat portion 93a depicted by a substantially straight line in FIG. 1 is a plane. Figure 1 and Figure 3A In the cross section shown, the flat portion 93a is a plane. The flat portion 93a may not be a completely flat surface. The flat portion 93a is a substantially flat surface and is a substantially smooth surface.

[0042] Figure 3B It is shown Figure 3A An enlarged cross-sectional view of a portion of the inner wall surface 27F in FIG. Figure 3B As shown, with respect to the reference plane 200 connecting the flat portions 93a of the two third inorganic particles 93 forming the inner wall surface 27F, the surface 80a of the resin 80 located therebetween may be recessed or protruded (see the dotted line portion). It is preferred that there is no other third inorganic particle 93 between the two third inorganic particles 93 used to form the reference plane 200. The distance between the reference plane 200 and the surface 80a of the resin 80 may also be used as a representative value of the amount of the step 28.

[0043] like Figure 3A As shown, the inner wall surface 27F of the first opening 26F is inclined. The angle (inclination angle) θ1 between the front surface 5F of the substrate 4 and the inner wall surface 27F is greater than 70° and less than 85°. The angle (inclination angle) θ2 between the first surface 22F of the first resin insulating layer 20F and the inner wall surface 27F is greater than 95° and less than 110°.

[0044] exist Figure 1 and Figure 3A In the cross section shown, the shape of the first opening 26F is shown as a substantially inverted trapezoid. However, the actual shape of the first opening 26F is a substantially inverted truncated cone. Therefore, the inner wall surface (side wall) 27F of the actual first opening 26F is a substantially curved surface. That is, the common surface formed by the flat portion 93a and the resin 80 includes the inner wall surface (side wall) 27F formed by a substantially curved surface.

[0045] like Figure 1 As shown, the first conductor layer 30F is formed on the first surface 22F of the first resin insulation layer 20F. The first conductor layer 30F includes a first signal wiring 32F, a second signal wiring 34F and a pad 36F. Although not shown, the first conductor layer 30F also includes a conductor circuit other than the first signal wiring 32F, the second signal wiring 34F and the pad 36F. The first signal wiring 32F and the second signal wiring 34F form a pair of wirings. The first conductor layer 30F is mainly formed of copper. The first conductor layer 30F is formed by a seed layer 30Fa and a plating layer 30Fb on the seed layer 30Fa. The seed layer 30Fa is formed by sputtering. The seed layer 30Fa is formed by a first layer 31Fa on the first surface 22F and a second layer 31Fb on the first layer 31Fa. The first layer 31Fa is in contact with the first surface 22F. The second layer 31Fb is not necessary. The first layer 31Fa and the second layer 31Fb are formed by sputtering. Both are sputtering films.

[0046] The first layer 31Fa is composed of an alloy containing copper and aluminum. The first layer 31Fa may also have a specific metal. Examples of specific metals are nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one specific metal, or two specific metals, or three specific metals. The content of aluminum in the alloy is greater than 1.0 at% and less than 15.0 at%. An example of a specific metal is silicon. The content of the specific metal in the alloy is greater than 0.5 at% and less than 10.0 at%. The first layer 31Fa may also contain impurities. Examples of impurities are oxygen and carbon. The first layer 31Fa may contain oxygen or carbon. The first layer 31Fa may contain oxygen and carbon. In an embodiment, the alloy also contains carbon. The content of carbon in the alloy is less than 50 ppm. The alloy also contains oxygen. The content of oxygen in the alloy is less than 100 ppm. The values ​​of the contents of the above-mentioned elements are examples. Among the elements forming the first layer 31Fa, the amount of copper is the largest. Next, the amount of aluminum is large. The amount of the specific metal is less than the amount of aluminum. Therefore, copper is the primary metal, aluminum is the first secondary metal, and the specific metal is the second secondary metal. The amount of impurities is smaller than the amount of the specific metal. The first layer 31Fa is a copper alloy.

[0047] The second layer 31Fb is formed of copper. The content of copper forming the second layer 31Fb is 99.9at% or more. The content of copper in the second layer 31Fb is preferably 99.95at% or more. The seed layer 30Fa is a copper alloy. The electroplating layer 30Fb is formed of copper. The content of copper forming the electroplating layer 30Fb is 99.9at% or more. The content of copper in the electroplating layer 30Fb is preferably 99.95at% or more.

[0048] The first resin insulating layer 20F is formed on a glass substrate 4. Since glass has excellent flatness, the first surface 22F of the first resin insulating layer 20F also has excellent flatness. If no conductor circuit is formed between the front surface 5F and the first resin insulating layer 20F, the first surface 22F can follow the front surface 5F. The first surface 22F can have the same flatness as the front surface 5F. The embodiment can form fine wiring on the first surface 22F. For example, the first conductor layer 30F can have wiring with a width of 1.5 μm or more and 3.5 μm or less. The width of the interval between adjacent wirings is 1.5 μm or more and 3.5 μm or less.

[0049] The first via-hole conductor 40F is formed in the first opening 26F. The first via-hole conductor 40F electrically connects the through-hole conductor 8 and the first conductor layer 30F. The first via-hole conductor 40F electrically connects the through-hole conductor 8 and the pad 36F of the first via-hole conductor 40F. The first via-hole conductor 40F is formed by a seed layer 30Fa and a plating layer 30Fb on the seed layer 30Fa. The seed layer 30Fa forming the first via-hole conductor 40F and the seed layer 30Fa forming the first conductor layer 30F are common. The plating layer 30Fb forming the first via-hole conductor 40F and the plating layer 30Fb forming the first conductor layer 30F are common. The seed layer 30Fa forming the first via-hole conductor 40F is formed by a first layer 31Fa formed on the inner wall surface 27F of the first opening 26F and on the upper end 8F of the through-hole conductor 8 exposed from the first opening 26F, and a second layer 31Fb on the first layer 31Fa. The first layer 31Fa forming the first via-hole conductor 40F is common to the first layer 31Fa forming the first conductor layer 30F. The second layer 31Fb forming the first via-hole conductor 40F is common to the second layer 31Fb forming the first conductor layer 30F. Figure 1 In the embodiment, the first via-hole conductor 40F is connected to the upper end 8F. The first layer 31Fa is in contact with the upper end 8F and the inner wall surface 27F of the through-hole conductor 8. The first via-hole conductor 40F is formed right above the upper end 8F.

[0050] Figure 3C It is schematically shown Figure 3A An enlarged cross-sectional view of a portion of the seed layer 30Fa on the inner wall surface 27F. Figure 4 FIG. 2 shows an example of a seed layer 30Fa. The seed layer 30Fa on the inner wall surface 27F is in contact with the inner wall surface 27F. Figure 3A , Figure 3C and Figure 4 As shown, the seed layer 30Fa forming the first via-hole conductor 40F has a substantially smooth first film 60 and a substantially smooth second film 70. The first film 60 is electrically connected to the second film 70. The first film 60 is continuous with the second film 70. Figure 4As shown, a portion of the first film 60 is formed on the second film 70. The front end 62 of the first film 60 is formed on the rear end 72 of the second film 70. The first film 60 and the second film 70 are formed simultaneously. The cross section of the seed layer 30Fa covering the inner wall surface 27F has a substantially step-like shape.

[0051] like Figure 3C As shown, the first layer 31Fa of the seed layer 30Fa has a first film 60a and a second film 70a. The first film 60a is electrically connected to the second film 70a. The first film 60a is continuous with the second film 70a. The front end 62a of the first film 60a is formed on the rear end 72a of the second film 70a. The cross section of the first layer 31Fa covering the inner wall surface 27F has a substantially stepped shape. The first layer 31Fa on the inner wall surface 27F is in contact with the inner wall surface 27F.

[0052] The second layer 31Fb of the seed layer 30Fa includes a first film 60b and a second film 70b. The first film 60b is electrically connected to the second film 70b. The first film 60b is continuous with the second film 70b. The front end 62b of the first film 60b is formed on the rear end 72b of the second film 70b. The cross section of the second layer 31Fb formed on the inner wall surface 27F has a substantially stepped shape.

[0053] In an embodiment, a portion of the first film 60 is laminated on the second film 70. A portion of the first film 60 overlaps the second film 70. A front end 62 of the first film 60 is laminated on a rear end 72 of the second film 70. A front end 62 of the first film 60 overlaps the rear end 72 of the second film 70.

[0054] The inner wall surface 27F of the embodiment is formed by a substantially smooth surface. If the first layer 31Fa follows the shape of the inner wall surface 27F, the first layer 31Fa on the inner wall surface 27F has a substantially smooth surface. The cross section of the first layer 31Fa has a linear shape. The seed layer 30Fa on the inner wall surface 27F has a substantially smooth surface. The cross section of the seed layer 30Fa has a linear shape. In this case, the electroplating layer 30Fb forming the first via-hole conductor 40F is formed on a smooth surface. For example, when the wiring substrate 2 is subjected to a large impact, peeling occurs between the first layer 31Fa on the inner wall surface 27F and the second layer 31Fb on the first layer 31Fa. Alternatively, peeling occurs between the seed layer 30Fa on the inner wall surface 27F and the electroplating layer 30Fb forming the first via-hole conductor 40F. In contrast, the cross sections of the seed layer 30Fa and the first layer 31Fa of the embodiment have a stepped shape. Therefore, peeling is difficult to occur.

[0055] In the case where the opening for the via conductor exposes the front side 5F, the first layer 31Fa contacts the glass substrate 4. The opening of the first example and the opening of the second example expose the front side 5F. Moreover, the opening of the first example and the opening of the second example expose the upper end 8F. The first layer 31Fa contains aluminum and the glass contains oxygen, so it is considered that the bonding strength between the first layer 31Fa and the substrate 4 is increased. Furthermore, if the first layer 31Fa contains silicon, the first layer 31Fa and the substrate 4 contain the same element (silicon). Furthermore, it is considered that the bonding strength between the first layer 31Fa and the substrate 4 is increased. If a part of the seed layer forming the via conductor contacts the glass substrate 4, even if the wiring substrate 2 is subjected to thermal shock, the via conductor is difficult to peel off from the through-hole conductor 8. The via conductor in contact with the upper end 8F is preferably in contact with the front side 5F. In this case, the seed layer (for example, the first layer 31Fa) forming such a via conductor contacts both the upper end 8F and the front side 5F. Similarly, it is preferred that the via conductor in contact with the lower end 8B contacts the back side 5B. In this case, the seed layer (e.g., the first layer) forming such a via conductor contacts both the lower end 8B and the back surface 5B. When an adhesive layer for bonding the resin insulating layer such as the first resin insulating layer 20F and the substrate 4 is arranged between the front surface 5F and the second surface 24F, the adhesive layer may also be a part of the resin insulating layer. The adhesive layer is included in the resin insulating layer. The adhesive layer includes an organic adhesive layer and an inorganic adhesive layer. The adhesive layer is formed of an insulating material.

[0056] The second resin insulating layer 120F is formed on the first surface 22F of the first resin insulating layer 20F and the first conductor layer 30F. The first conductor layer 30F is formed between the second resin insulating layer 120F and the first resin insulating layer 20F. The second resin insulating layer 120F has a first surface 122F and a second surface 124F on the opposite side of the first surface 122F. The second surface 124F of the second resin insulating layer 120F is opposite to the first conductor layer 30F. The second resin insulating layer 120F is formed of a resin 80 and inorganic particles (first inorganic particles 91, second inorganic particles 92, third inorganic particles 93) 90 in the same manner as the first resin insulating layer 20F. Therefore, the material of the second resin insulating layer 120F is the same as that of the first resin insulating layer 20F. The first surface 122F of the second resin insulating layer 120F is the same as the first surface 22F of the first resin insulating layer 20F. The first inorganic particles 91 forming the second resin insulating layer 120F have a first portion 91a and a second portion 91b, and an exposed surface 91aR of the first portion 91a forms a first surface 122F of the second resin insulating layer 120F. The first inorganic particles 91 in the first resin insulating layer 20F and the first inorganic particles 91 in the second resin insulating layer 120F have the same ratio R.

[0057] The second resin insulating layer 120F has a second opening 126F that exposes the first conductor layer 30F. The second opening 126F exposes the pad 36F. The second opening 126F has an inner wall surface 127F. The first opening 26F is identical to the second opening 126F. Therefore, the inner wall surface 27F of the first opening 26F is identical to the inner wall surface 127F of the second opening 126F.

[0058] The second conductor layer 130F is formed on the first surface 122F of the second resin insulating layer 120F. The second conductor layer 130F includes a first signal wiring 132F, a second signal wiring 134F, and a pad 136F. Although not shown in the figure, the second conductor layer 130F also includes a conductor circuit other than the first signal wiring 132F, the second signal wiring 134F, and the pad 136F. The first signal wiring 132F and the second signal wiring 134F form a pair of wirings. The second conductor layer 130F is the same as the first conductor layer 30F. Therefore, the second conductor layer 130F is formed by a seed layer 130Fa and a plating layer 130Fb on the seed layer 130Fa. The seed layer 130Fa is formed by a first layer 131Fa and a second layer 131Fb on the first layer 131Fa. The first layer 131Fa forming the second conductor layer 130F is the same as the first layer 31Fa forming the first conductor layer 30F. The second layer 131Fb forming the second conductor layer 130F is the same as the second layer 31Fb forming the first conductor layer 30F. The plating layer 130Fb forming the second conductor layer 130F is the same as the plating layer 30Fb forming the first conductor layer 30F.

[0059] The second via-hole conductor 140F is formed in the second opening 126F. The second via-hole conductor 140F electrically connects the first conductor layer 30F and the second conductor layer 130F. Figure 1, the second via conductor 140F electrically connects the pad 36F to the pad 136F. The second via conductor 140F is the same as the first via conductor 40F. Therefore, the second via conductor 140F is formed by the seed layer 130Fa and the electroplating layer 130Fb on the seed layer 130Fa. The seed layer 130Fa is formed by the first layer 131Fa and the second layer 131Fb on the first layer 131Fa. The first layer 131Fa forming the second via conductor 140F is the same as the first layer 31Fa forming the first conductor layer 30F. The second layer 131Fb forming the second via conductor 140F is the same as the second layer 31Fb forming the first conductor layer 30F. The electroplating layer 130Fb forming the second via conductor 140F is the same as the electroplating layer 30Fb forming the first conductor layer 30F. The first layer 131Fa forming the second via-hole conductor 140F and the first layer 131Fa forming the second conductor layer 130F are common. The second layer 131Fb forming the second via-hole conductor 140F and the second layer 131Fb forming the second conductor layer 130F are common. The plating layer 130Fb forming the second via-hole conductor 140F and the plating layer 130Fb forming the second conductor layer 130F are common.

[0060] The back side build-up layer 300B has a back side via conductor that penetrates the back side resin insulation layer, the back side conductor layer, and the back side resin insulation layer. The back side resin insulation layer and the back side conductor layer are alternately stacked. The back side conductor layer and the back side via conductor are electrically connected to the through-hole conductor 8. Figure 1 The resin insulation layer on the back side of the circuit is a first resin insulation layer 20B having a first surface 22B and a second surface 24B, and a second resin insulation layer 120B having a first surface 122B and a second surface 124B. The conductor layer on the back side is a first conductor layer 30B and a second conductor layer 130B. The first conductor layer 30B and the second conductor layer 130B include first signal wirings 32B, 132B and second signal wirings 34B, 134B. The via conductor on the back side is a first via conductor 40B and a second via conductor 140B.

[0061] The front side laminate 300F is the same as the back side laminate 300B. Therefore, the resin insulation layer on the front side of the front side laminate 300F is the same as the resin insulation layer on the back side of the back side laminate 300B. Each resin insulation layer on the back side is formed by a resin 80 and inorganic particles 90. Each resin insulation layer on the back side includes first inorganic particles 91, second inorganic particles 92, and third inorganic particles 93. The first surface of each resin insulation layer is formed by the upper surface 80R of the resin 80 and the exposed surface 91aR of the first part 91a exposed from the upper surface 80R of the resin 80. The conductor layer on the front side is the same as the conductor layer on the back side. The opening for the via conductor on the front side is the same as the opening for the via conductor on the back side. The inner wall surface of the opening for each via conductor is formed by the surface (exposed surface) 80a of the resin 80 and the exposed surface 93b of the inorganic particles. The surface 80a of the resin 80 and the exposed surface 93b of the inorganic particles form a substantially common surface. The via-conductor on the front side is the same as the via-conductor on the back side.

[0062] The length of each side of the wiring substrate 2 is 50 mm or more. The length of each side is preferably 100 mm or more. The length of each side is 250 mm or less. The length of the signal wiring formed according to the embodiment is 5 mm or more. The length of the signal wiring can be 10 mm or more and 20 mm or less.

[0063] [Method for Manufacturing Wiring Board 2 According to Embodiment]

[0064] Figure 5A to Figure 5M A method for manufacturing wiring board 2 according to the embodiment will be described. Figure 5A to Figure 5G , Fig.5I , Figure 5K , Figure 5M It is a cross-sectional view. Figure 5H , Figure 5J , Figure 5L is an enlarged cross-sectional view. Figure 5A 4 shows a glass substrate 4. The substrate 4 has a front surface 5F and a back surface 5B. Figure 5B As shown in FIG. 5 , a through hole 6 is formed from the front surface 5F to the back surface 5B. The through hole 6 penetrates the substrate 4. Laser is irradiated from the front surface 5F side of the substrate 4. Then, the substrate 4 is immersed in hydrofluoric acid. The through hole 6 is formed.

[0065] like Figure 5C As shown, a seed layer 10a is formed. The seed layer 10a is formed by chemical plating. The seed layer 10a is formed on the inner wall surface of the through hole 6, the front surface 5F, and the back surface 5B.

[0066] like Figure 5D As shown, a plating layer 10 b is formed. The plating layer 10 b is formed on the seed layer 10 a and fills the through hole 6 .

[0067] like Figure 5EAs shown, the plating layer 10b and the seed layer 10a on the front side 5F are removed by grinding. The plating layer 10b and the seed layer 10a on the back side 5B are removed by grinding. The front side 5F and the back side 5B of the substrate 4 are exposed. The through-hole conductor 8 is formed by the seed layer 10a on the inner wall surface of the through hole 6 and the plating layer 10b on the seed layer 10a. The upper end 8F of the through-hole conductor 8 is exposed from the front side 5F. The lower end 8B of the through-hole conductor 8 is exposed from the back side 5B. The surface forming the upper end 8F forms the same plane as the front side 5F. The surface forming the lower end 8B forms the same plane as the back side 5B. The core substrate 3 is formed. The core substrate 3 does not have a conductor circuit on the front side 5F. The core substrate 3 does not have a conductor circuit on the back side 5B.

[0068] The front side build-up layer 300F and the back side build-up layer 300B are formed in the same manner on the core substrate 3. The method for forming the front side build-up layer 300F is described below. The back side build-up layer 300B is also depicted in the figure.

[0069] like Fig. 5F As shown, a first resin insulating layer 20F and a protective film 50F are formed on the front surface 5F and the upper end 8F of the substrate 4. The second surface 24F of the first resin insulating layer 20F is opposite to the front surface 5F of the substrate 4. A protective film 50F is formed on the first surface 22F of the first resin insulating layer 20F. The first resin insulating layer 20F has a resin 80 and inorganic particles (second inorganic particles 92) 90. The inorganic particles 90 are buried in the resin 80. The first surface 22F of the first resin insulating layer 20F is formed only by the resin 80. The inorganic particles 90 are not exposed from the first surface 22F. The first surface 22F does not include the surface of the inorganic particles 90. No concavoconvexity is formed on the first surface 22F of the first resin insulating layer 20F. The first resin insulating layer 20F is formed on a plane formed by the front surface 5F and the upper end 8F. Therefore, the first surface 22F is formed by a substantially flat surface. The front surface 5F is substantially parallel to the first surface 22F.

[0070] like Figure 5G As shown, laser light L is irradiated from above the protective film 50F. The laser light L penetrates through the protective film 50F and the first resin insulating layer 20F at the same time. A first opening 26F for the via conductor reaching the upper end 8F of the through-hole conductor 8 is formed. The laser light L is, for example, UV laser, CO 2 Laser. Upper end 8F of via conductor 8 is exposed through first opening 26F. When first opening 26F is formed, first surface 22F is covered with protective film 50F. When first opening 26F is formed, even if resin scatters, it is possible to suppress the resin from adhering to first surface 22F.

[0071] The first surface 22F has excellent flatness. When the laser L is irradiated to the first surface 22F, the laser L is difficult to diffusely reflect. When forming each first opening 26F, the position of the focus of the laser L is easy to be consistent. The embodiment can form an opening for a via conductor with a small diameter. The diameter of each opening for a via conductor is approximately equal. For example, the embodiment can form an opening for a via conductor with a diameter of 15 μm or more and 35 μm or less. The size of the diameter is measured on the first surface 22F.

[0072] Figure 5H The inner wall surface 27Fb of the first opening 26F after laser irradiation is shown. The inner wall surface 27Fb is formed by the resin 80 and the inorganic particles 90 protruding from the resin 80. In order to control the shape of the inner wall surface, the inner wall surface 27Fb after laser irradiation is processed. It is preferred to selectively remove the inorganic particles 90 protruding from the resin 80. Thus, the third inorganic particles 93 are formed by the inorganic particles 90. For example, by treating the inner wall surface 27Fb after laser irradiation with chemicals, the inorganic particles 90 protruding from the resin 80 are selectively removed. Alternatively, by treating the inner wall surface 27Fb after laser irradiation with plasma, the inorganic particles 90 protruding from the resin 80 are selectively removed. The etching speed of the inorganic particles 90 is greater than the etching speed of the resin 80. For example, the difference in etching speed between the two is more than 10 times. Or, the difference in etching speed between the two is more than 50 times. Or, the difference in etching speed between the two is more than 100 times. By processing the inner wall surface 27Fb after laser irradiation, the third inorganic particle 93 having the flat portion 93a is obtained. By controlling the conditions for processing the inner wall surface 27Fb after laser irradiation, the embodiment can control the shape of the inner wall surface 27F. Examples of the conditions are temperature, concentration, time, type of gas, and pressure. The etching speed of the inorganic particle 90 and the etching speed of the resin are controlled.

[0073] By irradiating the first resin insulating layer 20F with laser light L, a portion of the second inorganic particle 92 embedded in the resin 80 forms the inner wall surface 27Fb after laser irradiation. The second inorganic particle 92 forming the inner wall surface 27Fb after laser irradiation is formed by a protruding portion P protruding from the resin 80 and a portion E embedded in the resin 80. An inorganic particle having a protruding portion P is called a protruding particle. For example, with respect to a protruding particle, the protruding portion P is not removed at all. The inner wall surface 27Fb after laser irradiation is treated. For example, the inner wall surface 27Fb is treated with a plasma containing a gas of tetrafluoromethane. The protruding portion P is selectively removed to form the inner wall surface 27F of the embodiment. The third inorganic particle 93 is formed by the second inorganic particle 92. By selectively removing the protruding portion P, a third inorganic particle 93 having a flat portion 93a is formed. The flat portion 93a is a plane. When the second inorganic particle 92 having a spherical shape is cut by a plane, the shape of the third inorganic particle 93 is obtained. The shape of the third inorganic particle 93 is substantially a spherical segment. The inner wall surface 27F is formed by the flat portion 93a and the surface 80a of the resin 80, and the exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 are located on substantially the same plane. Figure 4 As shown, a step 28 is formed at the boundary portion of the surface 80a of the resin 80 forming the inner wall surface 27F and the flat portion 93a of the third inorganic particle 93. For example, if a seed layer 30Fa is formed on the inner wall surface 27Fb by sputtering, the protruding portion P hinders the growth of the sputtered film (sputtering film). For example, a continuous seed layer 30Fa is not formed on the inner wall surface 27Fb. Alternatively, it is necessary to thicken the thickness of the seed layer 30Fa. It is believed that if the printed wiring board contains protruding particles, it is difficult to form a fine conductor circuit. In an embodiment, the protruding portion P is removed. The embodiment can make the thickness of the seed layer 30Fa formed by sputtering thinner. Even if the thickness of the seed layer 30Fa formed by sputtering is thin, a continuous seed layer 30Fa can be obtained. When there is a step 28, it is preferred that the surface 80a of the resin is recessed from the exposed surface 93b of the flat portion 93a. The surface 80a of the resin can also protrude from the exposed surface 93b of the flat portion 93a. By controlling the conditions for processing the inner wall surface 27Fb after laser irradiation, the size of the concavo-convex and the size of the step 28 can be controlled.

[0074] Forming the first opening 26F includes forming inorganic particles (second inorganic particles 92) 90 having a protruding portion P. The protruding portion P protrudes from the resin 80 forming the inner wall surface 27Fb of the first opening 26F. The third inorganic particles 93 are formed by removing the protruding portion P of the inorganic particles (second inorganic particles 92) 90. The inner wall surface 27F of the first opening 26F includes an exposed surface 93b of the third inorganic particle 93. The exposed surface 93b of the third inorganic particle 93 is formed by removing the protruding portion P.

[0075] The shape of the third inorganic particle 93 obtained by cutting the second inorganic particle 92 having a spherical shape in a plane includes removing the protruding portion P of the inorganic particle 90. The inner wall surface 27F of the actual first opening 26F is a substantially curved surface. The flat portion 93a is formed by removing the protruding portion P, so the exposed surface 93b of the flat portion 93a includes a curved surface. That is, the flat portion 93a and the resin 80 form a common surface, including forming an inner wall surface 27F formed by a substantial curved surface.

[0076] Cleaning the inside of the first opening 26F. By cleaning the inside of the first opening 26F, the resin residue generated when the first opening 26F is formed is removed. The cleaning inside the first opening 26F is performed by plasma. That is, the cleaning is performed by a dry process. The cleaning includes desmear treatment.

[0077] When cleaning the first opening 26F, the first surface 22F of the first resin insulating layer 20F is covered by the protective film 50F. The first surface 22F is not affected by the plasma. The first surface 22F is formed only by the resin 80. The inorganic particles 90 are not exposed from the first surface 22F. The first surface 22F does not include the surface of the inorganic particles 90. The first surface 22F of the first resin insulating layer 20F has no unevenness. The first surface 22F is formed smoothly.

[0078] When processing the inner wall surface 27Fb after laser irradiation includes cleaning the inside of the first opening 26F, the embodiment can eliminate the step of cleaning the inside of the first opening 26F.

[0079] like Fig.5I As shown, after cleaning the inside of the first opening 26F, the protective film 50F is removed from the first resin insulating layer 20F. In the case where the processing of the inner wall surface 27Fb after laser irradiation includes cleaning the inside of the first opening 26F, the protective film 50F is removed from the first resin insulating layer 20F after processing the inner wall surface 27Fb after laser irradiation. When the inner wall surface 27Fb after laser irradiation is processed, the protective film 50F covers the first surface 22F of the first resin insulating layer 20F. After removing the protective film 50F, the first surface 22F of the first resin insulating layer 20F is not roughened.

[0080] After the protective film 50F is removed, the first surface 22F of the first resin insulating layer 20F is cleaned. The resin 80 forming the first surface 22F is removed by a dry process. For example, the first surface 22F of the first resin insulating layer 20F is cleaned by reverse sputtering. For example, the first surface 22F of the first resin insulating layer 20F is cleaned by sputtering using argon gas (argon sputtering). Figure 5J (a) Figure 5J (b) schematically shows the first surface 22F of the first resin insulation layer 20F before and after cleaning. Figure 5J (a) Figure 5J As shown in (b), the resin 80 forming the first resin insulating layer 20F is removed by about 20 nm by cleaning based on sputtering or the like. For example, the adhesive material used to bond the protective film 50F to the first resin insulating layer 20F is removed. The resin 80 is selectively removed by cleaning. The thickness of the resin 80 becomes thinner. A portion of the inorganic particles (second inorganic particles 92) 90 is partially exposed from the upper surface of the resin 80 by cleaning. By exposing the second inorganic particles 92 embedded in the resin 80 from the upper surface of the resin 80, the first inorganic particles 91 are obtained. The first inorganic particles 91 are formed by the second inorganic particles 92. The shape of the first inorganic particles 91 is the same as that of the second inorganic particles 92. Both are spherical in shape. As shown in FIG. Figure 5J As shown in (b), the first inorganic particle 91 is formed by a first portion 91a protruding from the resin 80 and a second portion 91b embedded in the resin 80. The first surface 22F of the first resin insulating layer 20F is formed by the upper surface 80R of the resin 80 and the exposed surface 91aR of the first portion 91a protruding from the upper surface 80R of the resin 80. The exposed surface 91aR of the first portion 91a is exposed by cleaning. The first surface 22F of the first resin insulating layer 20F is not roughened. Therefore, almost no recess is formed on the first surface 22F. The first surface 22F has almost no recess. The upper surface 80R of the resin 80 is roughly flat. The upper surface 80R of the resin 80 has no recess.

[0081] For example, use Figure 5J The calculation is performed based on the cross-sectional view of the first inorganic particle 91 shown in (b). Figure 5J (b) is obtained by cutting the first resin insulating layer 20F along a plane perpendicular to the upper surface 80R. Figure 5J The first conductor layer 30F is omitted in (b). Figure 5J The first conductive layer 30F is formed on the first inorganic particles 91 in (b). Figure 5J The exposed surface 91aR in (b) is covered by the first conductor layer 30F. Figure 5J (b), the cross-sectional area 91aS of the first portion 91a is obtained. Similarly, the cross-sectional area 91S of the first inorganic particle 91 is obtained. For example, the ratio R is represented by the ratio of the cross-sectional area 91aS to the cross-sectional area 91S (the cross-sectional area 91aS of the first portion 91a / the cross-sectional area 91S of the first inorganic particle 91). For example, when evaluating the ratio R, 50 first inorganic particles 91 are observed. The 50 first inorganic particles 91 satisfy the ratio R.

[0082] like Figure 5KAs shown, a seed layer 30Fa is formed on the first surface 22F of the first resin insulating layer 20F. The seed layer 30Fa is formed by sputtering. The formation of the seed layer 30Fa is performed by a dry process. The seed layer 30Fa is also formed on the upper end 8F of the through-hole conductor 8 exposed from the first opening 26F and the inner wall surface 27F of the first opening 26F. The seed layer 30Fa is mainly formed of copper. The first layer 31Fa is formed on the first surface 22F by sputtering. The first layer 31Fa is formed by sputtering on the inner wall surface 27F exposed from the first opening 26F and the upper end 8F of the through-hole conductor 8. The second layer 31Fb is formed on the first layer 31Fa by sputtering. The first layer 31Fa is formed by an alloy containing copper, aluminum and a specific metal (such as silicon). The second layer 31Fb is formed by copper.

[0083] like Figure 5L As shown, the first layer 31Fa formed on the inner wall surface 27F has a first film 60a and a second film 70a. The first film 60a and the second film 70a are formed simultaneously. The first film 60a is electrically connected to the second film 70a. The front end 62a of the first film 60a is formed on the rear end 72a of the second film 70a. The cross section of the first layer 31Fa formed on the inner wall surface 27F has a substantially stepped shape. Examples of sputtering conditions are shown below. The distance between the target and the first surface 22F of the first resin insulating layer 20F is greater than 50 mm and less than 250 mm. The voltage is greater than 15 eV and less than 50 eV. The gas concentration is greater than 0.1 Pa and less than 1.0 Pa.

[0084] The second layer 31Fb formed on the first layer 31Fa covering the inner wall surface 27F includes a first film 60b and a second film 70b. The first film 60b and the second film 70b are formed simultaneously. The first film 60b is electrically connected to the second film 70b. The front end 62b of the first film 60b is formed on the rear end 72b of the second film 70b. The cross section of the second layer 31Fb formed on the inner wall surface 27F has a substantially stepped shape. The conditions for sputtering are substantially the same as those described above.

[0085] The inner wall surface 27F of the embodiment is formed by the surface 80a of the resin 80 and the exposed surface 93b of the third inorganic particle 93. The two form a roughly common surface. The surface 80a of the resin and the exposed surface 93b are formed by different materials. Moreover, the first layer 31Fa is formed by sputtering. It is believed that the growth of the first layer 31Fa formed on the surface 80a of the resin 80 is different from the growth of the first layer 31Fa formed on the exposed surface 93b. It is believed that the growth of the seed layer 30Fa formed on the surface 80a of the resin 80 is different from the growth of the seed layer 30Fa formed on the exposed surface 93b. Therefore, in the embodiment, it is believed that the first film 60a and the second film 70a are formed. It is believed that the front end 62a of the first film 60a is formed on the rear end 72a of the second film 70a. It is believed that the cross section of the first layer 31Fa has a roughly stepped shape. It is believed that the second layer 31Fb follows the first layer 31Fa. Therefore, it is believed that the second layer 31Fb has the first film 60b and the second film 70b. It is considered that the front end 62b of the first film 60b of the second layer 31Fb is formed on the rear end 72b of the second film 70b of the second layer 31Fb. It is considered that the cross section of the second layer 31Fb has a substantially stepped shape. Similarly, it is considered that the seed layer 30Fa has a first film 60 and a second film 70. It is considered that the front end 62 of the first film 60 of the seed layer 30Fa is formed on the rear end 72 of the second film 70 of the seed layer 30Fa. It is considered that the cross section of the seed layer 30Fa has a substantially stepped shape.

[0086] If the inner wall surface 27F has Figure 4 The step 28 shown in the figure can easily form the first layer 31Fa having the first film 60a and the second film 70a by sputtering. The embodiment can easily form the seed layer 30Fa having the first film 60 and the second film 70. The embodiment can form the front end 62a of the first film 60a on the rear end 72a of the second film 70a. The embodiment can form the front end 62 of the first film 60 on the rear end 72 of the second film 70. The embodiment can easily form the first layer 31Fa having a substantially step-like shape. The embodiment can easily form the seed layer 30Fa having a substantially step-like shape.

[0087] The first layer 31Fa on the inner wall surface 27F is formed on the substantially smooth inner wall surface 27F. Therefore, the embodiment can form the surface of the first film 60a of the first layer 31Fa and the surface of the second film 70a of the first layer 31Fa substantially smoothly. Similarly, the surface of the first film 60b of the second layer 31Fb and the surface of the second film 70b of the second layer 31Fb can be substantially smoothly formed. The surface of the first film 60 of the seed layer 30Fa and the surface of the second film 70 of the seed layer 30Fa can be substantially smoothly formed. Since the surface is smooth, the embodiment can reduce the transmission loss.

[0088] The first layer 31Fa of the seed layer 30Fa is formed by an alloy containing copper and aluminum. Aluminum has high ductility and high ductility. Therefore, the adhesion between the first resin insulating layer 20F and the first layer 31Fa is high. It is believed that even if the first resin insulating layer 20F expands and contracts due to thermal cycles, the seed layer 30Fa containing aluminum can also follow the expansion and contraction. Even if the first surface 22F is smooth, the seed layer 30Fa is difficult to peel off from the first resin insulating layer 20F. It is believed that aluminum is easily oxidized. It is believed that if the third inorganic particle 93 is an inorganic particle 90 containing oxygen (oxygen element), the first layer 31Fa formed on the inner wall surface 27F of the first opening 26F is closely attached to the third inorganic particle 93 via the oxygen in the inorganic particle 90 forming the inner wall surface 27F. The first layer 31Fa is firmly bonded to the inner wall surface 27F. The embodiment can improve the adhesion between the inner wall surface 27F of the first opening 26F and the first layer 31Fa. The seed layer 30Fa is difficult to peel off from the inner wall surface 27F. The inorganic particles 90 forming the inner wall surface 27F preferably contain oxygen. The third inorganic particles 93 are glass particles, and when the first layer 31Fa also contains silicon, both contain silicon. In this case, the first layer 31Fa is formed by an alloy containing copper, aluminum and silicon. It is believed that the two are firmly bonded via silicon. Therefore, it is believed that the bonding force between the first layer 31Fa and the third inorganic particles 93 is further improved.

[0089] The first surface 22F has excellent flatness. When the seed layer 30Fa is formed on the first surface 22F by sputtering, the distance between the target and the first surface 22F is substantially constant. The embodiment can form the seed layer 30Fa having a substantially uniform thickness.

[0090] The first layer 31Fa of the seed layer 30Fa contacts the exposed surface 91aR of the first part 91a of the first inorganic particle 91 forming the first surface 22F of the first resin insulating layer 20F. It is considered that if the first layer 31Fa contains aluminum and the first inorganic particle 91 contains oxygen, the adhesion between the first layer 31Fa and the first inorganic particle 91 is improved. Examples of the oxygen-containing inorganic particles (first inorganic particles, etc.) 90 are glass particles and aluminum oxide particles. Therefore, when the first layer 31Fa is formed by an alloy containing copper and aluminum, even if the first surface 22F of the first resin insulating layer 20F has almost no recess, the first layer 31Fa is difficult to peel off from the first resin insulating layer 20F. The amount of aluminum in the first layer 31Fa is 1.0 at% or more and 15.0 at% or less. The inorganic particles (first inorganic particles 91, second inorganic particles 92, third inorganic particles 93) containing the first inorganic particles 91 are glass particles, and when the first layer 31Fa also contains silicon, both contain silicon. In this case, the first layer 31Fa is formed of an alloy containing copper, aluminum and silicon. The amount of silicon is greater than 0.5 at% and less than 10.0 at%. It is believed that the two are firmly bonded via silicon. Therefore, it is believed that the bonding force between the first layer 31Fa and the inorganic particles containing the first inorganic particles 91 is further improved. The embodiment can form a fine first signal wiring 32F and a second signal wiring 34F. The width of the fine first signal wiring 32F and the second signal wiring 34F is greater than 1 μm and less than 3 μm. Even if the wiring substrate 2 having the fine first signal wiring 32F and the second signal wiring 34F is subjected to thermal shock, the first signal wiring 32F and the second signal wiring 34F are difficult to peel off from the first resin insulation layer 20F.

[0091] A plating resist is formed on the seed layer 30Fa. The plating resist has an opening for forming the first signal wiring 32F, the second signal wiring 34F and the pad 36F. If the first surface 22F has a recess, the air caused by the recess is easily enclosed between the plating resist and the seed layer 30Fa. However, in an embodiment, the first surface 22F has almost no recess. Therefore, the seed layer 30Fa on the first surface 22F is formed to be roughly flat. The seed layer 30Fa has almost no recess. It is difficult for air to remain between the plating resist and the seed layer 30Fa. The contact area between the plating resist and the seed layer 30Fa is large. Even if the width of the plating resist used to form the space between the signal wirings is less than 10μm, the plating resist is difficult to peel off from the upper surface of the seed layer 30Fa. Even if the width of the plating resist is more than 3μm and less than 8μm, the embodiment can also form the plating resist on the seed layer 30Fa. Even if the width of the plating resist is 6 μm or less, the plating resist is unlikely to be peeled off from the seed layer 30Fa.

[0092] The electroplating layer 30Fb is formed on the seed layer 30Fa exposed from the plating resist. The electroplating layer 30Fb fills the first opening 26F. The first signal wiring 32F, the second signal wiring 34F and the pad 36F are formed by the seed layer 30Fa and the electroplating layer 30Fb on the first surface 22F. The first conductor layer 30F is formed. The first via conductor 40F is formed by the seed layer 30Fa and the electroplating layer 30Fb in the first opening 26F. The first via conductor 40F connects the through-hole conductor 8 to the pad 36F. The first signal wiring 32F and the second signal wiring 34F form a pair of wirings.

[0093] Remove the plating resist. Remove the seed layer 30Fa exposed from the electroplating layer 30Fb. Figure 5M As shown, the first conductor layer 30F and the first via-hole conductor 40F are formed at the same time.

[0094] The second resin insulating layer 120F is formed on the first surface 22F of the first resin insulating layer 20F and the first conductor layer 30F. The second conductor layer 130F is formed on the first surface 122F of the second resin insulating layer 120F. The second via conductor 140F is formed in the second opening 126F of the second resin insulating layer 120F. The second resin insulating layer 120F is formed by the same method as the first resin insulating layer 20F. The second conductor layer 130F is formed by the same method as the first conductor layer 30F. The second via conductor 140F is formed by the same method as the first via conductor 40F. The wiring substrate 2 of the embodiment is obtained.

[0095] The core substrate 3 of the wiring substrate 2 of the embodiment includes a glass substrate 4. The glass substrate 4 has excellent flatness. The first surfaces 22F and 22B of the first resin insulating layers 20F and 20B have excellent flatness and smoothness. The embodiment can form fine signal wirings 32F, 32B, 34F, and 34B on the first surfaces 22F and 22B of the first resin insulating layers 20F and 20B. The first surfaces 122F and 122B of the second resin insulating layers 120F and 120B are also the same as the first surfaces 22F and 22B of the first resin insulating layers 20F and 20B. Therefore, the embodiment can form fine signal wirings 132F, 132B, 134F, and 134B on the first surfaces 122F and 122B of the second resin insulating layers 120F and 120B. The L / S of the signal wiring formed according to the embodiment is, for example, less than 5μm / 5μm. The L / S of the signal wiring is preferably not less than 1.5 μm / 1.5 μm and not more than 3.5 μm / 3.5 μm. L represents the width of the signal wiring, and S represents the width of the space between adjacent signal wirings.

[0096] In the embodiment, the first layer formed on the inner wall surface of the opening for the via conductor is formed by sputtering. The resin insulating layer on the glass substrate 4 is difficult to warp. It is difficult to generate a gap that hinders the growth of the sputtering film between the resin 80 and the third inorganic particles 93 that form the inner wall surface of the opening for the via conductor. It is difficult for the inner wall surface of the opening to have large undulations and large concavities and convexities. Even if the thickness of the sputtering film on the inner wall surface is thin, the embodiment can form a continuous sputtering film.

[0097] The inner wall surface of the opening (first opening, second opening) for the via conductor is formed by the resin 80 and the exposed surface 93b of the flat portion 93a of the third inorganic particle 93. It is believed that when the first layer is formed, the particles forming the sputtering film are attached to the third inorganic particle 93. It is believed that the particles forming the sputtering film are not buried in the third inorganic particle 93. The embodiment can form a thin and continuous seed layer on the inner wall surface. The embodiment can form a thin and continuous seed layer on the first surface and the inner wall surface. When the seed layer is removed, the etching amount is small. Therefore, the etching amount of the electroplating layer is small. The signal wiring has a width like the design value. The embodiment can form a fine signal wiring. A wiring substrate 2 with high quality can be provided.

[0098] In the wiring substrate 2 of the embodiment, the first surface 22F of the first resin insulating layer 20F is formed by the upper surface 80R of the resin 80 and the exposed surface 91aR of the first part 91a exposed from the upper surface 80R of the resin 80. The first surface 22F and the upper surface 80R have almost no recesses. Therefore, in the case where the seed layer 30Fa is formed on the first resin insulating layer 20F by sputtering, even if the thickness of the sputtering film is thin, the embodiment can form a continuous seed layer 30Fa. The seed layer 30Fa is formed thin. When the seed layer 30Fa is removed, the etching amount is small. Therefore, the etching amount of the electroplating layer 30Fb is small. The signal wiring has a width like the design value. Fine wiring is formed. It is possible to provide a wiring substrate 2 with high quality.

[0099] The embodiment can reduce the thickness of the first layer 31Fa composed of an alloy containing copper and aluminum. The aluminum content in the signal wiring is small, and the copper content is large. The embodiment can provide a low-resistance signal wiring. The embodiment can provide a signal wiring having high adhesion to the resin insulating layer.

[0100] In the wiring substrate 2 of the embodiment, the first surface 22F, 22B of the first resin insulating layer 20F, 20B has almost no recess. The standard deviation of the relative dielectric constant of the portion near the first surface 22F, 22B of the first resin insulating layer 20F, 20B is suppressed from becoming larger. The relative dielectric constant of the first surface 22F, 22B does not change significantly depending on the position. Even if the first signal wiring 32F, 32B and the second signal wiring 34F, 34B are in contact with the first surface 22F, 22B, the embodiment can reduce the difference in propagation speed of the electrical signal between the first signal wiring 32F, 32B and the second signal wiring 34F, 34B. Therefore, noise is suppressed in the wiring substrate 2 of the embodiment. Even if a logic IC is installed on the wiring substrate 2 of the embodiment, the data transmitted by the first signal wiring 32F, 32B and the data transmitted by the second signal wiring 34F, 34B reach the logic IC almost without delay. The embodiment can suppress malfunction of the logic IC. Even if the length of the first signal wiring 32F, 32B and the length of the second signal wiring 34F, 34B are 5 mm or more, the embodiment can reduce the difference in propagation speed between the two. Even if the length of the first signal wiring 32F, 32B and the length of the second signal wiring 34F, 34B are 10 mm or more and 20 mm or less, the embodiment can suppress malfunction of the logic IC. The first surface 122F, 122B of the second resin insulating layer 120F, 120B is also the same as the first surface 22F, 22B of the first resin insulating layer 20F, 20B. Therefore, the first signal wiring 132F, 132B and the second signal wiring 134F, 134B also have the same effect as the first signal wiring 32F, 32B and the second signal wiring 34F, 34B. It is possible to provide a wiring substrate 2 with high quality.

[0101] In an embodiment, a portion of the first film of the seed layer covering the inner wall surface of the opening (first opening, second opening) for the via conductor is formed on the second film. The first film partially overlaps the second film. Therefore, the strength of the seed layer is high. Since the thermal expansion coefficient of the glass core substrate 3 is greatly different from the thermal expansion coefficient of the resin insulation layer, when the wiring substrate 2 is subjected to a thermal cycle, stress acts between the resin insulation layer and the seed layer. It is believed that even if the resin insulation layer expands and contracts due to the thermal cycle, the stress can be relieved by partially overlapping the first film and the second film. Alternatively, it is believed that the seed layer can follow the expansion and contraction. Therefore, the seed layer is difficult to break. The seed layer is formed by a roughly smooth first film and a roughly smooth second film. Therefore, when transmitting a high-frequency signal, the transmission loss is small. A high-quality wiring substrate 2 can be provided.

[0102] The first layer contains silicon as a specific metal, and when the inorganic particles are glass particles, the first layer on the inner wall surface and the third inorganic particles 93 contain silicon. The first layer and the first inorganic particles 91 on the first surface contain silicon. It is believed that the two are firmly bonded via silicon. The seed layer is difficult to peel off from the inner wall surface. The seed layer is difficult to peel off from the first surface. Therefore, the first layer is preferably an alloy containing copper, aluminum and silicon.

[0103] It is considered that if the first layer contains aluminum and the inorganic particles (first inorganic particles 91, second inorganic particles 92, third inorganic particles 93) 90 contain oxygen, the first layer is firmly bonded to the inorganic particles (inorganic particles containing oxygen such as glass particles) 90. In the case where the first layer contains aluminum and the inorganic particles 90 contain oxygen, the first layer may not contain the specific metal. In this case, the first layer is formed of copper, aluminum, and impurities.

[0104] [Another Example 1 of Implementation]

[0105] In another example 1 of the embodiment, the specific metal included in the alloy forming the first layer is at least one of nickel, zinc, gallium, silicon, and magnesium.

[0106] [Another Example 2 of Implementation Method]

[0107] In another embodiment example 2, the alloy forming the first layer does not contain carbon.

[0108] [Another Example 3 of Implementation]

[0109] In another example 3 of the embodiment, the alloy forming the first layer does not contain oxygen.

[0110] [Modification of the embodiment]

[0111] The wiring substrate of the modified example has a core substrate 3, a front side buildup layer 300F, and a back side buildup layer 300B in the same manner as in the embodiment. The core substrate 3 of the embodiment is different from the core substrate 3 of the modified example. The front side buildup layer 300F of the embodiment is the same as the front side buildup layer 300F of the modified example. The back side buildup layer 300B of the embodiment is the same as the back side buildup layer 300B of the modified example. The cross section of the core substrate 3 of the modified example is as follows: Figure 6 and Figure 7 As shown. Figure 6 and Figure 7As shown, the core substrate 3 of the modified example has conductor layers 10F and 11F on the front surface 5F of the glass substrate 4. The conductor layers 10F and 11F include a pad 14F covering the upper end 8F of the through-hole conductor 8. In addition, the core substrate 3 of the modified example has conductor layers 10B and 11B on the back surface 5B of the substrate 4. The conductor layers 10B and 11B include a pad 14B covering the lower end 8B of the through-hole conductor 8. The pad 14F and the pad 14B are electrically connected through the through-hole conductor 8. The core substrate 3 of the embodiment does not have a conductor layer on the front surface 5F and a conductor layer on the back surface 5B.

[0112] In the modified example, the resin insulation layer (resin insulation layer directly above the core substrate) forming the front side of the front side build-up layer 300F is formed on the conductor layers 10F, 11F and the front side 5F. The resin insulation layer (first resin insulation layer 20F) directly above the core substrate has an opening (first opening 26F) for a via conductor that reaches the pad 14F. A via conductor (first via conductor 40F) that is the same as in the embodiment is formed in the opening for the via conductor. The via conductor that passes through the resin insulation layer directly above the core substrate reaches the pad 14F, so the seed layer (first layer 31Fa) that forms the via conductor is in contact with the upper surface of the pad 14F and the inner wall surface of the opening. The via conductor that passes through the resin insulation layer directly above the core substrate is electrically connected to the through-hole conductor 8 via the pad 14F.

[0113] In the modified example, the resin insulation layer (resin insulation layer directly below the core substrate) on the back side of the back side build-up layer 300B is formed on the conductor layers 10B, 11B and the back side 5B. The resin insulation layer (first resin insulation layer 20B) directly below the core substrate has an opening (first opening) for a via conductor that reaches the pad 14B. A via conductor (first via conductor 40B) similar to that in the embodiment is formed in the opening for the via conductor. The via conductor that passes through the resin insulation layer directly below the core substrate reaches the pad 14B, so the seed layer that forms the via conductor contacts the upper surface of the pad 14B and the inner wall surface of the opening. The via conductor that passes through the resin insulation layer directly below the core substrate is electrically connected to the through-hole conductor 8 via the pad 14B.

[0114] [Manufacturing method of wiring substrate according to modification example]

[0115] Figure 6 The core substrate 3 shown is a core substrate 3 of the first example. The method for manufacturing the core substrate 3 of the first example is as follows. Figure 5D The intermediate substrate shown in FIG. The conductor layer 10F is formed on the front surface 5F by a subtractive method. The conductor layer 10B is formed on the back surface 5B. The core substrate 3 of the first example of the modification is obtained.

[0116] The conductor layer 10F is formed by a seed layer 10a and an electroplating layer 10b on the seed layer 10a. The conductor layer 10B is formed by a seed layer 10a and an electroplating layer 10b on the seed layer 10a. The seed layer 10a is formed by chemical plating. The seed layer 10a forming the conductor layer 10F, the seed layer 10a forming the conductor layer 10B, and the seed layer 10a forming the through-hole conductor 8 are common. The electroplating layer 10b forming the conductor layer 10F, the electroplating layer 10b forming the conductor layer 10B, and the electroplating layer 10b forming the through-hole conductor 8 are common. The conductor layers 10F, 10B, and the through-hole conductor 8 are formed simultaneously. The through-hole conductor 8 and the pads 14F, 14B are formed simultaneously. The through-hole conductor 8 and the pads 14F, 14B are formed integrally. There is no seed layer between the upper end 8F and the pad 14F. There is no seed layer between lower end 8B and pad 14B.

[0117] Figure 7 The core substrate 3 shown is a core substrate 3 of the second example. The manufacturing method of the core substrate 3 of the second example is as follows. Figure 5E The intermediate substrate shown. Seed layers 11Fa and 11Ba are formed on the front surface 5F and the back surface 5B. The seed layers 11Fa and 11Ba are formed by chemical plating. The seed layers 11Fa and 11Ba can also be formed by sputtering. The seed layer 11Fa covers the front surface 5F of the substrate 4 and the upper end 8F of the through-hole conductor 8. The seed layer 11Ba covers the back surface 5B of the substrate 4 and the lower end 8B of the through-hole conductor 8. Electroplating layers 11Fb and 11Bb are formed on the seed layers 11Fa and 11Ba. Then, the conductor layers 11F and 11B are formed by a subtractive method. The core substrate 3 of the second example of the modified example is obtained.

[0118] The conductor layer 11F is formed by a seed layer 11Fa and a plating layer 11Fb on the seed layer 11Fa. The conductor layer 11B is formed by a seed layer 11Ba and a plating layer 11Bb on the seed layer 11Ba. The seed layer 11Fa is formed on the front surface 5F of the substrate 4. The seed layer 11Fa covers the upper end 8F of the through-hole conductor 8. The seed layer 11Ba is formed on the back surface 5B of the substrate 4. The seed layer 11Ba covers the lower end 8B of the through-hole conductor 8. The seed layers 11Fa and 11Ba are formed by chemical plating. The seed layers 11Fa and 11Ba can also be formed by sputtering. The seed layers 11Fa and 11Ba that form the conductor layers 11F and 11B are different from the seed layer 10a that forms the through-hole conductor 8. The plating layers 11Fb and 11Bb that form the conductor layers 11F and 11B are different from the plating layer 10b that forms the through-hole conductor 8. Conductor layers 11F, 11B and through-hole conductors 8 are formed separately. In the second example, a seed layer 11Fa for forming pads 14F exists between the plating layer 10b for forming upper end 8F and the plating layer 11Fb for forming pads 14F. A seed layer 11Ba for forming pads 14B exists between the plating layer 10b for forming lower end 8B and the plating layer 11Bb for forming pads 14B. In contrast, in the first example ( Figure 6 ), the plating layer 10b forming the upper end 8F is continuous with the plating layer 10b forming the pad 14F. The plating layer 10b forming the lower end 8B is continuous with the plating layer 10b forming the pad 14B.

[0119] On the core substrate 3 of the modification, the front side build-up layer 300F and the back side build-up layer 300B are formed by the same method as the embodiment.

[0120] In this specification, the term "plane" is used to refer to the shape of the inner wall surface, the shape of the flat portion 93a, and the shape of the third inorganic particle 93. The plane used in these terms means Figure 1 and Figure 3A That is, in Figure 1 and Figure 3A In the figure, the inner wall surface is drawn roughly straight. Figure 1 and Figure 3A The shape of the inner wall surface in the cross section is generally a straight line. The plane in this specification includes the substantial straight line shown in the cross section. Figure 1 and Figure 3A As shown in the cross section of the third inorganic particle 93, in the cross section, cutting with a plane includes cutting with a straight line. The plane in this specification does not mean a complete plane, but includes a substantial plane. The substantial plane may also include small bumps and depressions.

Claims

1. A wiring substrate, comprising: a core substrate having a glass substrate, a through hole penetrating the substrate, and a through-hole conductor formed in the through hole; a resin insulating layer formed on the core substrate, having a first surface, a second surface opposite to the first surface, and an opening for a via conductor extending from the first surface to the second surface; a first conductor layer formed on the first surface of the resin insulating layer; as well as a via conductor formed in the opening and electrically connected to the through-hole conductor, in, The first conductor layer and the via conductor are formed of a seed layer and a plating layer formed on the seed layer, wherein the seed layer is formed by sputtering. The resin insulating layer is formed of resin and inorganic particles. The inorganic particles include first inorganic particles partially buried in the resin and second inorganic particles buried in the resin, The first inorganic particle is formed of a first portion protruding from the resin and a second portion buried in the resin, The first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface.

2. The wiring substrate according to claim 1, wherein: A ratio of the volume of the first portion to the volume of the first inorganic particles is greater than 0 and is equal to or less than 0.

4.

3. The wiring substrate according to claim 1, wherein The inorganic particles are glass particles.

4. The wiring substrate according to claim 1, wherein: The inorganic particles further include third inorganic particles forming the inner wall surface of the opening, The inner wall surface is formed by the third inorganic particles and the resin, The third inorganic particle has a flat portion, The flat portion forms the inner wall surface.

5. The wiring substrate according to claim 4, wherein: The flat portion and a surface of the resin forming the inner wall surface form a substantially common surface.

6. The wiring substrate according to claim 4, wherein: The second inorganic particles are in the shape of spheres, The shape of the third inorganic particle is obtained by cutting the second inorganic particle along a plane.

7. The wiring substrate according to claim 4, wherein: In the process of forming the opening, the inorganic particles are formed to have a protruding portion protruding from the resin forming the inner wall surface of the opening, and the third inorganic particles are formed by removing the protruding portion of the inorganic particles.

8. The wiring substrate according to claim 4, wherein: In the process of forming the opening, the inorganic particles having the protruding portion are formed from the second inorganic particles, The inner wall surface of the opening includes an exposed surface of the third inorganic particles formed by removing the protruding portion.

9. The wiring substrate according to claim 1, wherein: The inorganic particles contain oxygen element.

10. The wiring substrate according to claim 1, wherein The seed layer has a first layer and a second layer formed on the first layer, The first layer is composed of an alloy containing copper and aluminum.

11. The wiring substrate according to claim 10, wherein: The alloy also contains silicon.

12. The wiring substrate according to claim 1, wherein The seed layer covering the inner wall surface of the opening has a substantially smooth first film and a substantially smooth second film, The first film is electrically connected to the second film, A portion of the first film is formed on the second film.

13. The wiring substrate according to claim 12, wherein: The front end of the first film is formed on the rear end of the second film.

14. The wiring substrate according to claim 12, wherein: The first film and the second film are formed simultaneously.

15. The wiring substrate according to claim 12, wherein: The seed layer covering the inner wall surface has a substantially step-like cross-section.

Images