Sputtering process of thin-film resistor with PN junction structure

Abstract

The invention provides a thin-film resistor sputtering process with a PN junction structure, which comprises the following steps: (1) a Cap layer and an etching layer are sequentially arranged on a substrate, and the etching layer comprises a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer which are sequentially stacked from bottom to top; (2) a P-contact layer is formed through evaporation; (3) etching to form a first upper convex island and a second upper convex island; (4) etching to form a first lower island base and a second lower island base; (5) performing evaporation to form an N-contact layer; (6) etching to form a sputtering cavity; and (7) thin film resistance sputtering. According to the invention, the problem that the edge of the thin-film resistor with a PN junction structure tilts during sputtering is effectively solved, the appearance yield is improved, and the failure of a device caused by the fact that subsequent lead metal is connected with the salient point position is avoided; in addition, the process can utilize the existing structure, no additional photomask is added, and the cost is not increased.

Description

Technical Field

[0001] The invention relates to the technical field of thin film resistor sputtering technology, and in particular to a thin film resistor sputtering technology with a PN junction structure. Background Art

[0002] Existing thin film resistor sputtering process technology, such as Figure 1 Specifically, photoresist is used → photoresist coating → alignment → IR inversion → full exposure → development to form a positive trapezoidal morphology → thin film resistor sputtering; when the thin film resistor is sputtered, the bottom corner of this morphology will be connected to the bottom sputtered metal, so when the metal is lifted off, the metal at the bottom edge will be torn up, causing the edge of the sputtered metal to warp, affecting the appearance yield. In addition to the above problems, the sputtering process of thin film resistors with PN junction structure also has the problems of complex process and low production efficiency. Summary of the invention

[0003] In view of the above problems, the present invention proposes a sputtering process for a thin film resistor with a PN junction structure.

[0004] The technical solution of the present invention is achieved in this way:

[0005] A sputtering process for a thin film resistor with a PN junction structure comprises the following steps:

[0006] (1) a Cap layer and an etching layer are sequentially provided on a substrate, wherein the etching layer comprises a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer stacked sequentially from bottom to top;

[0007] (2) coating the first photoresist on the second GaAs layer, exposing and developing the first photoresist in the P-pole region of the PN junction to expose the second GaAs layer and form a P-pole window of the PN junction, then performing a first metal evaporation to form a P-contact layer on the second GaAs layer at the bottom of the P-pole window, wherein the thickness of the P-contact layer is less than that of the first photoresist, removing excess metal from the first metal evaporation on the first photoresist, and then removing the first photoresist;

[0008] (3) coating the P-contact layer of the second GaAs layer and its surroundings and the thin film resistor process area with a second photoresist, etching the second GaAs layer and the second InGaP layer outside the second photoresist area in turn, and then removing the second photoresist, so that the second GaAs layer and the second InGaP layer remaining at the bottom of the P-contact layer form a first upper convex island, and the second GaAs layer and the second InGaP layer remaining in the thin film resistor process area form a second upper convex island;

[0009] (4) coating the first upper convex island and the second upper convex island and their surrounding areas with a third photoresist, etching the first GaAs layer and the first InGaP layer outside the third photoresist in turn, and then removing the third photoresist, so that the first GaAs layer and the first InGaP layer at the bottom of the first upper convex island form a first lower island seat, and the first GaAs layer and the first InGaP layer at the bottom of the second upper convex island form a second lower island seat, and the width of the first lower island seat is greater than that of the first upper convex island;

[0010] (5) coating a fourth photoresist on the Cap layer, the fourth photoresist covering all components on the Cap layer, exposing and developing the fourth photoresist to form an N-pole window connected to the PN junction on the upper surface of the first lower island, and then performing a second metal evaporation to form an N-contact layer on the Cap layer at the bottom of the N-pole window, the thickness of the N-contact layer being less than that of the fourth photoresist, removing excess metal from the second metal evaporation on the fourth photoresist, and then removing the fourth photoresist;

[0011] (6) coating a fifth photoresist on the Cap layer, the fifth photoresist covering all components on the Cap layer, exposing and developing the fifth photoresist, forming a sputtering window on the fifth photoresist that leads to the upper surface of the second upper convex island, etching the second convex island and the second lower island seat through the sputtering window, etching away all the second convex island and the second lower island seat to form a sputtering cavity;

[0012] (7) performing sputtering of a thin film resistor to form a thin film resistor layer at the bottom of the sputtering cavity, wherein the thickness of the thin film resistor layer is less than the thickness of the sputtering cavity, removing the sputtering residue on the fifth photoresist, and finally removing the fifth photoresist.

[0013] Preferably, the P-pole window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom, the N-pole window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom, and the sputtering window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom.

[0014] Preferably, the width of the second lower island seat is equal to or greater than that of the second upper convex island.

[0015] Preferably, the width of the sputtering window is smaller than that of the second upper convex island.

[0016] Preferably, the first photoresist is positive photoresist or negative photoresist, the second photoresist is positive photoresist or negative photoresist, the third photoresist is positive photoresist or negative photoresist, the fourth photoresist is positive photoresist or negative photoresist, and the fifth photoresist is positive photoresist or negative photoresist.

[0017] Preferably, the substrate is a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate.

[0018] Preferably, the thin film resistor is made of TaN.

[0019] The beneficial effects of the present invention are as follows: the process of the present invention effectively solves the problem of edge warping during sputtering of a thin-film resistor with a PN junction structure, thereby improving the appearance yield rate and preventing subsequent lead metal from passing through the bump position and causing device failure; and the process of the present invention can utilize the existing structure, without the need for an additional photomask, and without increasing production costs; after vapor deposition, when removing excess vapor-deposited material and photoresist, the P-contact layer and the N-contact layer of the PN junction will not produce the problem of edge warping, thereby improving the appearance yield rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 The figure is a process diagram of the existing metal sputtering process;

[0022] Figure 2 is a structural diagram of step (1) of the present invention;

[0023] Figure 3 is a process flow chart of step (2) of the present invention;

[0024] Figure 4 is a process flow chart of step (3) of the present invention;

[0025] Figure 5 is a process flow chart of step (4) of the present invention;

[0026] Figure 6 is a process flow chart of step (5) of the present invention;

[0027] Figure 7 is a process flow chart of step (6) of the present invention;

[0028] Figure 8 This is a process flow chart of step (7) of the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Explanation of English terms involved in the article: P-contact is also called P-type contact layer or P electrode; N-contact is also called N-type contact layer or N electrode.

[0031] Reference Figure 2-8 , a sputtering process for a thin film resistor with a PN junction structure, comprising the following steps:

[0032] (1) a Cap layer and an etching layer are sequentially provided on a substrate, wherein the etching layer comprises a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer stacked sequentially from bottom to top;

[0033] (2) coating the first photoresist on the second GaAs layer, exposing and developing the first photoresist in the P-pole region of the PN junction to expose the second GaAs layer and form a P-pole window of the PN junction, then performing a first metal evaporation to form a P-contact layer on the second GaAs layer at the bottom of the P-pole window, wherein the thickness of the P-contact layer is less than that of the first photoresist, removing excess metal from the first metal evaporation on the first photoresist, and then removing the first photoresist;

[0034] (3) coating the P-contact layer of the second GaAs layer and its surroundings and the thin film resistor process area with a second photoresist, etching the second GaAs layer and the second InGaP layer outside the second photoresist area in turn, and then removing the second photoresist, so that the second GaAs layer and the second InGaP layer remaining at the bottom of the P-contact layer form a first upper convex island, and the second GaAs layer and the second InGaP layer remaining in the thin film resistor process area form a second upper convex island;

[0035] (4) coating the first upper convex island and the second upper convex island and their surrounding areas with a third photoresist, etching the first GaAs layer and the first InGaP layer outside the third photoresist in turn, and then removing the third photoresist, so that the first GaAs layer and the first InGaP layer at the bottom of the first upper convex island form a first lower island seat, and the first GaAs layer and the first InGaP layer at the bottom of the second upper convex island form a second lower island seat, and the width of the first lower island seat is greater than that of the first upper convex island;

[0036] (5) coating a fourth photoresist on the Cap layer, the fourth photoresist covering all components on the Cap layer, exposing and developing the fourth photoresist to form an N-pole window connected to the PN junction on the upper surface of the first lower island, and then performing a second metal evaporation to form an N-contact layer on the Cap layer at the bottom of the N-pole window, the thickness of the N-contact layer being less than that of the fourth photoresist, removing excess metal from the second metal evaporation on the fourth photoresist, and then removing the fourth photoresist;

[0037] (6) coating a fifth photoresist on the Cap layer, the fifth photoresist covering all components on the Cap layer, exposing and developing the fifth photoresist, forming a sputtering window on the fifth photoresist that leads to the upper surface of the second upper convex island, etching the second convex island and the second lower island seat through the sputtering window, etching away all the second convex island and the second lower island seat to form a sputtering cavity;

[0038] (7) performing sputtering of a thin film resistor to form a thin film resistor layer at the bottom of the sputtering cavity, wherein the thickness of the thin film resistor layer is less than the thickness of the sputtering cavity, removing the sputtering residue on the fifth photoresist, and finally removing the fifth photoresist.

[0039] As a preferred embodiment, the P-pole window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom, the N-pole window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom, and the sputtering window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom.

[0040] As a preferred implementation manner, the width of the second lower island seat is equal to or greater than that of the second upper convex island.

[0041] As a preferred implementation manner, the width of the sputtering window is smaller than that of the second upper convex island.

[0042] As a preferred embodiment, the first photoresist is positive photoresist or negative photoresist, the second photoresist is positive photoresist or negative photoresist, the third photoresist is positive photoresist or negative photoresist, the fourth photoresist is positive photoresist or negative photoresist, and the fifth photoresist is positive photoresist or negative photoresist.

[0043] Wherein, the substrate is a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate.

[0044] The thin film resistor is made of TaN. The P-contact layer and the N-contact layer are made of materials known in the prior art, and the evaporated materials are also known in the prior art, so they will not be described in detail.

[0045] The process of the present invention effectively solves the problem of edge warping during sputtering of a thin film resistor with a PN junction structure, improves the appearance yield, and does not cause subsequent lead metal to pass through the bump position, which is likely to cause device failure; and the process of the present invention can use the existing structure, without additional photomasks, and does not increase production costs; after evaporation, when the P-contact layer and the N-contact layer of the PN junction are removed from the excess evaporation material and photoresist, the P-contact layer and the N-contact layer will not have the problem of edge warping, thereby improving the appearance yield.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A sputtering process for a thin film resistor with a PN junction structure, characterized in that: The following steps are involved: (1) a Cap layer and an etching layer are sequentially provided on a substrate, wherein the etching layer comprises a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer stacked sequentially from bottom to top; (2) coating the first photoresist on the second GaAs layer, exposing and developing the first photoresist in the P-pole region of the PN junction to expose the second GaAs layer and form a P-pole window of the PN junction, then performing a first metal evaporation to form a P-contact layer on the second GaAs layer at the bottom of the P-pole window, wherein the thickness of the P-contact layer is less than that of the first photoresist, removing excess metal from the first metal evaporation on the first photoresist, and then removing the first photoresist; (3) coating the P-contact layer of the second GaAs layer and its surroundings and the thin film resistor process area with a second photoresist, etching the second GaAs layer and the second InGaP layer outside the second photoresist area in turn, and then removing the second photoresist, so that the second GaAs layer and the second InGaP layer remaining at the bottom of the P-contact layer form a first upper convex island, and the second GaAs layer and the second InGaP layer remaining in the thin film resistor process area form a second upper convex island; (4) coating the first upper convex island and the second upper convex island and their surrounding areas with a third photoresist, etching the first GaAs layer and the first InGaP layer outside the third photoresist in turn, and then removing the third photoresist, so that the first GaAs layer and the first InGaP layer at the bottom of the first upper convex island form a first lower island seat, and the first GaAs layer and the first InGaP layer at the bottom of the second upper convex island form a second lower island seat, and the width of the first lower island seat is greater than that of the first upper convex island; (5) coating a fourth photoresist on the Cap layer, the fourth photoresist covering all components on the Cap layer, exposing and developing the fourth photoresist to form an N-pole window connected to the PN junction on the upper surface of the first lower island, and then performing a second metal evaporation to form an N-contact layer on the Cap layer at the bottom of the N-pole window, the thickness of the N-contact layer being less than that of the fourth photoresist, removing excess metal from the second metal evaporation on the fourth photoresist, and then removing the fourth photoresist; (6) coating a fifth photoresist on the Cap layer, the fifth photoresist covering all components on the Cap layer, exposing and developing the fifth photoresist, forming a sputtering window on the fifth photoresist that leads to the upper surface of the second upper convex island, etching the second convex island and the second lower island seat through the sputtering window, etching away all the second convex island and the second lower island seat to form a sputtering cavity; (7) performing sputtering of a thin film resistor to form a thin film resistor layer at the bottom of the sputtering cavity, wherein the thickness of the thin film resistor layer is less than the thickness of the sputtering cavity, removing the sputtering residue on the fifth photoresist, and finally removing the fifth photoresist.

2. The sputtering process for a thin film resistor with a PN junction structure as claimed in claim 1, characterized in that: The P-pole window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom, the N-pole window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom, and the sputtering window is a rectangular window or a trapezoidal window that is small at the top and large at the bottom.

3. The sputtering process for a thin film resistor with a PN junction structure as claimed in claim 1, characterized in that: The width of the second lower island seat is equal to or greater than that of the second upper convex island.

4. The sputtering process for a thin film resistor with a PN junction structure as claimed in claim 1, characterized in that: The sputtering window has a width smaller than that of the second upper convex island.

5. The sputtering process for a thin film resistor with a PN junction structure as claimed in claim 1, characterized in that: The first photoresist is a positive photoresist or a negative photoresist, the second photoresist is a positive photoresist or a negative photoresist, the third photoresist is a positive photoresist or a negative photoresist, the fourth photoresist is a positive photoresist or a negative photoresist, and the fifth photoresist is a positive photoresist or a negative photoresist.

6. The sputtering process for a thin film resistor with a PN junction structure as claimed in claim 1, characterized in that: The substrate is a single crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate or a silicon carbide substrate.

7. The sputtering process for a thin film resistor with a PN junction structure as claimed in claim 1, characterized in that: The material of the thin film resistor is TaN.

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