Preparation method of chip packaging structure and chip packaging structure

Abstract

The invention relates to the technical field of laminated packaging, and discloses a chip packaging structure and a preparation method thereof, and the method comprises the steps: providing a first substrate and a second substrate; mounting a first passive component and a first conductive structure on the first surface of the first substrate, wherein the first conductive structure comprises a plurality of first conductive columns and a first connecting frame; forming a first plastic package layer on the first surface; grinding the first plastic package layer to enable the first plastic package layer to expose the surface, away from the first surface, of the first conductive column; mounting a second passive component and a second conductive structure on the second surface of the second substrate; grinding the second plastic package layer to enable the second plastic package layer to expose the surface, away from the second surface, of the second conductive column; and the first conductive column and the second conductive column are subjected to fitting treatment, so that the first conductive column and the second conductive column are electrically connected. According to the chip packaging structure, the size of the chip packaging structure can be reduced, and the problem of toppling caused by the fact that the conductive columns are too high in the mounting process can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of stacked packaging, and in particular to a preparation method of a chip packaging structure and a chip packaging structure. Background Art

[0002] Package on Package (POP) technology is an advanced packaging technology that stacks two or more chip packages together. It can achieve higher integration within a limited circuit board space and is used in miniaturized electronic devices such as smartphones and tablets.

[0003] POP packaging mostly uses through mold via (TMV) + solder ball to achieve electrical connection between different packages. Specifically, during the packaging process, vertical conductive vias are made in the plastic packaging material. The conductive vias can be used to achieve electrical connection between different layers inside the package. Then, solder balls are set on the pads of the lower package to connect the upper package with the lower package to build a stacked package structure.

[0004] However, as the number and size of devices in the package increase, the solder balls themselves are limited in size. In fine pitch and thicker package products, the above packaging method is difficult to meet the requirements of good spacing and thickness. Summary of the invention

[0005] In view of this, the present invention provides a method for preparing a chip packaging structure and a chip packaging structure to solve the problem that the chip packaging structure has a large size.

[0006] In a first aspect, the present invention provides a method for preparing a chip packaging structure, the method comprising: providing a first substrate and a second substrate; mounting a first passive component and a first conductive structure on a first surface of the first substrate, wherein the first conductive structure comprises a plurality of first conductive pillars and a first connecting frame, the first connecting frame connects the plurality of first conductive pillars spaced apart, and a surface of the first conductive pillar on a side away from the first connecting frame is attached to the first surface; forming a first plastic encapsulation layer on the first surface, wherein the first plastic encapsulation layer encapsulates the first passive component and the first conductive structure; grinding the first plastic encapsulation layer so that the first plastic encapsulation layer exposes the first conductive pillar away from the first surface surface; mounting a second passive component and a second conductive structure on the second surface of the second substrate, wherein the second conductive structure includes a plurality of second conductive pillars and a second connecting frame, the second connecting frame connects the plurality of second conductive pillars spaced apart, and a surface of the second conductive pillar on a side away from the second connecting frame is bonded to the second surface; forming a second plastic encapsulation layer on the second surface, wherein the second plastic encapsulation layer encapsulates the second passive component and the second conductive structure; grinding the second plastic encapsulation layer so that the second plastic encapsulation layer exposes a surface of the second conductive pillar away from the second surface; bonding the first conductive pillar and the second conductive pillar so that the first conductive pillar and the second conductive pillar are electrically connected.

[0007] The preparation method of the chip packaging structure provided in this embodiment is that after the first passive component and the first conductive structure are mounted on the first surface of the first substrate, a first plastic sealing layer is formed on the first surface, and the first plastic sealing layer is ground so that the first plastic sealing layer exposes the first conductive column to form a first package. At the same time, the second passive component and the second conductive structure are mounted on the second surface of the second substrate, and then a second plastic sealing layer is formed on the second surface, and the second plastic sealing layer is ground so that the second plastic sealing layer exposes the second conductive column to form a second package. Afterwards, the first package and the second package are electrically connected by bonding the first conductive column and the second conductive column. The present invention exposes the corresponding pads by adopting the surface mounting and thinning method of the conductive structure to realize the electrical connection of each package, which can reduce the size of the chip packaging structure, and can also improve the dumping problem caused by the excessive height of the conductive column during the mounting process. In addition, the present invention has high practicality and simple process, and can reduce the development cost on the basis of existing equipment.

[0008] In an optional implementation, a ratio of a width to a height of the first conductive pillar is greater than or equal to 1:2, and a ratio of a width to a height of the second conductive pillar is greater than or equal to 1:2.

[0009] In this embodiment, after the multiple conductive pillars are merged into a whole through the connecting frame, the aspect ratio of the conductive pillar can be greater than 1:2, which is equivalent to reducing the width of the conductive pillar, and can increase the number of input / output (IO) pins under the same area. It can also add corresponding IO structures between components that originally could not be embedded in the conductive pillars, further increase the number of IO interfaces of the upper and lower chips, and improve chip performance.

[0010] In an optional embodiment, the first conductive column and the second conductive column are bonded together, including: coating solder paste on the second conductive column; arranging the first conductive column and the second conductive column relative to each other, and bonding the first conductive column and the second conductive column by a hot pressing process or a reflow process.

[0011] In an optional implementation, after the first conductive pillar and the second conductive pillar are bonded together, the distance between the first conductive pillar and the second conductive pillar is less than or equal to 0.05 mm.

[0012] In an optional implementation, grinding the first plastic sealing layer includes: grinding the first plastic sealing layer by a chemical mechanical polishing process.

[0013] In this embodiment, the first plastic sealing layer is ground by a chemical mechanical polishing process. The chemical corrosion can soften the surface material of the workpiece, making it easier for abrasive particles to remove microscopic protrusions, thereby reducing the occurrence of surface defects such as scratches and pits, improving surface quality, and also improving polishing efficiency.

[0014] In an optional implementation, after the first plastic encapsulation layer is ground, the height of the first conductive column is less than or equal to 0.6 mm, and after the second plastic encapsulation layer is ground, the height of the second conductive column is less than or equal to 0.6 mm.

[0015] In an optional embodiment, before mounting the first passive component and the first conductive structure on the first surface of the first substrate, the method further includes: mounting the first chip and the third passive component on the third surface of the first substrate, wherein the third surface and the first surface are two surfaces of the first substrate arranged opposite to each other; forming a third plastic encapsulation layer on the third surface, wherein the third plastic encapsulation layer encapsulates the first chip and the third passive component.

[0016] In an optional implementation, before forming the second plastic encapsulation layer on the second surface, the method further includes: mounting a second chip on the second surface, wherein the second plastic encapsulation layer further encapsulates the second chip.

[0017] In an optional implementation, after laminating the first conductive pillar and the second conductive pillar, the method further includes: performing ball planting on the fourth surface of the second substrate, wherein the fourth surface and the second surface are two surfaces of the second substrate arranged opposite to each other.

[0018] In a second aspect, the present invention provides a chip packaging structure, which is prepared by the method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 is a schematic flow chart of a method for preparing a chip packaging structure according to an embodiment of the present invention;

[0021] Figure 2 is a schematic structural diagram of a first conductive structure according to an embodiment of the present invention;

[0022] Figures 3 to 13 A schematic diagram of the structure of a chip packaging structure during a method for preparing the chip packaging structure according to an embodiment of the present invention;

[0023] Fig.14 is a schematic diagram of a chip packaging structure according to an embodiment of the present invention.

[0024] Figure numerals: 10, first substrate; 20, first conductive structure; 21, first conductive column; 22, first connecting frame; 30, third passive component; 40, first chip; 41, lead; 50, third plastic layer; 60, first passive component; 70, first plastic layer; 80, second substrate; 90, second passive component; 100, second conductive structure; 110, second chip; 120, second plastic layer; 130, solder ball. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0026] With the continuous development of semiconductor manufacturing technology and three-dimensional packaging technology, electronic devices and electronic products have higher and higher requirements for multifunctionality and miniaturization. Driven by this miniaturization trend, the chip packaging size is required to be continuously reduced. According to the international semiconductor technology roadmap, three-dimensional stacking packaging technology can better achieve the miniaturization of packaging.

[0027] Three-dimensional stacking packaging has the characteristics of smaller package volume, larger package space, shorter lead distance and shorter product development cycle. It is mainly used in electronic products such as mobile phones, laptops or digital cameras. Three-dimensional stacking packaging is mainly divided into three forms: carrier stacking, bare chip stacking and wafer stacking. 3D bare chip stacking packaging technology mainly includes multi-chip packaging (Multi-Chip Packaging, MCP), built-in packaging technology (Package-in-Package, PiP) and PoP packaging.

[0028] POP packaging is a way to achieve 3D packaging by stacking multiple layers of packaging, that is, POP packaging is to stack another matching package on top of a package at the bottom. Each package of POP packaging is relatively independent, and the bottom and top package devices can be tested separately, thus ensuring good finished product performance.

[0029] However, currently, POP packaging mostly uses TMV and solder balls to achieve electrical connection between packages. As the number and size of devices in the package increase, due to the size limitation of the solder balls themselves, it is difficult to meet the requirements of good spacing and thickness in fine pitch and thicker package products. That is, due to the limitation of the size of the solder balls, the size of the final chip package structure may be large, which is difficult to meet the packaging requirements.

[0030] In view of this, the present invention provides a method for preparing a chip packaging structure. By adopting a copper pillar array frame surface mounting and then thinning to expose the corresponding pads (Pad), electrical connection of each package body is achieved, which can reduce the size (thickness) of the chip packaging structure and improve the tipping problem caused by the excessive height of the conductive pillar during the mounting process.

[0031] The preparation method of the chip packaging structure provided by the present invention is described below in conjunction with the accompanying drawings.

[0032] In this embodiment, a method for preparing a chip packaging structure is provided. Figure 1 FIG. 1 is a flow chart of a method for preparing a chip packaging structure according to an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0033] Step S101, providing a first substrate and a second substrate.

[0034] Specifically, both the first substrate and the second substrate may be a multilayer structure composed of insulating materials (such as resin, glass fiber, etc.) and conductive materials (such as copper foil, etc.), which may provide physical support and electrical connection for chips and other electronic components.

[0035] Exemplarily, both the first substrate and the second substrate may be a printed circuit board (PCB), a metal lead frame, a silicon substrate, a resin substrate, a ceramic substrate or a glass substrate, etc. The first substrate and the second substrate may be selected by the designer according to packaging requirements.

[0036] Step S102 : mounting a first passive component and a first conductive structure on a first surface of a first substrate.

[0037] Among them, Figure 2 As shown, the first conductive structure 20 includes a plurality of first conductive pillars 21 and a first connecting frame 22. The first connecting frame 22 connects the plurality of first conductive pillars 21 spaced apart from each other, and a surface of the first conductive pillar 21 away from the first connecting frame 22 is attached to the first surface. Exemplarily, the first conductive pillar may be a copper pillar.

[0038] Specifically, the heights of the plurality of first conductive pillars 21 are the same, the widths of the plurality of first conductive pillars 21 may be determined based on the connection positions, and the widths of the plurality of first conductive pillars 21 may be the same or different.

[0039] The present invention does not specifically limit the arrangement of the plurality of first conductive pillars. For example, the plurality of first conductive pillars may be arranged as follows: Figure 2 The first conductive pillars are arranged equidistantly, that is, the intervals between any two adjacent first conductive pillars are equal. The first conductive pillars may also be arranged unequally, that is, the intervals between any two adjacent first conductive pillars are unequal. The present invention does not limit the number of first conductive pillars, as long as it is greater than 3. For example, the number of first conductive pillars may be 6, 10, or 20.

[0040] Specifically, the first passive component refers to a passive component arranged on the first surface of the first substrate. The passive component refers to an electronic component that does not have active functions such as amplification or control in the circuit, and only regulates, filters and couples signals such as current, voltage or frequency.

[0041] Exemplarily, the first passive component may be a resistor, a capacitor, an inductor or a transformer, etc. The resistor has an obstructive effect on the current and is used to control the current size and voltage division in the circuit. The capacitor can store charge and has the characteristics of passing AC and blocking DC, and is used for filtering, coupling and energy storage, etc. The inductor can store magnetic field energy and has the characteristics of passing DC and blocking AC, and is used for filtering, oscillation and delay, etc. The transformer can realize voltage conversion and power transmission through the principle of electromagnetic induction.

[0042] The first surface may be one of the surfaces of the first substrate. For example, the upper surface of the first substrate may be the first surface, or the lower surface of the first substrate may be the first surface.

[0043] Exemplarily, the process of mounting the first passive component and the first conductive structure on the first surface of the first substrate may specifically be: according to the layout of the passive components and the first conductive structure on the first substrate and the size of the pads, a corresponding steel mesh is made; the steel mesh is placed on the first substrate, and the solder paste is evenly printed on the pads of the first substrate by a scraper; at least one passive component and the first conductive structure are placed on the corresponding pads by a placement machine, and a preset pressure is applied to make the at least one passive component and the first conductive structure in close contact with the pads on the first surface; welding or curing treatment is performed to fix the at least one passive component and the first conductive structure on the first surface and electrically connected to the first substrate.

[0044] Specifically, in this embodiment, the first conductive column is combined into a whole through the first connecting frame, and the first conductive column structure is stabilized by the first connecting frame. During the surface mounting (Surface Mount Technology, SMT) of the conductive column, the tilting or tipping of the single conductive column caused by the unstable solder paste shape can be improved, and the product failure caused by the displacement of the top pad position can be avoided.

[0045] Step S103, forming a first plastic packaging layer on the first surface.

[0046] The first plastic encapsulation layer encapsulates the first passive component and the first conductive structure.

[0047] Specifically, the first plastic sealing layer can be formed on the first surface by injection molding, transfer molding, potting, etc.

[0048] In the injection molding method, the plastic encapsulation material is heated and melted, and then injected into the mold cavity through the screw of the injection molding machine. The injection speed, pressure and temperature are determined by the designer to ensure that the plastic encapsulation material can fully fill the mold cavity and avoid defects such as bubbles and lack of material. In the transfer molding method, the plastic encapsulation material is pre-heated and melted, and then placed in the feeding chamber of the transfer molding machine. The plastic encapsulation material is pushed into the mold cavity by the plunger. Under the action of pressure and temperature, the plastic encapsulation material fills the mold cavity and solidifies. In the potting method, the plastic encapsulation material is slowly poured into the mold cavity in liquid form, and the plastic encapsulation material flows and fills naturally, and then heated or cured to solidify the plastic encapsulation material.

[0049] Exemplarily, the molding material forming the first molding layer may be epoxy resin, silicone resin, polyimide or phenolic resin.

[0050] Epoxy resin has good insulation, heat resistance, mechanical strength and chemical stability, and can be cured at room temperature or under heating conditions to form a hard plastic layer. Silicone resin has excellent heat resistance, cold resistance, weather resistance and electrical insulation, and can be used for a long time at high temperature without aging and embrittlement. Silicone resin also has good moisture resistance and can protect electronic components from moisture. Polyimide has good insulation properties and can withstand high voltage and high frequency electrical signals. Phenolic resin has good heat resistance, mechanical strength and chemical stability, and can be cured at a lower temperature to form a hard plastic layer.

[0051] Step S104 , grinding the first plastic encapsulation layer to expose the surface of the first conductive pillar away from the first surface.

[0052] Specifically, the first plastic encapsulation layer can be ground by mechanical processing, for example, the first plastic encapsulation layer can be ground by a grinder. During the grinding process of the first plastic encapsulation layer, the first connection frame can be removed, so that the side of the first plastic encapsulation layer away from the first surface exposes the surface of the first conductive column away from the first surface, so as to obtain the first package body.

[0053] Step S105 , mounting a second passive component and a second conductive structure on a second surface of the second substrate.

[0054] The second conductive structure includes a plurality of second conductive pillars and a second connecting frame, the second connecting frame connects the plurality of second conductive pillars arranged at intervals, and a side surface of the second conductive pillar away from the second connecting frame is in contact with the second surface.

[0055] Specifically, the second conductive structure is similar to the first conductive structure, except that the second conductive structure is a conductive structure disposed on the second surface of the second substrate, and the first conductive structure is a conductive structure disposed on the first surface of the first substrate. The second conductive structure and the first conductive structure may be completely the same or different, for example, the number of the second conductive columns is different from the number of the first conductive columns, or the arrangement of the second conductive columns and the first conductive columns is different.

[0056] The second passive component refers to a passive component disposed on the second surface of the second substrate. For example, the second passive component may also be a resistor, a capacitor, an inductor or a transformer, etc. The second surface refers to one of the surfaces of the second substrate. For example, the second surface may be the upper surface of the second substrate or the lower surface of the second substrate.

[0057] The method of mounting the second passive component and the second conductive structure on the second surface of the second substrate may be the same as the method mentioned in the above step S102, which will not be described here.

[0058] Step S106, forming a second plastic packaging layer on the second surface.

[0059] The second plastic packaging layer encapsulates the second passive component and the second conductive structure.

[0060] Specifically, the first plastic sealing layer can be formed on the first surface by injection molding, transfer molding, potting, etc.

[0061] Exemplarily, the molding material forming the first molding layer may be epoxy resin, silicone resin, polyimide or phenolic resin.

[0062] Step S107 , grinding the second plastic encapsulation layer to expose the surface of the second conductive pillar away from the second surface.

[0063] Specifically, the second plastic encapsulation layer can be ground by mechanical processing, for example, the second plastic encapsulation layer can be ground by a grinder. During the grinding process of the second plastic encapsulation layer, the second connection frame can be removed, so that the side of the second plastic encapsulation layer away from the second surface exposes the surface of the second conductive column away from the second surface, so as to obtain the second package body.

[0064] Exemplarily, the present invention does not limit the execution order of step S102 and step S105, that is, steps S105 to S107 may be executed after steps S102 to S104 are executed; steps S102 to S104 may be executed after steps S105 to S107 are executed; and step S105 may be executed while step S102 is executed.

[0065] Step S108 , performing a bonding process on the first conductive pillar and the second conductive pillar to electrically connect the first conductive pillar and the second conductive pillar.

[0066] Specifically, after obtaining the first package body and the second package body, the first conductive column and the second conductive column can be arranged relative to each other, and then the first conductive column and the second conductive column can be fixedly connected by welding or conductive adhesive bonding, and the first conductive column and the second conductive column are electrically connected, thereby electrically connecting the first package body and the second package body.

[0067] The preparation method of the chip packaging structure provided in this embodiment is that after the first passive component and the first conductive structure are mounted on the first surface of the first substrate, a first plastic sealing layer is formed on the first surface, and the first plastic sealing layer is ground so that the first plastic sealing layer exposes the first conductive column to form a first package. At the same time, the second passive component and the second conductive structure are mounted on the second surface of the second substrate, and then a second plastic sealing layer is formed on the second surface, and the second plastic sealing layer is ground so that the second plastic sealing layer exposes the second conductive column to form a second package. Afterwards, the first package and the second package are electrically connected by bonding the first conductive column and the second conductive column. The present invention exposes the corresponding pads by adopting the surface mounting and thinning method of the conductive structure to realize the electrical connection of each package, which can reduce the size of the chip packaging structure, and can also improve the dumping problem caused by the excessive height of the conductive column during the mounting process. In addition, the present invention has high practicality and simple process, and can reduce the development cost on the basis of existing equipment.

[0068] In some embodiments, the ratio of the width to the height of the first conductive pillar in the first conductive structure is greater than or equal to 1:2, and the ratio of the width to the height of the second conductive pillar in the second conductive structure is greater than or equal to 1:2. For example, the ratio of the width to the height of the first conductive pillar may be 1:2, 1:3, 1:6, 1:8, or 1:10, and the ratio of the width to the height of the second conductive pillar may be 1:2, 1:4, 1:5, 1:8, or 1:10, etc.

[0069] In this embodiment, after multiple conductive pillars are merged into a whole through a connecting frame, the aspect ratio of the conductive pillars can be greater than 1:2. Reducing the width of the conductive pillars can increase the number of input / output (IO) pins under the same area, and can also add corresponding IO structures between components that originally could not be embedded in the conductive pillars, thereby further increasing the number of IO interfaces of the upper and lower chips and improving chip performance.

[0070] Exemplarily, the steps of bonding the first conductive column and the second conductive column may specifically be: coating solder paste on the second conductive column; arranging the first conductive column and the second conductive column relative to each other, and bonding the first conductive column and the second conductive column by a hot pressing process or a reflow process.

[0071] In one example, after the first conductive pillar and the second conductive pillar are bonded together, the distance between the first conductive pillar and the second conductive pillar may be less than or equal to 0.05 mm.

[0072] The preparation method of the chip packaging structure provided by the present invention is further described below in conjunction with the accompanying drawings.

[0073] Specifically, Figure 3 As shown, firstly, the third passive component 30 is mounted on the third surface (such as the upper surface) of the first substrate 10, and then Figure 4 As shown, a first chip 40 is mounted on the third surface of the first substrate 10 , and the first chip 40 is connected to the first substrate 10 via leads 41 .

[0074] The third surface and the first surface are two surfaces of the first substrate 10 that are opposite to each other. If the third surface is the upper surface, the first surface is the lower surface.

[0075] Wire bonding is a process that connects the pads on the chip to the pads or pins on the package substrate with metal wires. Usually, very fine metal wires (such as gold wires, copper wires, etc.) are used to form reliable electrical and mechanical connections between the metal wires and the pads through hot pressing, ultrasound or thermosonication under certain pressure, temperature and time conditions. The electrical signals generated inside the chip are transmitted to the pins on the package substrate through the wires, and then communicate with the external circuit. At the same time, wire bonding also provides a certain mechanical support for the chip, enhancing the stability of the chip in the package.

[0076] Exemplarily, the first chip 40 may be a processor chip, a memory chip or a communication chip, etc. The third passive component refers to a passive component disposed on the third surface of the first substrate 10, and the third passive component may be a resistor, a capacitor, an inductor or a transformer, etc.

[0077] Afterwards, if Figure 5 As shown, a third plastic encapsulation layer 50 is formed on the third surface, and the third plastic encapsulation layer 50 encapsulates the first chip and the third passive component. Specifically, the third plastic encapsulation layer can be formed on the third surface by injection molding, transfer molding, potting, etc. Exemplarily, the plastic encapsulation material forming the third plastic encapsulation layer can be epoxy resin, silicone resin, polyimide or phenolic resin, etc.

[0078] In the formation Figure 5 After the structure shown, Figure 6 As shown, the first passive component 60 and the first conductive structure 20 are mounted on the first surface of the first substrate 10, and then, as shown in FIG. Figure 7As shown, a first plastic encapsulation layer 70 is formed on the first surface, and the first plastic encapsulation layer 70 encapsulates the first passive component 60 and the first conductive structure 20. After the first plastic encapsulation layer is formed, the first plastic encapsulation layer is ground to expose the surface of the first conductive column away from the first surface, and the first plastic encapsulation layer is formed as shown in FIG. Figure 8 The first package is shown.

[0079] In some optional implementations, the step of grinding the first plastic encapsulation layer may specifically include grinding the first plastic encapsulation layer by a chemical-mechanical polishing (CMP) process.

[0080] CMP is a surface flattening technology that combines chemical corrosion and mechanical grinding. During the chemical mechanical polishing process, the workpiece surface comes into contact with a chemical polishing liquid containing abrasives. At the same time, under a certain pressure and relative motion, the synergistic effect of chemical corrosion and mechanical grinding is used to remove the microscopic protrusions on the workpiece surface and achieve a highly flat surface.

[0081] In this embodiment, the first plastic sealing layer is ground by a chemical mechanical polishing process. The chemical corrosion can soften the surface material of the workpiece, making it easier for abrasive particles to remove microscopic protrusions, thereby reducing the occurrence of surface defects such as scratches and pits, improving surface quality, and also improving polishing efficiency.

[0082] At the same time, Fig. 9 As shown, the second passive component 90 and the second conductive structure 100 are mounted on the second surface (such as the upper surface) of the second substrate 80. In one example, a second chip 110 can also be mounted on the second surface of the second substrate 80.

[0083] Exemplarily, the second chip 110 may also be a processor chip, a memory chip, a communication chip, or the like.

[0084] Then, if Fig.10 As shown, a second plastic encapsulation layer 120 is formed on the second surface, and then the second plastic encapsulation layer 120 is ground to expose the surface of the second conductive column away from the second surface of the second plastic encapsulation layer 120, so as to obtain Fig.11 The second package body shown in FIG. illustratively, the second plastic packaging layer can be ground by chemical mechanical polishing.

[0085] After obtaining the first package and the second package, Fig.12 As shown, the first conductive pillar and the second conductive pillar are bonded to each other so that the first conductive pillar and the second conductive pillar are electrically connected, thereby electrically connecting the first package body and the second package body.

[0086] Afterwards, if Fig.13As shown, the fourth surface of the second substrate 80 is subjected to ball planting to obtain a chip packaging structure. The fourth surface and the second surface are two surfaces of the second substrate 80 that are opposite to each other. If the second surface is the upper surface of the second substrate 80, the fourth surface is the lower surface of the second substrate 80.

[0087] Exemplarily, the step of performing ball planting on the fourth surface of the second substrate 80 may specifically include: placing the solder ball 130 on the pad on the fourth surface by ball planting equipment; and fixing the solder ball 130 and the pad on the fourth surface by a reflow process.

[0088] In this embodiment, by performing ball implantation, an electrical connection channel can be established between the chip package and the external circuit using the solder balls as connection points.

[0089] In one example, if Fig.14 As shown, the thickness A of the third plastic sealing layer is less than or equal to 0.37 mm, the thickness B of the first substrate 10 is less than or equal to 0.2 mm, the thickness of the first plastic sealing layer that has not been ground is greater than or equal to 0.8 mm, the thickness C of the first plastic sealing layer after the grinding treatment is less than or equal to 0.6 mm, that is, the height of the first conductive column is less than or equal to 0.6 mm, the spacing D between the first conductive column and the second conductive column is less than or equal to 0.05 mm, the thickness of the second plastic sealing layer that has not been ground is greater than or equal to 0.8 mm, the thickness E of the second plastic sealing layer after the grinding treatment is less than or equal to 0.6 mm, that is, the height of the second conductive column is less than or equal to 0.6 mm, the thickness F of the second substrate is less than or equal to 0.26 mm, the solder ball support height G is less than or equal to the solder ball size (less than or equal to 0.6 mm) / support height (less than or equal to 0.5 mm), and the total thickness of the chip packaging structure finally prepared is less than or equal to 2.58 mm.

[0090] The present invention further provides a chip packaging structure, which is prepared by the chip packaging structure preparation method provided by any of the above embodiments. Fig.14 shown.

[0091] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0092] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0093] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0094] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0095] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0096] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the present invention.

Claims

1. A method for preparing a chip packaging structure, characterized in that: The method comprises: providing a first substrate and a second substrate; Mounting a first passive component and a first conductive structure on a first surface of the first substrate, wherein the first conductive structure comprises a plurality of first conductive pillars and a first connecting frame, the first connecting frame connects the plurality of first conductive pillars arranged at intervals, and a surface of a side of the first conductive pillar away from the first connecting frame is attached to the first surface; forming a first plastic encapsulation layer on the first surface, wherein the first plastic encapsulation layer encapsulates the first passive component and the first conductive structure; Grinding the first plastic encapsulation layer so that the first plastic encapsulation layer exposes a surface of the first conductive column away from the first surface; Mounting a second passive component and a second conductive structure on the second surface of the second substrate, wherein the second conductive structure includes a plurality of second conductive pillars and a second connecting frame, the second connecting frame connects the plurality of second conductive pillars arranged at intervals, and a surface of the second conductive pillar on one side away from the second connecting frame is attached to the second surface; forming a second plastic encapsulation layer on the second surface, wherein the second plastic encapsulation layer encapsulates the second passive component and the second conductive structure; Grinding the second plastic encapsulation layer so that the second plastic encapsulation layer exposes a surface of the second conductive column away from the second surface; The first conductive pillar and the second conductive pillar are bonded to each other so that the first conductive pillar and the second conductive pillar are electrically connected.

2. The method according to claim 1, characterized in that A ratio of a width to a height of the first conductive pillar is greater than or equal to 1:2, and a ratio of a width to a height of the second conductive pillar is greater than or equal to 1:

2.

3. The method according to claim 1, characterized in that The laminating process of the first conductive pillar and the second conductive pillar comprises: Applying solder paste on the second conductive column; The first conductive pillar and the second conductive pillar are arranged opposite to each other, and the first conductive pillar and the second conductive pillar are bonded together by a hot pressing welding process or a reflow welding process.

4. The method according to claim 3, characterized in that After the first conductive pillar and the second conductive pillar are bonded together, a distance between the first conductive pillar and the second conductive pillar is less than or equal to 0.05 mm.

5. The method according to claim 1, characterized in that The grinding process of the first plastic sealing layer includes: The first plastic packaging layer is ground by a chemical mechanical polishing process.

6. The method according to claim 5, characterized in that After the first plastic encapsulation layer is ground, the height of the first conductive pillar is less than or equal to 0.6 mm. After the second plastic encapsulation layer is ground, the height of the second conductive pillar is less than or equal to 0.6 mm.

7. The method according to any one of claims 1 to 6, characterized in that Before mounting the first passive component and the first conductive structure on the first surface of the first substrate, the method further includes: Mounting a first chip and a third passive component on a third surface of the first substrate, wherein the third surface and the first surface are two surfaces of the first substrate arranged opposite to each other; A third plastic encapsulation layer is formed on the third surface, wherein the third plastic encapsulation layer encapsulates the first chip and the third passive component.

8. The method according to any one of claims 1 to 6, characterized in that Before forming the second plastic encapsulation layer on the second surface, the method further includes: A second chip is mounted on the second surface, wherein the second plastic packaging layer also encapsulates the second chip.

9. The method according to any one of claims 1 to 6, characterized in that After the first conductive pillar and the second conductive pillar are bonded together, the method further includes: A ball planting process is performed on the fourth surface of the second substrate, wherein the fourth surface and the second surface are two surfaces of the second substrate that are opposite to each other.

10. A chip packaging structure, characterized in that: The chip packaging structure is prepared by the method according to any one of claims 1 to 9.

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