Successive approximation and event-driven hybrid level crossing ADC (Analog to Digital Converter) circuit

Abstract

According to the successive approximation and event-driven hybrid level crossing ADC circuit, a novel hybrid architecture of an LC ADC and an SAR ADC is adopted, level crossing detection of any input frequency can be achieved at the very low clock frequency, meanwhile, the SAR ADC has the very excellent low-energy-consumption performance at the low clock frequency, the power consumption of the whole system can be very low, and the system reliability is improved. Moreover, the output of the system is not affected by the precision of the LC ADC through the SAR ADC, and meanwhile, the signal regeneration processing is not needed, and the subsequent digital signal processing can be directly carried out on the output data. Meanwhile, a digital-analog hybrid design method is used, and a logic processing module in the system is realized by using a digital method, so that external logic devices such as an FPGA (Field Programmable Gate Array) are not needed, and the circuit integration level and the use convenience are improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a successive approximation and event-driven mixed level crossing ADC circuit. Background Art

[0002] In the Internet of Things (IoT), especially in portable mobile IoT applications, signal acquisition and communication often have the characteristics of long distance, low rate and dense terminal nodes. Low power consumption is one of the key requirements of such systems. Since ADC (analog-to-digital conversion) is an indispensable module in the IoT system, its main function is to convert analog signals into digital signals for subsequent processing. Therefore, low power consumption of ADC is an inevitable requirement for IoT applications. However, traditional ADCs all adopt the form of uniform sampling. For signals that are rich in frequency domain and sparse in time domain (such as communication signals of digital electronic detonators, collection of human physiological signals, etc.), because the frequency of the signal is usually low and sparse, continuous sampling and conversion during the silent period will inevitably cause a lot of power loss, so it will cause a lot of power consumption loss. Although the event-driven level crossing ADC (LC ADC) that detects level mutations can stop conversion during the silent period and quickly sample when the level mutation occurs, it can reduce system power consumption, but the traditional LC ADC is difficult to balance between the three key indicators of accuracy, speed and power consumption, and usually needs to be compromised, and cannot meet the requirements of high accuracy, high speed and low power consumption at the same time. To this end, the traditional LC ADC architecture still needs to be further improved. Summary of the invention

[0003] The present invention aims to solve the problem that the existing event-driven level-crossing ADC circuit is difficult to balance among the three key indicators of accuracy, speed and power consumption, and provides a successive approximation and event-driven hybrid level-crossing ADC circuit.

[0004] To solve the above problems, the present invention is achieved through the following technical solutions:

[0005] A successive approximation and event-driven hybrid level-crossing ADC circuit includes a level-crossing analog-to-digital conversion module, a system clock generation module, a successive approximation analog-to-digital conversion module, and a switch signal generation module. The level-crossing analog-to-digital conversion module is connected to an externally input power supply voltage Vss, an analog signal Vin, a reference voltage Vref, a reference voltage VH, and a reference voltage VL, a switch control signal a[0]-a[5] and b[0]-b[5] output by the switch signal generation module, and clock signals CLK_DAC, CLK_DACN, and CLK_COMP output by the system clock generation module. The level-crossing analog-to-digital conversion module outputs control signals S0 and S1. The system clock generation module is connected to an externally input power supply voltage Vss and a clock signal CP, and control signals S0 and S1 output by the level-crossing analog-to-digital conversion module. The system clock generation module outputs clock signals CLK_DAC, CLK_DACN, CLK_COMP, and a control signal FS. The successive approximation analog-to-digital conversion module is connected to the external input power supply voltage Vss and the analog signal Vin, as well as the control signal FS output by the system clock generation module. The successive approximation analog-to-digital conversion module outputs the digital signal D[10:0]. The switch signal generation module is connected to the upper six-bit signals D[5]~D

[10] in the digital signal D[10:0] output by the successive approximation analog-to-digital conversion module, and the clock signal CLK_DAC output by the system clock generation module. The switch signal generation module outputs switch control signals a[0]~a[5] and switch control signals b[0]~b[5].

[0006] The above-mentioned level cross analog-to-digital conversion module is composed of switches SW1-SW15, capacitors C0-C6, comparators COMP1 and COMP2, NAND gate NAND1, and event-driven logic unit EVENT LOGIC. One end of switch SW1 is connected to the external input analog signal Vin, and the other end of switch SW1 is connected to one end of capacitors C0-C5 and one end of switch SW2. The other end of capacitor C0 is connected to one end of switches SW4 and SW5. The other end of capacitor C1 is connected to one end of switches SW6 and SW7. The other end of capacitor C2 is connected to one end of switches SW8 and SW9. The other end of capacitor C3 is connected to one end of switches SW10 and SW11. The other end of capacitor C4 is connected to one end of switches SW12 and SW13. The other end of capacitor C5 is connected to one end of switches SW14 and SW15. The other end of switch SW2 is connected to one end of capacitor C6, one end of switch SW3, the inverting input end of comparator COMP1, and the non-inverting input end of comparator COMP2. The control ends of switches SW1 and SW3 are connected to the clock signal CLK_DAC output by the system clock generation module. The control end of switch SW2 is connected to the clock signal CLK_DACN output by the system clock generation module. The other ends of switches SW4, SW6, SW8, SW10, SW12, SW14 and SW3 are connected to the external input reference voltage Vref. The other ends of switches SW5, SW7, SW9, SW11, SW32 and SW15 and the other end of capacitor C6 are connected to the external input power supply voltage Vss. The control ends of switches SW4, SW6, SW8, SW10, SW12 and SW14 are respectively connected to the switch control signals a[0] to a[5] output by the switch signal generation module. The control ends of switches SW5, SW7, SW9, SW11, SW32 and SW15 are respectively connected to the switch control signals b[0] to b[5] output by the switch signal generation module. The non-inverting input end of comparator COMP1 is connected to the external input reference voltage VH. The inverting input terminal of the comparator COMP2 is connected to the external input reference voltage VL. The control terminals of the comparators COMP1 and COMP2 are connected to the clock signal CLK_COMP output by the system clock generation module. The output terminals of the comparators COMP1 and COMP2 are respectively connected to the two input terminals of the NAND gate NAND1, and the output terminal of the NAND gate NAND1 is connected to the input terminal of the event-driven logic unit EVENT LOGIC. The control terminal of the event-driven logic unit EVENT LOGIC is connected to the clock signal CLK_DAC output by the system clock generation module. The output terminal of the event-driven logic unit EVENT LOGIC outputs control signals S0 and S1.

[0007] The system clock generation module is composed of a frequency divider Divder, D flip-flops DFF1 to DFF3, multiplexers MUX1 and MUX2, delayers DELAY1 and DEALY2, AND gate AND1, and inverters INV7 and INV8. The input of the frequency divider is connected to the external input clock signal CP, and the output of the frequency divider is connected to the clock input of the D flip-flop DFF1, the input of the delay DELAY2, and the 1 input of the multiplexers MUX1 and MUX2. The D end of the D flip-flop DFF1 is connected to the The Q end of the D flip-flop DFF1 is connected to the clock input end of the D flip-flop DFF2, and the D end of the D flip-flop DFF2 is connected to the The output end of the delayer DELAY2 and the Q end of the D flip-flop DFF2 are respectively connected to the two input ends of the AND gate AND1, and the output end of the AND gate AND1 is connected to the clock input end of the D flip-flop DFF3. The D end of the D flip-flop DFF3 is connected to the control signal S1 output by the level-crossing analog-to-digital conversion module. The Q end of the D flip-flop DFF3 is connected to the control end of the multiplexer MUX1. The output end of the multiplexer MUX1 is connected to the input end of the inverting INV7 and the input end of the delayer DELAY1, and outputs the clock signal CLK_DAC. The output end of the inverting INV7 outputs the clock signal CLK_DACN. The output end of the delayer DELAY1 is connected to the input end of the inverter INV8, and the output end of the inverter INV8 outputs the clock signal CLK_COMP. The 0 input terminal of the multiplexer MUX2 is connected to the external input power supply voltage Vss, the control terminal of the multiplexer MUX2 is connected to the control signal S0 output by the level-crossing analog-to-digital conversion module, and the output terminal of the multiplexer MUX2 outputs the control signal FS.

[0008] The switch signal generating module is composed of NAND gates NAND2 to NAND7 and inverters INV1 to INV6. One end of the NAND gates NAND2 to NAND7 is connected to the clock signal CLK_DAC output by the system clock generating module. The other end of the NAND gates NAND2 to NAND7 is respectively connected to the upper six-bit signals D[5] to D

[10] in the digital signal D[10:0] output by the successive approximation analog-to-digital conversion module. The output ends of the NAND gates NAND2 to NAND7 are respectively connected to the input ends of the inverters INV1 to INV6, and respectively output the switch control signals b[0] to b[5]. The output ends of the inverters INV1 to INV6 respectively output the switch control signals a[0] to a[5].

[0009] Compared with the prior art, the present invention has the following characteristics:

[0010] 1. A hybrid architecture of SAR ADC and event-driven LC ADC was constructed. Taking advantage of the superior low energy consumption of SAR ADC, a sampling rate of only 40ksps is required to achieve a bandwidth requirement of 20kHz while meeting the Nyquist sampling requirement.

[0011] 2. The output of the SAR ADC is used as the output of the entire system, so that the accuracy of the output signal is not affected by the accuracy of the LC ADC. The traditional LC ADC architecture requires the output time domain pulse signal to be regenerated to obtain the digital code output, while the digital code of the present invention is output by the SAR ADC and does not need to be regenerated.

[0012] 3. The present invention performs level crossing detection through the difference between the output of the system at the previous moment and the input of the system at the current moment. Only a 40kHz clock signal is needed to complete the level crossing detection of signals within 20kHz, while the traditional LCADC needs to reach a speed of at least MHz or very low accuracy to meet the requirement of detecting the change rate of 20kHz signal.

[0013] 4. The event-driven logic control module of the traditional LC ADC is generated by using an external FPGA. The present invention integrates the event-driven logic control module with the remaining parts to improve the circuit integration and convenience during use.

[0014] 5. Reduce the power consumption of LC ADC (<4uW) while ensuring medium accuracy (effective number of bits > 10bit) and large bandwidth (<20kHz). BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The schematic diagram of a successive approximation and event-driven hybrid level-crossing ADC circuit is shown in FIG.

[0016] Figure 2 This is the circuit schematic diagram of the CLK_GEN module.

[0017] Figure 3 This is the workflow diagram of the EVENT LOGIC module.

[0018] Figure 4 This is the simulation result diagram of the CLK_GEN module.

[0019] Figure 5 This is the system working timing diagram at the level crossing moment.

[0020] Figure 6 This is the system simulation result diagram under 117.1875Hz sinusoidal signal input.

[0021] Figure 7This is the frequency domain result diagram of the output signal under 117.1875Hz sinusoidal signal input.

[0022] Figure 8 This is the system simulation result diagram under 19453.125Hz sinusoidal signal input.

[0023] Fig. 9 This is the frequency domain result diagram of the output signal under the 19453.125Hz sinusoidal signal input.

[0024] Fig.10 Figure 2 is a diagram of system simulation results using a low-frequency ECG signal as input example. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific examples and with reference to the accompanying drawings.

[0026] A successive approximation and event-driven hybrid level-crossing ADC circuit, such as Figure 1 As shown, it includes a level crossing analog-to-digital conversion module LC ADC, a system clock generation module CLK_GEN, a successive approximation analog-to-digital conversion module SAR ADC, and a switch signal generation module.

[0027] The level-crossing analog-to-digital conversion module is connected to the external input power supply voltage Vss, the analog signal Vin, the reference voltage Vref, the reference voltage VH and the reference voltage VL, the switch control signals a[0]-a[5] and b[0]-b[5] output by the switch signal generation module, and the clock signals CLK_DAC, CLK_DACN and CLK_COMP output by the system clock generation module. The level-crossing analog-to-digital conversion module outputs control signals S0 and S1.

[0028] The above-mentioned level cross analog-to-digital conversion module is composed of switches SW1-SW15, capacitors C0-C6, comparators COMP1 and COMP2, NAND gate NAND1, and event-driven logic unit EVENT LOGIC. One end of switch SW1 is connected to the external input analog signal Vin, and the other end of switch SW1 is connected to one end of capacitors C0-C5 and one end of switch SW2. The other end of capacitor C0 is connected to one end of switches SW4 and SW5. The other end of capacitor C1 is connected to one end of switches SW6 and SW7. The other end of capacitor C2 is connected to one end of switches SW8 and SW9. The other end of capacitor C3 is connected to one end of switches SW10 and SW11. The other end of capacitor C4 is connected to one end of switches SW12 and SW13. The other end of capacitor C5 is connected to one end of switches SW14 and SW15. The other end of switch SW2 is connected to one end of capacitor C6, one end of switch SW3, the inverting input end of comparator COMP1, and the non-inverting input end of comparator COMP2. The control ends of switches SW1 and SW3 are connected to the clock signal CLK_DAC output by the system clock generation module. The control end of switch SW2 is connected to the clock signal CLK_DACN output by the system clock generation module. The other ends of switches SW4, SW6, SW8, SW10, SW12, SW14 and SW3 are connected to the external input reference voltage Vref. The other ends of switches SW5, SW7, SW9, SW11, SW32 and SW15 and the other end of capacitor C6 are connected to the external input power supply voltage Vss. The control ends of switches SW4, SW6, SW8, SW10, SW12 and SW14 are respectively connected to the switch control signals a[0] to a[5] output by the switch signal generation module. The control ends of switches SW5, SW7, SW9, SW11, SW32 and SW15 are respectively connected to the switch control signals b[0] to b[5] output by the switch signal generation module. The non-inverting input end of comparator COMP1 is connected to the external input reference voltage VH. The inverting input terminal of the comparator COMP2 is connected to the external input reference voltage VL. The control terminals of the comparators COMP1 and COMP2 are connected to the clock signal CLK_COMP output by the system clock generation module. The output terminals of the comparators COMP1 and COMP2 are respectively connected to the two input terminals of the NAND gate NAND1, and the output terminal of the NAND gate NAND1 is connected to the input terminal of the event-driven logic unit EVENT LOGIC. The control terminal of the event-driven logic unit EVENT LOGIC is connected to the clock signal CLK_DAC output by the system clock generation module. The output terminal of the event-driven logic unit EVENT LOGIC outputs control signals S0 and S1.

[0029] The system clock generation module is connected to the external input power supply voltage Vss and the clock signal CP, as well as the control signals S0 and S1 output by the level crossing analog-to-digital conversion module. The system clock generation module outputs clock signals CLK_DAC, CLK_DACN and CLK_COMP and a control signal FS.

[0030] The system clock generation module is composed of a frequency divider Divder, D flip-flops DFF1 to DFF3, multiplexers MUX1 and MUX2, delays DELAY1 and DEALY2, AND gate AND1, and inverters INV7 and INV8. Figure 2 As shown. The input end of the frequency divider is connected to the external input clock signal CP, and the output end of the frequency divider is connected to the clock input end of the D flip-flop DFF1, the input end of the delay DELAY2, and the 1 input end of the multiplexers MUX1 and MUX2. The Q end of the D flip-flop DFF1 is connected to the clock input end of the D flip-flop DFF2, and the D end of the D flip-flop DFF2 is connected to the The output end of the delayer DELAY2 and the Q end of the D flip-flop DFF2 are respectively connected to the two input ends of the AND gate AND1, and the output end of the AND gate AND1 is connected to the clock input end of the D flip-flop DFF3. The D end of the D flip-flop DFF3 is connected to the control signal S1 output by the level-crossing analog-to-digital conversion module. The Q end of the D flip-flop DFF3 is connected to the control end of the multiplexer MUX1. The output end of the multiplexer MUX1 is connected to the input end of the inverting INV7 and the input end of the delayer DELAY1, and outputs the clock signal CLK_DAC. The output end of the inverting INV7 outputs the clock signal CLK_DACN. The output end of the delayer DELAY1 is connected to the input end of the inverter INV8, and the output end of the inverter INV8 outputs the clock signal CLK_COMP. The 0 input terminal of the multiplexer MUX2 is connected to the external input power supply voltage Vss, the control terminal of the multiplexer MUX2 is connected to the control signal S0 output by the level-crossing analog-to-digital conversion module, and the output terminal of the multiplexer MUX2 outputs the control signal FS.

[0031] The successive approximation analog-to-digital conversion module is connected to the external input power supply voltage Vss and the analog signal Vin, as well as the control signal FS output by the system clock generation module. The successive approximation analog-to-digital conversion module outputs a digital signal D[10:0], which is the final output of the successive approximation and event-driven hybrid level crossing ADC circuit.

[0032] The switch signal generation module is connected to the upper six bits D[5] to D

[10] of the digital signal D[10:0] output by the successive approximation analog-to-digital conversion module and the clock signal CLK_DAC output by the system clock generation module. The switch signal generation module outputs switch control signals a[0] to a[5] and switch control signals b[0] to b[5].

[0033] The switch signal generating module is composed of NAND gates NAND2 to NAND7 and inverters INV1 to INV6. One end of the NAND gates NAND2 to NAND7 is connected to the clock signal CLK_DAC output by the system clock generating module. The other end of the NAND gates NAND2 to NAND7 is respectively connected to the upper six-bit signals D[5] to D

[10] in the digital signal D[10:0] output by the successive approximation analog-to-digital conversion module. The output ends of the NAND gates NAND2 to NAND7 are respectively connected to the input ends of the inverters INV1 to INV6, and respectively output the switch control signals b[0] to b[5]. The output ends of the inverters INV1 to INV6 respectively output the switch control signals a[0] to a[5].

[0034] The working principle of the present invention is:

[0035] The input signal Vin is first sent to the level-crossing analog-to-digital conversion module. The level-crossing analog-to-digital conversion module performs level-crossing detection according to the switch signal generated by the switch signal generation module, determines whether a level cross occurs, and outputs a CHANGE signal to control the working state of the event-driven logic unit EVENT LOGIC. The event-driven logic unit EVENTLOGIC outputs different control signals S0 and S1. The system clock generation circuit will output different system clock signals CLK_DAC, CLK_DACN, CLK_COMP and control signal FS according to the control signals S0 and S1, which are used to control the operation of the level-crossing analog-to-digital conversion module and the successive approximation analog-to-digital conversion module. The 11-bit digital signal D[10:0] output by the successive approximation analog-to-digital conversion module is the output result of the ADC. The upper six bits D[5]~D

[10] of D[10:0] and CLK_DAC are input to the switch signal generation module to generate switch control signals a[0]~a[5] and b[0]~b[5].

[0036] The event-driven logic unit EVENT LOGIC has two input signals CHANGE and CLK_DAC. CHANGE is a level-crossing trigger signal output by the NAND gate NAND1, which is used to control the working state of the event-driven logic unit EVENT LOGIC. CLK_DAC is a clock signal output by the system clock generation module, which serves as the clock of the event-driven logic unit EVENT LOGIC. The workflow diagram of the event-driven logic unit EVENT LOGIC is shown in the figure below. Figure 3 As shown. After power-on reset, the output control signal S0=1, S1=1, set the internal counter counter=8. When S0=1, S1=1, the control level crossing analog-to-digital conversion module and the successive approximation analog-to-digital conversion module are detected and converted at a normal speed, and the state is represented as a normal detection conversion state. The next process determines whether counter is greater than 4. If it is YES, counter is counted down, and then it is determined whether CHANGE is 1, that is, whether a level crossing occurs. If it is YES, it jumps to S0=1, S1=1 after the start, and sets the internal counter counter=8. If it is NO, it continues to return to determine whether counter is greater than 4, and the cycle continues. If no level crossing occurs after 4 CLK_DAC clock cycles, the result of determining whether counter is greater than 4 is NO, and the next process is entered, and the output control signal S0=0, S1=1. When S0=0, S1=1, the control level crossing analog-to-digital conversion module is detected at a normal speed, and the control successive approximation analog-to-digital conversion module stops converting, and the state is represented as a normal detection state. The next process determines whether counter is greater than 0. If it is YES, counter counts down, and then determines whether CHANGE is 1, that is, whether a level crossing occurs. If it is YES, it jumps to S0=1, S1=1 after the start, and sets the internal counter counter=8. If it is NO, it continues to return to determine whether counter is greater than 0, and the cycle continues. If there is no level crossing after 4 CLK_DAC clocks, the result of determining whether counter is greater than 0 is NO, and the next process is entered, and the control signal S0=0, S1=0 is output. When S0=0, S1=0, the control level crossing analog-to-digital conversion module is detected at one-fourth of the normal speed, and the successive approximation analog-to-digital conversion module stops conversion. Therefore, the detection speed of the level crossing analog-to-digital conversion module is only one-fourth of the normal detection state, so the state is represented as a slow detection state. The next process determines whether CHANGE is 1, that is, detects whether a level crossing occurs. If it is YES, it jumps to S0=1, S1=1 after the start, and sets the internal counter counter=8. If it is NO, it continues to repeat the judgment and waits for the CHANGE=1 signal to arrive.

[0037] The system clock generation module generates the clock according to the two control signals S0 and S1. When the external clock signal CP is 520kHz, the level cross analog-to-digital conversion module divides the frequency by 13 to obtain a signal CLK_DIV1 with a frequency of 40kHz. Figure 3The workflow diagram of the event-driven logic unit EVENTLOGIC is shown in FIG. If a level crossing occurs, CHANGE=1, and the event-driven logic unit EVENT LOGIC will output control signals S0=1, S1=1. The frequency of the output signal CLK_DAC of the system clock generation module is 40kHz, and the CLK_DAC signal controls the detection of the level crossing analog-to-digital conversion module. The frequency of the output signal FS of the system clock generation module is 40kHz, and the FS signal controls the conversion of the successive approximation analog-to-digital conversion module. The state when S0=1, S1=1 represents the normal detection conversion state. If no level crossing occurs, after four CLK_DAC cycles, counter>4 is judged as NO, and the event-driven logic unit EVENT LOGIC outputs control signals S0=0, S1=1. At this time, CLK_DAC still outputs a 40kHz signal, and FS outputs a low level Vss to stop the conversion of the successive approximation analog-to-digital conversion module. The state when S0=0, S1=1 represents the normal detection state. If there is still no level crossing at this time, after 4 CLK_DAC cycles, counter>0 is judged as NO, and the event-driven logic unit EVENT LOGIC will output the control signal S0=0, S1=0. At this time, the signal output by CLK_DAC is CLK_DIV1, which is divided by the 4-divider composed of two D flip-flops DFF1 and DFF2, and the output frequency is 10kHz signal CLK_DIV2, which controls the detection of the level crossing analog-to-digital conversion module. FS continues to output low level Vss, and the successive approximation analog-to-digital conversion module stops converting. The state when S0=0, S1=0 is because the successive approximation analog-to-digital conversion module stops converting, and the level crossing analog-to-digital conversion module works at 10kHz, while the level crossing analog-to-digital conversion module works at 40kHz in the normal detection state, which is only one-fourth of the normal detection state. Therefore, the state when S0=0, S1=0 indicates a slow detection state, waiting for the level crossing signal CHANGE=1 to arrive. During the operation of the event-driven logic unit EVENTLOGIC, as long as the level-crossing analog-to-digital conversion module detects a level crossing, CHANGE=1 will control the event-driven logic unit EVENT LOGIC to output control signals S0=1, S1=1, and counter=8, thereby starting a new count.

[0038] The simulation results of the event-driven logic unit EVENT LOGIC and the system clock generation circuit CLK_GEN are as follows: Figure 4 The simulation results show that CLK_DIV1 is the output of CP after dividing by 13, and the frequency of CLK_DIV1 is 40kHz. Figure 4The x-axis time starts at 2.83ms. At this time, S0=0, S1=0, and the frequency of CLK_DAC is 10kHz, which is one-fourth of the normal working state. It is in a slow detection state. The level crossing analog-to-digital conversion module detects the level crossing at one-fourth of the speed in the normal detection state. FS outputs a low level Vss to stop the conversion of the successive approximation analog-to-digital conversion module to reduce power consumption. Figure 4 At the cursor V1 moment, the level crossing analog-to-digital conversion module detects the level crossing, CHANGE=1, EVENT LOGIC outputs control signals S0=1, S1=1, and CLK_GEN outputs a 40kHz signal from FS according to S0 and S1 to start the successive approximation analog-to-digital conversion module for conversion, while CLK_DAC switches back to 40kHz and enters the normal detection conversion state. No level crossing is detected within 4 CLK_DAC cycles, so after 4 CLK_DAC cycles, it enters the normal detection state. From the simulation results, it can be seen that S0 changes from 1 to 0, indicating that EVENT LOGIC outputs control signals S0=0, S1=1. In CLK_GEN, FS outputs Vss, and the successive approximation analog-to-digital conversion module stops converting.

[0039] Figure 5 This is the system working timing diagram at the time of level crossing, which is equivalent to Figure 4 At the cursor V1 in the figure, a level crossing is detected. At t-2, a level crossing is detected, CHANGE = 1, that is, EVENT LOGIC outputs control signals S0 = 1, S1 = 1, CLK_DAC outputs a 40kHz signal, and FS outputs a 40kHz signal. At t-1, FS rises, indicating that the successive approximation analog-to-digital conversion module starts a conversion. The outputs a[0]~a[5] and b[0]~b[5] of the switch signal generation module are obtained by the conversion results of the successive approximation analog-to-digital conversion module at t-1 and CLK_DAC. The specific switch status is shown in Table 1, where n is 0 to 5.

[0040] Table 1 Output truth table of the switch signal generation module

[0041] CLK_DAC a[n] b[n] 0 0 1 1 D[n+5] D[n+5]

[0042] Switch SW1, SW4~SW15 and capacitors C0~C5 form a 6-bit DAC. At time t, CLK_DAC rises, and the level-crossing analog-to-digital conversion module enters the sampling state. The input signal is input by the 6-bit DAC in the level-crossing analog-to-digital conversion module, CLK_DAC is 1, CLK_DACN is 0, that is, SW1 is closed, SW2 is open, and SW3 is closed. The input signal is input to the upper plate of the 6-bit DAC through the Bootstrap switch SW1, and the lower plate of the 6-bit DAC is connected to Vref and Vss respectively according to the output a[0]~a[5] and b[0]~b[5] of the 6-bitDAC switch signal generation module generated at time t-1. The reason why SW1 uses the Bootstrap switch here is that the gate-source voltage of the switch tube in SW1 can be kept constant, so as to adapt to the constant on-resistance of SW1 under input signals of different amplitudes, thereby achieving stable signal sampling and holding, and improving the accuracy and performance of the sampling circuit. In the sampling state of the level-crossing analog-to-digital conversion module, the switch states of a[0]~a[5] and b[0]~b[5] will be determined by the output result after the successive approximation analog-to-digital conversion module is completed at time t-1. After time t, CLK_DAC falls and the sampling state of the level-crossing analog-to-digital conversion module ends. At this time, CLK_DAC=0, CLK_DACN=1, and the switch states of a[0]~a[5] and b[0]~b[5] are 0 according to Table 1, and b[0]~b[5] are 1, that is, the lower plates of the capacitors of the 6-bit DAC are all connected to Vss. Assume that the voltage of the input signal converted by the successive approximation analog-to-digital conversion module at time t-1 is V(t-1), and the voltage of the input signal collected by the level crossing analog-to-digital conversion module at time t is V(t). After the sampling is completed, SW1 is disconnected, and the switch states of a[0]~a[5] and b[0]~b[5] change, the upper plate voltage of the 6-bit DAC is:

[0043] V dac =V(t)-V(t-1)

[0044] The total capacitance of the 6-bit DAC is 63C, where C represents the unit capacitance and the capacitance of C6 is 63C. After SW3 is disconnected, the charges on the 6-bit DAC and C6 are:

[0045] Q DAC =63C*V dac

[0046] Q C6 =63C*Vref

[0047] After SW2 is closed, the charge of the capacitor is redistributed, and the final voltage input to comparators COMP1 and COMP2 is:

[0048] V dac =(V(t)-V(t-1)+Vref) / 2

[0049] It should be noted that after the sampling of the level-crossing analog-to-digital conversion module is completed, SW1 is disconnected, SW2 is closed, and SW3 is disconnected at the same time, so the final output signal of the 6-bitDAC and C6 can be approximated to be half of the difference between the input signal at time t-1 and the input signal at time t plus Vref / 2. Considering that for the falling signal V(t)<V(t-1), this method can avoid negative pressure by shifting the level up by Vref / 2, and at the same time, the common-mode input level of the comparator can be controlled near Vref / 2, reducing the difficulty of comparator design.

[0050] After a short delay, the comparator clock signal CLK_COMP rises, and COMP1 and COMP2 redistribute the charge between the 6-bit DAC and C6 to produce the output result V dac The output of the two comparators is input to the NAND gate NAND1, and the NAND gate outputs the signal CHANGE. If the output of the 6-bit DAC and C6 after charge redistribution is V dac After comparing with VH and VL, if it is higher than VH or lower than VL, then CHANGE = 1, indicating a level crossing. Then CHANGE is input to EVENT LOGIC for processing, and the output control signals S0 = 1, S1 = 1 are used to control the system clock generation circuit CLK GEN. If the result V after the 6-bit DAC and C6 perform charge redistribution dac If it is neither higher than VH nor lower than VL, CHANGE continues to be 0, indicating that the levels have not crossed and EVENT LOGIC continues to maintain its current operation.

[0051] Figure 6The transient simulation result when the input Vin is a 117.1875Hz sinusoidal signal. The simulation waveforms from top to bottom are the output signal CHANGE of the NAND gate NAND1, the Dout signal is the output of the 11-bit digital signal D[10:0] output by the successive approximation analog-to-digital conversion module after being restored by an ideal DAC, FS is the output of the system clock generation module CLK_GEN, which is used to control the operation of the successive approximation analog-to-digital conversion module, Vin is a sinusoidal signal with an external input frequency of 117.1875Hz, and CLK_DAC is the signal output by CLK_GEN for controlling the level-crossing analog-to-digital conversion module and the 6-bit DAC switch signal generation module. From the results, it can be seen that for the CHANGE signal, when the input signal Vin reaches the maximum value, the signal amplitude changes little, and the CHANGE signal does not appear to be set to 1, indicating that no level crossing occurs in the level-crossing analog-to-digital conversion module. The same is true when Vin reaches the minimum value. The amplitude change is not obvious and no level crossing occurs. The FS signal is used as the conversion control signal of the successive approximation analog-to-digital conversion module. Within 4 CLK_DAC cycles, the level-crossing analog-to-digital conversion module does not detect the level crossing, and FS outputs Vss. The successive approximation analog-to-digital conversion module stops converting, so Dout is displayed as a straight line. For the CLK_DAC signal, within 4 CLK_DAC cycles after FS outputs Vss, the level-crossing analog-to-digital conversion module still does not detect the level crossing, and the frequency is switched to 10kHz to reduce system power consumption. The output Dout is exported for FFT to obtain the dynamic parameters at this frequency. Because the amplitude of Vin changes very little at the maximum and minimum values, the conversion of the successive approximation analog-to-digital conversion module does not occur, so the output data is manifested as non-uniform sampling. The output data needs to be interpolated and reconstructed. The non-uniform data is interpolated and reconstructed into uniform data before FFT is performed, and the following is finally obtained. Figure 7 As shown in the results, the effective number of bits is 10.1 bits, the spurious-free dynamic range is 64.7 dB, the signal-to-noise-distortion ratio is 62.3 dB, and the power consumption is only 2.439 uW.

[0052] The simulated output waveform when the input signal Vin frequency is 19453.125Hz is as follows Figure 8As shown, it can be seen from the simulation results that the FS did not output Vss at this time, indicating that the successive approximation analog-to-digital conversion module has been converting, and from the CHANGE signal, there was a level crossing in the simulation results and the analog-to-digital conversion module did not detect the level crossing, because after this time, the level crossing analog-to-digital conversion module continued to detect the level crossing. According to the EVENTLOGIC workflow diagram, the FS will output Vss after 4 CLK_DAC cycles without level crossing. Therefore, the FS has not yet reached the condition to output Vss here. The biggest advantage of this is that it ensures the integrity of the signal when the output frequency is high. The higher the frequency, the more difficult the interpolation is. Therefore, this method can well ensure the integrity of the signal at high frequencies, thereby increasing the effective number of bits. The CLK_DAC signal can also continuously detect the level crossing because the level crossing analog-to-digital conversion module can output a 40kHz signal, ensuring that the level crossing analog-to-digital conversion module continues to detect the level crossing. The FFT result of Dout is shown as follows Fig. 9 As shown, due to the good signal integrity, there is no need to perform interpolation reconstruction, and the signal is directly subjected to FFT. It can be seen from the figure that the effective number of bits is 10.9 bits, the spurious-free dynamic range is as high as 79.2 dB, the signal-to-noise distortion ratio is 67.7 dB, and the power consumption is 3.768 uW.

[0053] The simulation example with ECG signal as input signal Vin is as follows Fig.10As shown, the external input signal Vin is a complete ECG signal. From the simulation results, it can be seen that at the cursor V1 and V2 moments, it is the time period when the amplitude of Vin changes more obviously. In these two time periods, according to the CHANGE signal, it can be seen that the level crossing analog-to-digital conversion module detects more level crossings in these two time periods, and FS indicates that the number of conversions of the successive approximation analog-to-digital conversion module is also more, while at other moments, it is less, so the output signal Dout of the successive approximation analog-to-digital conversion module is obtained. At moment V1, Vin does not change significantly, so the level crossing analog-to-digital conversion module does not detect the level crossing, but on both sides of V1, the level crossing is detected, and the successive approximation analog-to-digital conversion module is correspondingly triggered to perform conversion, because the principle of the present invention is based on the subtraction of the input signal at this moment and the output of the successive approximation analog-to-digital conversion module at the previous moment, so if no level crossing occurs at the current moment, the difference between the input at the next moment and the output of the successive approximation analog-to-digital conversion module will be accumulated until the level crossing detection of the level crossing analog-to-digital conversion module is triggered. The biggest advantage of this is that when the Vin frequency is low, the integrity of the signal can be improved, that is, no matter how low the signal frequency changes, as long as the overall amplitude change exceeds the detection window of the level crossing analog-to-digital conversion module, the level crossing of the level crossing analog-to-digital conversion module will be triggered, and the simulation output results between V1 and V2 reflect this advantage. From the output Dout of the successive approximation analog-to-digital conversion module in the figure, between V1 and V2, although the change amplitude of Vin is very low, after a long period of time, the level crossing analog-to-digital conversion module still detects the level crossing, and the successive approximation analog-to-digital conversion module performs conversion, which improves the integrity of this section of the signal. The time period near V2 is the period of time with the largest change amplitude in the ECG signal. During this period of time, the level crossing analog-to-digital conversion module is continuously triggered, and the successive approximation analog-to-digital conversion module continues to convert. The final average power consumption for the entire period is 158nW, which shows that the present invention can achieve very low power consumption when processing characteristic signals with strong sparsity in the time domain, such as biomedical signals.

[0054] The present invention is suitable for the conversion of low-frequency signals such as electrocardiogram signals. The lower the frequency of the signal, the lower the power consumption of the system. The conversion can be triggered only when the signal change amplitude exceeds a certain range. At the same time, continuous detection can be performed when the signal amplitude changes rapidly. It is very suitable for the conversion of sparse analog signals in the time domain.

[0055] The present invention mixes a successive approximation analog-to-digital conversion module on the basis of a traditional level-crossing analog-to-digital conversion module, combines the advantages of two ADC architectures, and can reduce power consumption while maintaining medium resolution and large bandwidth. Since the traditional level-crossing analog-to-digital conversion module architecture usually uses a bidirectional shift register to perform level crossing detection, when the input signal frequency is high, in order to meet the change rate requirement of the input signal, the level-crossing analog-to-digital conversion module needs to work at a very high frequency. When the bandwidth exceeds 10kHz, the traditional level-crossing analog-to-digital conversion module usually works at a frequency above MHz, resulting in increased power consumption. The present invention does not require a bidirectional shift register, and uses a 6-bit DAC in the level-crossing analog-to-digital conversion module to process the input signal. The 6-bit DAC is combined with the high 6 bits of the output data of the successive approximation analog-to-digital conversion module to realize V(t)-V(t-1), wherein V(t) represents the input at the current moment, and V(t-1) represents the input at the previous moment. The level crossing detection is performed by using the difference and the reference voltage VH and the reference voltage VL. The level crossing detection is performed by using the high-bit data of the successive approximation analog-to-digital conversion module and the level-crossing analog-to-digital conversion module, and there is no need to consider the change rate requirement of the input signal. In this way, the operating frequency of the level-crossing analog-to-digital conversion module can be greatly reduced. At the same time, at a lower operating frequency and medium precision, the architecture of the successive approximation analog-to-digital conversion module itself has a superior energy consumption advantage, so lower system power consumption can be achieved under the conditions of medium resolution and large bandwidth. Compared with the traditional shift register method, the present invention can realize the level crossing detection of any input frequency at a very low clock frequency. At the same time, the successive approximation analog-to-digital conversion module has a very superior low energy consumption performance at a low clock frequency, which can make the power consumption of the entire system very low. The successive approximation analog-to-digital conversion module can make the output of the system not affected by the accuracy of the level crossing analog-to-digital conversion module. At the same time, there is no need to perform signal regeneration processing, and the output data can be directly subjected to subsequent digital signal processing. At the same time, the present invention uses a digital-analog hybrid design method, and uses a digital method to implement the logic processing module in the system, thereby eliminating the need for external logic devices such as FPGAs, thereby improving the circuit integration and ease of use.

[0056] It should be noted that, although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A successive approximation and event-driven hybrid level-crossing ADC circuit, characterized in that: It includes a level-crossing analog-to-digital conversion module, a system clock generation module, a successive approximation analog-to-digital conversion module, and a switch signal generation module; The level-crossing analog-to-digital conversion module is connected to the external input power supply voltage Vss, the analog signal Vin, the reference voltage Vref, the reference voltage VH and the reference voltage VL, the switch control signals a[0]-a[5] and b[0]-b[5] output by the switch signal generation module, and the clock signals CLK_DAC, CLK_DACN and CLK_COMP output by the system clock generation module; the level-crossing analog-to-digital conversion module outputs control signals S0 and S1; The system clock generation module is connected to the external input power supply voltage Vss and the clock signal CP, as well as the control signals S0 and S1 output by the level crossing analog-to-digital conversion module; the system clock generation module outputs clock signals CLK_DAC, CLK_DACN and CLK_COMP and the control signal FS; The successive approximation analog-to-digital conversion module is connected to the external input power supply voltage Vss and the analog signal Vin, as well as the control signal FS output by the system clock generation module; the successive approximation analog-to-digital conversion module outputs a digital signal D[10:0]; The switch signal generating module is connected to the upper six-bit signals D[5]~D[10] in the digital signal D[10:0] output by the successive approximation analog-to-digital conversion module, and the clock signal CLK_DAC output by the system clock generating module; the switch signal generating module outputs switch control signals a[0]~a[5] and switch control signals b[0]~b[5].

2. The successive approximation and event-driven hybrid level-crossing ADC circuit according to claim 1, characterized in that: Level Crossing The analog-to-digital conversion module is composed of switches SW1-SW15, capacitors C0-C6, comparators COMP1 and COMP2, NAND gate NAND1, and event-driven logic unit EVENT LOGIC; One end of the switch SW1 is connected to the external input analog signal Vin, and the other end of the switch SW1 is connected to one end of the capacitors C0 to C5 and one end of the switch SW2; the other end of the capacitor C0 is connected to one end of the switches SW4 and SW5; the other end of the capacitor C1 is connected to one end of the switches SW6 and SW7; the other end of the capacitor C2 is connected to one end of the switches SW8 and SW9; the other end of the capacitor C3 is connected to one end of the switches SW10 and SW11; the other end of the capacitor C4 is connected to one end of the switches SW12 and SW13; the other end of the capacitor C5 is connected to one end of the switches SW14 and SW15; the other end of the switch SW2 is connected to one end of the capacitor C6, one end of the switch SW3, the inverting input end of the comparator COMP1, and the non-inverting input end of the comparator COMP2; The control ends of switches SW1 and SW3 are connected to the clock signal CLK_DAC output by the system clock generation module; the control end of switch SW2 is connected to the clock signal CLK_DACN output by the system clock generation module; The other ends of switches SW4, SW6, SW8, SW10, SW12, SW14 and SW3 are connected to an externally input reference voltage Vref; the other ends of switches SW5, SW7, SW9, SW11, SW32 and SW15 and the other end of capacitor C6 are connected to an externally input power supply voltage Vss; The control ends of switches SW4, SW6, SW8, SW10, SW12 and SW14 are respectively connected to switch control signals a[0] to a[5] output by the switch signal generating module; the control ends of switches SW5, SW7, SW9, SW11, SW32 and SW15 are respectively connected to switch control signals b[0] to b[5] output by the switch signal generating module; The non-inverting input terminal of the comparator COMP1 is connected to the external input reference voltage VH; the inverting input terminal of the comparator COMP2 is connected to the external input reference voltage VL; the control terminals of the comparators COMP1 and COMP2 are connected to the clock signal CLK_COMP output by the system clock generation module; The output ends of the comparators COMP1 and COMP2 are respectively connected to the two input ends of the NAND gate NAND1, the output end of the NAND gate NAND1 is connected to the input end of the event-driven logic unit EVENT LOGIC, the control end of the event-driven logic unit EVENT LOGIC is connected to the clock signal CLK_DAC output by the system clock generation module; the output end of the event-driven logic unit EVENT LOGIC outputs control signals S0 and S1.

3. The successive approximation and event-driven hybrid level-crossing ADC circuit according to claim 1, characterized in that: The system clock generation module is composed of a frequency divider Divder, D flip-flops DFF1 to DFF3, multiplexers MUX1 and MUX2, delayers DELAY1 and DEALY2, AND gate AND1, and inverters INV7 and INV8; The input end of the frequency divider is connected to the external input clock signal CP, and the output end of the frequency divider is connected to the clock input end of the D flip-flop DFF1, the input end of the delay device DELAY2, and the 1 input ends of the multiplexers MUX1 and MUX2; The D terminal of D flip-flop DFF1 is connected to The Q end of the D flip-flop DFF1 is connected to the clock input end of the D flip-flop DFF2, and the D end of the D flip-flop DFF2 is connected to the The Q end of the D flip-flop DFF2 is connected to the 0 input end of the multiplexer MUX1; The output end of the delay device DELAY2 and the Q end of the D flip-flop DFF2 are respectively connected to the two input ends of the AND gate AND1, and the output end of the AND gate AND1 is connected to the clock input end of the D flip-flop DFF3; the D end of the D flip-flop DFF3 is connected to the control signal S1 output by the level crossing analog-to-digital conversion module; the Q end of the D flip-flop DFF3 is connected to the control end of the multiplexer MUX1; the output end of the multiplexer MUX1 is connected to the input end of the inverting INV7 and the input end of the delay device DELAY1, and outputs the clock signal CLK_DAC; The output end of the inverting INV7 outputs the clock signal CLK_DACN; the output end of the delay device DELAY1 is connected to the input end of the inverter INV8, and the output end of the inverter INV8 outputs the clock signal CLK_COMP; The 0 input terminal of the multiplexer MUX2 is connected to the external input power supply voltage Vss, the control terminal of the multiplexer MUX2 is connected to the control signal S0 output by the level-crossing analog-to-digital conversion module, and the output terminal of the multiplexer MUX2 outputs the control signal FS.

4. The successive approximation and event-driven hybrid level-crossing ADC circuit according to claim 1, characterized in that: The switch signal generating module is composed of NAND gates NAND2 to NAND7 and inverters INV1 to INV6; One end of the NAND gates NAND2 to NAND7 is connected to the clock signal CLK_DAC output by the system clock generation module; the other ends of the NAND gates NAND2 to NAND7 are respectively connected to the upper six-bit signals D[5] to D[10] of the digital signal D[10:0] output by the successive approximation analog-to-digital conversion module; The output ends of the NAND gates NAND2 to NAND7 are connected to the input ends of the inverters INV1 to INV6, respectively, and output switch control signals b[0] to b[5] respectively; the output ends of the inverters INV1 to INV6 output switch control signals a[0] to a[5] respectively.

Images