High-side switching circuit

Abstract

The embodiment of the invention provides a high-side switching circuit which comprises a first power supply, a first switching transistor and a driving circuit, the first end of the first switching transistor is connected with the first power supply, and the second end of the first switching transistor is connected with a load circuit. The gate end and the second end of the first switch transistor are connected with the driving circuit; the first power supply provides first voltage for the first switching transistor; the driving circuit receives the second voltage and uplifts the second voltage to obtain a bias voltage, and then controls whether to turn on the first switching transistor or not according to the bias voltage; wherein the lifting processing enables the difference between the voltage of the gate end of the first switch transistor and the voltage of the second end to be greater than a preset difference value; when the first switching transistor is turned on, the first switching transistor transmits the first voltage to the load circuit. Therefore, the area of the high-side switch circuit can be reduced, and the switch resistance can be stable.

Description

Technical Field

[0001] The present disclosure relates to the technical field of switching power supplies, and in particular to, but not limited to, a high-side switching circuit. Background Art

[0002] Metal Oxide Semiconductor (MOS) high-side switches are currently widely used in many fields such as automobiles, industry, and mobile devices due to their low loss, easy driving, high reliability, and near-ideal switching characteristics.

[0003] In the related art, P-type MOS tubes (PMOS tubes) are usually used as high-side switches. However, PMOS tubes have two disadvantages as high-side switches: first, the carrier mobility of PMOS tubes is low, and more area is needed to achieve the same on-resistance requirement; second, when PMOS tubes are used as high-side switches, the gate-source voltage is greatly affected by power supply fluctuations, making the on-resistance of the high-side switch unstable. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a high-side switch circuit.

[0005] An embodiment of the present disclosure provides a high-side switch circuit, the high-side switch circuit comprising: a first power supply, a first switch transistor and a drive circuit, wherein a first end of the first switch transistor is connected to the first power supply, a second end of the first switch transistor is connected to a load circuit, and a gate end and a second end of the first switch transistor are both connected to the drive circuit; wherein:

[0006] The first power supply is used to provide a first voltage to the first switching transistor;

[0007] The driving circuit is used to receive a second voltage, and to perform a boost processing on the second voltage. After obtaining a bias voltage, whether to turn on the first switching transistor is controlled according to the bias voltage; wherein the boost processing makes the difference between the voltage at the gate terminal of the first switching transistor and the voltage at the second terminal of the first switching transistor greater than a preset difference; when the first switching transistor is turned on, the first switching transistor transmits the first voltage to the load circuit.

[0008] In some embodiments, the high-side switch circuit further includes a second power supply, and the drive circuit includes: a first charge pump circuit and a second charge pump circuit; a first end of the first charge pump circuit is coupled to the second power supply, and a second end of the first charge pump circuit is connected to a first end of the second charge pump circuit; a second end of the second charge pump circuit is connected to a gate end of the first switch transistor; wherein:

[0009] The second power supply is used to provide the second voltage;

[0010] The first charge pump circuit is used to raise the second voltage to obtain a preset voltage, and transmit the preset voltage to the second charge pump circuit;

[0011] The second charge pump circuit is used to raise the preset voltage to obtain the bias voltage, and apply the bias voltage to the gate terminal of the first switching transistor; wherein the preset voltage and the preset difference are equal in value; during the operation of the high-side switching circuit, the second power supply and the first charge pump circuit are always kept in the turned-on state.

[0012] In some embodiments, the third terminal of the second charge pump circuit is connected to the second terminal of the first switch transistor; wherein:

[0013] The second charge pump circuit is further configured to receive the second terminal voltage of the first switch transistor, and to raise the preset voltage according to the voltage of the second terminal of the first switch transistor to obtain the bias voltage.

[0014] In some embodiments, the high-side switch circuit further includes a second switch transistor and a third power supply; a first end of the second switch transistor is connected to the third power supply, a second end of the second switch transistor is connected to the load circuit, and a gate end of the second switch transistor and a second end of the second switch transistor are connected to the drive circuit; wherein:

[0015] The third power supply is used to provide a third voltage to the second switch transistor;

[0016] The driving circuit, after raising the second voltage to obtain the bias voltage, controls whether to turn on the second switching transistor according to the bias voltage; wherein the raising process also makes the difference between the voltage at the gate terminal of the second switching transistor and the voltage at the second terminal of the second switching transistor greater than the preset difference; when the second switching transistor is turned on, the second switching transistor transmits the third voltage to the load circuit.

[0017] In some embodiments, both the first switch transistor and the second switch transistor are NMOS transistors.

[0018] In some embodiments, the driving circuit further includes a third charge pump circuit; a first end of the third charge pump circuit is connected to a second end of the first charge pump circuit, a second end of the third charge pump circuit is connected to a gate end of the second switch transistor, and a third end of the third charge pump circuit is connected to a second end of the second switch transistor; wherein:

[0019] The third charge pump circuit is used to raise the voltage of the second end of the second switching transistor by the preset difference to obtain the bias voltage, and apply the bias voltage to the gate end of the second switching transistor; the second charge pump circuit and / or the third charge pump circuit are turned on or off according to the working state of the high-side switching circuit.

[0020] In some embodiments, the high-side switch circuit further includes a logic control circuit; the logic control circuit is connected to the control terminal of the second charge pump circuit; wherein:

[0021] The logic control circuit is used to receive an initial control signal, perform logic processing on the initial control signal, generate a first control signal in an enabled state when the initial control signal indicates to turn on the first switch transistor, and transmit the first control signal to the second charge pump circuit;

[0022] Wherein, when the first control signal is in an enabled state, the second charge pump circuit is turned on and the first switch transistor is turned on; when the first control signal is in a disabled state, the second charge pump circuit is turned off and the first switch transistor is turned off.

[0023] In some embodiments, the logic control circuit is also connected to the control terminal of the third charge pump circuit; wherein:

[0024] The logic control circuit is further configured to generate a first control signal in an enabled state and a second control signal in a disabled state when the initial control signal indicates that the first switch transistor is turned on and the second switch transistor is turned off; or, generate a first control signal in a disabled state and a second control signal in an enabled state when the initial control signal indicates that the first switch transistor is turned off and the second switch transistor is turned on; and transmit the first control signal to the second charge pump circuit, and transmit the second control signal to the third charge pump circuit;

[0025] Among them, when the second control signal is in an enabled state, the third charge pump circuit is turned on and the second switch transistor is turned on; when the second control signal is in a disabled state, the third charge pump circuit is turned off and the second switch transistor is turned off.

[0026] In some embodiments, the high-side switch circuit further includes: a dead time control circuit; a first output end of the dead time control circuit is connected to the control end of the second charge pump circuit, and a second output end of the dead time control circuit is connected to the control end of the third charge pump circuit; wherein:

[0027] The dead time control circuit is used to delay the first control signal and / or the second control signal, and then transmit the delayed first control signal to the second charge pump circuit and transmit the delayed second control signal to the third charge pump circuit, respectively, so that after the second charge pump circuit is turned off, the third charge pump circuit is delayed to turn on, or after the third charge pump circuit is turned off, the second charge pump circuit is delayed to turn on.

[0028] In some embodiments, the dead time control circuit includes a logic processing circuit and a delay processing circuit;

[0029] The logic processing circuit is used to receive the first control signal and the second control signal, and perform logic processing according to the first control signal and the second control signal to generate a first intermediate control signal and a second intermediate control signal; wherein, if the first control signal and the second control signal are both in the first level state, then the first intermediate control signal and the second intermediate control signal are both in the second level state; otherwise, the level state of the first intermediate control signal is the same as the first control signal, and the level state of the second intermediate control signal is the same as the second control signal;

[0030] The delay processing circuit is used to receive the first intermediate control signal and the second intermediate control signal, and generate a first target control signal and a second target control signal according to the first intermediate control signal and the second intermediate control signal; wherein, when one of the first intermediate control signal and the second intermediate control signal changes from the second level state to the first level state, after the preset time interval, one of the first target control signal and the second target control signal changes from the second level state to the first level state;

[0031] The first target control signal is the first control signal after delay processing; the second target control signal is the second control signal after delay processing.

[0032] In some embodiments, the logic processing circuit includes a first NAND gate, a first AND gate, and a second AND gate;

[0033] The first input end of the first NAND gate and the first input end of the first AND gate are both used to receive the first control signal, the second input end of the first NAND gate and the second input end of the second AND gate are both used to receive the second control signal, and the output end of the first NAND gate is connected to the second input end of the first AND gate and the first input end of the second AND gate;

[0034] The output end of the first AND gate is used to output the first intermediate control signal;

[0035] The output terminal of the second AND gate is used to output the second intermediate control signal.

[0036] In some embodiments, the delay processing circuit includes a second NAND gate, a first delay unit, a first NOR gate, a third NOR gate, a third NAND gate, a second delay unit, a second NOR gate, a fourth NOR gate, a fifth NOR gate, and a sixth NOR gate;

[0037] The first input end of the second NAND gate is used to receive the first intermediate control signal; the second input end of the second NAND gate is connected to the output end of the fourth NAND gate, and is used to receive the fourth intermediate control signal; the output end of the second NAND gate is connected to the input end of the first delay unit and the first input end of the first NOR gate; the output end of the first delay unit is connected to the second input end of the first NOR gate; the output end of the first NOR gate is connected to the input end of the third NOR gate; the output end of the third NOR gate is used to output a third intermediate control signal;

[0038] The first input end of the third NAND gate is used to receive the second intermediate control signal; the second input end of the third NAND gate is connected to the output end of the third NOT gate, and is used to receive the third intermediate control signal; the output end of the third NAND gate is connected to the input end of the second delay unit and the first input end of the second NOR gate; the output end of the second delay unit is connected to the second input end of the second NOR gate; the output end of the second NOR gate is connected to the input end of the fourth NOT gate; the output end of the fourth NOT gate is used to output the fourth intermediate control signal;

[0039] The input end of the fifth NOT gate is used to receive the third intermediate control signal, and the output end of the fifth NOT gate is used to output the first target control signal;

[0040] The input end of the sixth NOT gate is used to receive the fourth intermediate control signal, and the output end of the sixth NOT gate is used to output the second target control signal.

[0041] In some embodiments, the working mode of the first power supply includes an ET mode or an APT mode; the working mode of the third power supply includes an ET mode or an APT mode; wherein the working modes of the first power supply and the third power supply are different.

[0042] A high-side switch circuit provided by an embodiment of the present disclosure includes: a first power supply, a first switch transistor and a drive circuit, wherein the first end of the first switch transistor is connected to the first power supply, the second end of the first switch transistor is connected to the load circuit, and the gate end and the second end of the first switch transistor are both connected to the drive circuit; wherein: the first power supply is used to provide a first voltage to the first switch transistor; the drive circuit is used to receive a second voltage, and perform a lifting process on the second voltage, and after obtaining a bias voltage, control whether to turn on the first switch transistor according to the bias voltage; wherein the lifting process makes the difference between the voltage at the gate end of the first switch transistor and the voltage at the second end of the first switch transistor greater than a preset difference; when the first switch transistor is turned on, the first switch transistor transmits the first voltage to the load circuit. In this way, since the drive circuit lifts the received second voltage, the gate voltage of the first switch transistor is higher, so that the first switch transistor can use a small NMOS tube with stable switch resistance as a high-side switch, thereby not only reducing the area of ​​the high-side switch circuit, but also making the switch resistance stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0044] Figure 1 A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 1 ;

[0045] Figure 2 A schematic diagram of the voltage waveform of the VCC port under the ET mode and APT provided in the embodiment of the present disclosure;

[0046] Figure 3 A schematic diagram of the structure of a load circuit provided in an embodiment of the present disclosure;

[0047] Figure 4 A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 2 ;

[0048] Figure 5 A schematic diagram of the structure of the high-side switch circuit provided in the embodiment of the present disclosure Figure 3 ;

[0049] Figure 6 A timing diagram of a dead time control circuit provided in an embodiment of the present disclosure;

[0050] Figure 7 A schematic diagram of the dead time control circuit provided in the embodiment of the present disclosure Figure 1 ;

[0051] Figure 8 A schematic diagram of the dead time control circuit provided in the embodiment of the present disclosure Figure 2 ;

[0052] Fig. 9 A schematic diagram of the structure of the charge pump circuit provided in the embodiment of the present disclosure Figure 1 ;

[0053] Fig.10 A schematic diagram of the structure of the charge pump circuit provided in the embodiment of the present disclosure Figure 2 ;

[0054] Fig.11 A schematic diagram of the structure of the charge pump circuit provided in the embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0055] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0056] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0057] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0058] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0059] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] At present, MOS high-side switches are widely used in many fields such as automobiles, industry, and mobile devices due to their low loss, easy drive, high reliability, and near-ideal switching characteristics, and cover the control and protection of currents within tens of amperes. However, for high-frequency application environments (GHz level), due to parasitic resistance and capacitance and coupling crosstalk, the control and protection of high-side switches are complex, and the industry generally uses PMOS tubes (i.e. MPS) as high-side switch devices.

[0061] Furthermore, when the PMOS tube is used as a high-side switch device, it is relatively easy to control the gate terminal voltage to turn the PMOS tube on or off. However, there are two disadvantages of using the PMOS tube as a high-side switch device: first, the carrier mobility of the PMOS tube is low, and more area is required to achieve the same on-resistance requirement; second, the gate-source voltage of the PMOS tube used as a high-side switch device is greatly affected by power supply fluctuations, so the on-resistance of the switch is unstable. In the related art, N-type MOS tubes (NMOS tubes) are usually not used as high-side switch devices. This is because when the N-type MOS tube is used for high-side switching, there will be two problems due to the source being connected to the load: the source is suspended and the gate voltage is higher than the drain supply voltage.

[0062] Based on this, a high-side switch circuit provided by an embodiment of the present disclosure includes: a first power supply, a first switch transistor and a drive circuit, wherein the first end of the first switch transistor is connected to the first power supply, the second end of the first switch transistor is connected to the load circuit, and the gate end and the second end of the first switch transistor are both connected to the drive circuit; wherein: the first power supply is used to provide a first voltage to the first switch transistor; the drive circuit is used to receive a second voltage, and perform a lifting process on the second voltage to obtain a bias voltage, and turn on the first switch transistor according to the bias voltage; wherein the lifting process makes the difference between the voltage at the gate end of the first switch transistor and the voltage at the second end of the first switch transistor greater than a preset difference. In this way, since the drive circuit lifts the received second voltage, the gate voltage of the first switch transistor is higher, so that the first switch transistor can use a small NMOS tube with stable switch resistance as a high-side switch, thereby not only reducing the area of ​​the high-side switch circuit, but also making the switch resistance stable.

[0063] The high side switch circuit in the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0064] Figure 1 A schematic diagram of the structure of a high-side switch circuit 100 provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the high-side switch circuit 100 includes: a first power supply 110, a first switch transistor 120 and a drive circuit 130, wherein the first end of the first switch transistor 120 is connected to the first power supply 110, the second end of the first switch transistor 120 is connected to the load circuit 140, and the gate end of the first switch transistor 120 is connected to the drive circuit 130; wherein:

[0065] A first power supply 110, configured to provide a first voltage to the first switch transistor 120;

[0066] The driving circuit 130 is used to receive the second voltage, and raise the second voltage to obtain a bias voltage, and turn on the first switch transistor 120 according to the bias voltage; wherein the raising process makes the difference between the voltage at the gate terminal of the first switch transistor 120 and the voltage at the second terminal of the first switch transistor 120 greater than a preset difference; when the first switch transistor 120 is turned on, the first switch transistor 120 transmits the first voltage to the load circuit 140.

[0067] Here, the first power supply 110 is used to output a first voltage, and the first voltage may be a voltage for supplying power to the load circuit 140. The first voltage may be VCC_PS1 ( Figure 1 The second voltage may be the output voltage of the voltage stabilizing circuit, and the second voltage may be represented by V2. In other embodiments, the first voltage and the second voltage may also be other voltages, or may be provided by other power supply circuits.

[0068] It should be noted that the first voltage can be a fixed voltage or a variable voltage. The first power supply 110 supplies power and operates in either of two modes: envelope tracking mode (ET mode) and average power tracking mode (Average Power Tracking mode, APT mode); the voltage waveform diagram of the first voltage in the ET mode and the APT mode is shown in FIG. Figure 2 shown.

[0069] In addition, the structural diagram of the load circuit 140 is as follows: Figure 3 As shown, the load circuit 140 may include a power amplifier 141 (Power Amplifier, PA). The first end of the power amplifier 141 is connected to the second end of the first switch transistor 120 through a port 142; the second end of the power amplifier 141 is grounded; the input end of the power amplifier 141 is used to receive a radio frequency input signal RF_in; and the output end of the power amplifier 141 is used to output a radio frequency output signal RF_out. It should be noted that Figure 3 The load circuit 140 in FIG. 1 is a simplified structural diagram. In fact, the load circuit 140 can be any achievable circuit structure.

[0070] In some embodiments, the first switch transistor 120 is an NMOS transistor. The first switch transistor 120 may also be other N-type field effect transistors, which is not limited here.

[0071] In some embodiments, the driving circuit 130 will not be able to stably drive the second voltage of the first switch transistor to be raised. Here, the second voltage may be, for example, 2.5V, and the preset difference may be, for example, 5V. In actual implementation, the preset difference may also be other values ​​that can turn on the first switch transistor 120, such as 6V, 6.5V, 7V, etc. Since the second voltage is raised by the driving circuit 130, the first switch transistor 120 in the high-side switch circuit 100 may be an NMOS tube (i.e., MNS), so as to turn on the first switch transistor 120 by setting the voltage of the gate terminal of the first switch transistor 120 to be greater than the voltage of the second terminal thereof.

[0072] In the embodiment of the present disclosure, since the driving circuit raises the received second voltage, the gate voltage of the first switching transistor is higher. In this way, the first switching transistor can adopt a small NMOS tube with stable switch resistance as a high-side switch, which not only reduces the area of ​​the high-side switch circuit but also stabilizes the switch resistance.

[0073] Next, please refer to Figure 4 , the high-side switch circuit 100 provided in the embodiment of the present disclosure is further described.

[0074] In some embodiments, please refer to Figure 4 The high-side switch circuit 100 also includes a second power supply 151, and the drive circuit 130 includes: a first charge pump circuit 131 and a second charge pump circuit 132; the first end of the first charge pump circuit 131 is coupled to the second power supply 151, and the second end of the first charge pump circuit 131 is connected to the first end of the second charge pump circuit 132; the second end of the second charge pump circuit 132 is connected to the gate end of the first switching transistor 120; wherein: the second power supply 151 is used to provide a second voltage; the first charge pump circuit 131 is used to raise the second voltage to obtain a preset voltage; the second charge pump circuit 132 is used to further raise the preset voltage to obtain a bias voltage.

[0075] It should be noted that the first end of the first charge pump circuit 131 is coupled to the second power supply 151: it means that the first end of the first charge pump circuit 131 and the second power supply 151 can be directly connected or indirectly connected, that is, "coupling" includes two ways of direct connection or indirect connection. The "coupling" that appears in the subsequent description can be understood with reference to the above explanation.

[0076] In the embodiment of the present disclosure, the value of the second voltage output by the second power supply 151 is within a certain range, here, the certain range may be within 2.5V-3V, and the second voltage may be, for example, 2.5V, 2.6V, etc. In some embodiments, the second power supply 151 may be a voltage stabilizing circuit, wherein the voltage stabilizing circuit is used to convert the battery voltage VBAT to output the second voltage. In other embodiments, the voltage stabilizing circuit may also convert the voltage of other power supplies.

[0077] Here, the first charge pump circuit 131 may be a VX2 CP (twice charge pump), which is used to increase the second voltage by two times to obtain a preset voltage; for example, the second voltage is 3V, and the first charge pump circuit 131 increases the 3V second voltage V2 by two times to output a preset voltage of 6V. The second charge pump circuit 132 may be a QPUMP (gate drive charge pump), which is used to further increase the preset voltage to obtain a bias voltage, for example, 8V. It should be noted that the first charge pump circuit 131 may also increase the second voltage V2 to other voltage values, for example, by 1.5 times.

[0078] It should also be noted that in Figure 4 In the embodiment, the first power supply supplies power to the first switch transistor 120 through the port 111, the load circuit is connected to the first switch transistor 120 through the port 142, and the second power supply 151 is connected to the battery voltage VBAT through the port 152. In addition, the high-side switch circuit 100 further includes a port GND connected to the ground terminal, and some components in the high-side switch circuit 100 are grounded through the port GND.

[0079] In the disclosed embodiment, since the driving circuit performs a lifting process on the received second voltage, the gate voltage of the first switch transistor 120 is stably increased, so that when the first switch transistor 120 is an NMOS transistor, the first switch transistor 120 can be turned on or off; in addition, since the NMOS transistor has a higher carrier mobility characteristic, the high-side switch circuit can have a stronger driving current capability, thereby improving the current density and efficiency.

[0080] In some embodiments, the third terminal of the second charge pump circuit 132 is connected to the second terminal of the first switch transistor 120, and the second charge pump circuit 132 is further used to receive the second terminal voltage of the first switch transistor 120, and raise the preset voltage according to the voltage of the second terminal of the first switch transistor 120 to obtain the bias voltage. In this way, the gate voltage of the first switch transistor 120 can be adjusted according to the voltage feedback of the input terminal of the load circuit, so that the difference between the gate voltage of the first switch transistor 120 and the second terminal voltage is greater than or equal to the preset difference, so as to turn on the first switch transistor 120; it should be noted that the preset voltage and the preset difference are equal in value.

[0081] Specifically, the second charge pump circuit 132 is used to increase the voltage of the second end of the first switching transistor 120 (i.e., the voltage output by the port 142) by a preset difference (i.e., the value of the preset voltage) to obtain a bias voltage, and apply the bias voltage to the gate end of the first switching transistor 120; for example, the voltage of the second end of the first switching transistor 120 is 3V, the second charge pump circuit 132 raises the voltage of 3V by 5V, and the obtained bias voltage is 8V, and the bias voltage of 8V is applied to the gate end of the first switching transistor 120.

[0082] In the disclosed embodiment, since the first switch transistor 120 includes an NMOS tube, the turn-on voltage of the NMOS is usually less than 5V under low voltage conditions, so the preset difference can be greater than 5V, such as 6V, 6.5V, 7V, etc. In other embodiments, it can also be set according to actual conditions, and when the second voltage V2 is small, more charge pump circuits can be set to increase the second voltage.

[0083] In the embodiment of the present disclosure, since a driving circuit (i.e., the second charge pump circuit 132) is connected to the gate terminal and the second terminal of the first switching transistor, the voltages at the gate terminal and the second terminal of the first switching transistor can be controlled by the driving circuit to turn on the first switching transistor.

[0084] In the disclosed embodiment, when the high-side switch circuit 100 is turned off, the second power supply 151, the drive circuit 130 and other circuits are all turned off. When the high-side switch circuit 100 is turned on, the second power supply and the first charge pump circuit 131 in the drive circuit 130 are both kept turned on; at this time, when the high-side switch circuit 100 needs to be turned on, the second charge pump circuit 132 in the drive circuit 130 is turned on to drive the high-side switch circuit 100 to work.

[0085] In this way, the first switch transistor 120 can be turned on or off only by turning on or off the second charge pump circuit 132. That is to say, during the operation of the high-side switch circuit 100, the second power supply 151 and the first charge pump circuit 131 will not cause any delay, thereby improving the response speed of the high-side switch circuit 100.

[0086] In some embodiments, please refer to Figure 4 The high-side switch circuit 100 further includes a first body-end switch circuit 190, wherein a first terminal and a second terminal of the first body-end switch circuit 190 are respectively connected to a gate terminal and a second terminal of the first switch transistor 120, so as to ensure that the first switch transistor 120 is reliably turned on and off.

[0087] In some embodiments, please refer to Figure 5, the high-side switch circuit 100 further includes a second switch transistor 160; the first end of the second switch transistor 160 is used to connect to a third power source (not shown) through a port 170, the second end of the second switch transistor 160 is connected to a load circuit (not shown) through a port 142, and the gate end of the second switch transistor 160 and the second end of the second switch transistor 160 are connected to the drive circuit 130. Wherein: the third power source is used to provide a third voltage to the second switch transistor 160; the drive circuit 130 is also used to perform a lifting process on the second voltage, and after obtaining a bias voltage, control the second switch transistor 160 to turn on according to the bias voltage; wherein the lifting process also makes the difference between the voltage at the gate end of the second switch transistor 160 and the voltage at the second end of the second switch transistor 160 greater than a preset difference; when the second switch transistor 160 is turned on, the second switch transistor 160 transmits the third voltage to the load circuit.

[0088] It should be noted that the load circuit, the first power supply, the second power supply and the switch circuit can also be set on one IC, or part of them and the switch circuit can be set on one IC. In this case, no external interface is required for connection and they can be directly connected.

[0089] In the embodiment of the present disclosure, the third voltage can be represented by VCC_PS2. Please continue to refer to Figure 5 The third power supply supplies power to the load circuit through the port 170 when the second switch transistor 160 is turned on. The third voltage can be a fixed voltage or a variable voltage; the third power supply and the load circuit can be powered and operated in either of the ET and APT modes.

[0090] In some embodiments, the first power supply and the third power supply have different working modes. For example, the working mode of the first power supply is ET mode, and the working mode of the third power supply is APT mode; or, the working mode of the first power supply is APT mode, and the working mode of the third power supply is ET mode. In this way, the power supply mode of the load circuit can be switched by the first switch transistor 120 and the second switch transistor 160, thereby broadening the application scenarios of the high-side switch circuit 100.

[0091] In some embodiments, the structure and function of the second switch transistor 160 are similar to those of the first switch transistor 120 , and are not described in detail herein.

[0092] In some embodiments, the driving circuit 130 also includes a third charge pump circuit 133; the first end of the third charge pump circuit 133 is connected to the second end of the first charge pump circuit 131, the second end of the third charge pump circuit 133 is connected to the gate end of the second switching transistor 160, and the third end of the third charge pump circuit 133 is connected to the second end of the second switching transistor 160; wherein: the structure and function of the third charge pump circuit 133 are similar to those of the second charge pump, and will not be repeated here.

[0093] In some embodiments, please refer to Figure 4 , Figure 5 The high-side switch circuit 100 further includes a logic control circuit 180, which is connected to the second charge pump circuit 132 (see Figure 4 ), or connected to the control terminals of the second charge pump circuit 132 and the third charge pump circuit 133 at the same time (please refer to Figure 5 ). Wherein: the logic control circuit 180 is used to generate a first control signal and transmit the first control signal to the second charge pump circuit 132; when the first control signal is in an enabled state, the second charge pump circuit 132 is turned on and the first switch transistor 120 is turned on; when the first control signal is in a disabled state, the second charge pump circuit 132 is turned off and the first switch transistor 120 is turned off. The logic control circuit 180 is also used to generate a second control signal and transmit the second control signal to the third charge pump circuit 133; when the second control signal is in an enabled state, the third charge pump circuit 133 is turned on and the second switch transistor 160 is turned on; when the second control signal is in a disabled state, the third charge pump circuit 133 is turned off and the second switch transistor 160 is turned off.

[0094] Here, the output signal of the logic control circuit 180 can be represented by CTRL_IN<1:0>, which includes the first control signal CTRL_IN <0> and the second control signal CTRL_IN <1> .

[0095] In some embodiments, the logic control circuit 180 is also used to control the opening and closing of the second power supply 151 and the first charge pump circuit 131 .

[0096] In some embodiments, the logic control circuit 180 is also used to receive the initial control signal output by the port 182, such as Figure 4 , Figure 5 The VCC_Ctrl signal is logically processed by the initial control signal VCC_Ctrl, and generates a first control signal in an enabled state when the initial control signal indicates to turn on the first switch transistor 120; and generates a second control signal in an enabled state when the initial control signal indicates to turn on the second switch transistor 160. Wherein, VCC_Ctrl is a 2-bit signal.

[0097] In some disclosed embodiments, Figure 4 , Figure 5As shown, the initial control signal VCC_Ctrl<1:0> of the logic control circuit 180 has four working states, namely 00, 01, 10, and 11. Specifically, when the initial control signal VCC_Ctrl<1:0>=00, the high-side switch circuit 100 is in the off state as a whole, that is, all circuits in the high-side switch circuit 100 have no static current; when the initial control signal VCC_Ctrl<1:0>=01, the second power supply 151, the first charge pump circuit 131 and the third charge pump circuit 133 are turned on, and the first control signal CTRL_IN <0> In the disabled state, the first switch transistor 120 is turned off, and the second control signal CTRL_IN <1> In the enabled state, the second switch transistor 160 is turned on. At this time, the third power supply supplies power to the load circuit 140. When the initial control signal VCC_Ctrl<1:0>=10, the first control signal CTRL_IN <0> In the enabled state, the first switch transistor is turned on, and the second control signal CTRL_IN <1> In the disabled state, the second switch transistor 160 is turned off. At this time, the first power supply 110 supplies power to the load circuit through the first switch transistor 120. When the initial control signal VCC_Ctrl<1:0>=11, the first control signal CTRL_IN <0> and the second control signal CTRL_IN <1> The first switch transistor 120 and the second switch transistor 160 are both turned off, but the second power supply 151 and the first charge pump circuit 131 remain turned on. It should be noted that when the high-side switch circuit does not have the second switch transistor 160, the control signal related thereto is omitted.

[0098] In the embodiment of the present disclosure, the high-side switch circuit 100 can realize the opening or closing of the second charge pump circuit 132 and the third charge pump circuit 133 under the control of the input first control signal and the second control signal, thereby switching the first power supply 110 and the third power supply, so that the load circuit can operate in APT mode or ET mode; thereby broadening the application scenarios of the high-side switch circuit 100.

[0099] In the embodiment of the present disclosure, in order to avoid the problem that the first switch transistor 120 and the second switch transistor 160 are turned on at the same time during the operation of the high-side switch circuit 100, resulting in excessive transient current and burning the load circuit. In some embodiments, please continue to refer to Figure 5The high-side switch circuit 100 further includes: a dead time control circuit 181; a first output terminal of the dead time control circuit 181 is connected to the control terminal of the second charge pump circuit 132, and a second output terminal of the dead time control circuit 181 is connected to the control terminal of the third charge pump circuit 133; wherein: the dead time control circuit 181 is used to control the first control signal CTRL_IN <0> and / or the second control signal CTRL_IN <1> After the delay processing is performed, the third charge pump circuit 133 is delayed to be turned on after the second charge pump circuit 132 is turned off, or the second charge pump circuit 132 is delayed to be turned on after the third charge pump circuit 133 is turned off.

[0100] Here, please continue to refer to Figure 5 , the first control signal CTRL_IN after delay processing <0> For the first target control signal, use CTRL_OUT <0> Indicates that the second control signal CTRL_IN after delay processing <1> For the second target control signal, use CTRL_OUT <1> express.

[0101] Specifically, please refer to Figure 6 , when the first control signal CTRL_IN <0> When the first target control signal CTRL_OUT changes from high level to low level, <0> Then it becomes a low level; when the first control signal CTRL_IN <0> When the second control signal CTRL_IN changes from low level to high level, <1> is high, then the second control signal CTRL_IN <1> After a preset time, the first target control signal CTRL_OUT changes from a high level to a low level. <0> From low level to high level; when the first control signal CTRL_IN <0> When the second control signal CTRL_IN changes from low level to high level, <1> is low level, then after a preset time, the first target control signal CTRL_OUT <0> From low level to high level. Similarly, the second target control signal CTRL_OUT <1> The timing of the first target control signal CTRL_OUT <0> Similar, no further description is given here.

[0102] In some embodiments, when the first control signal CTRL_IN <0> When the second control signal CTRL_IN changes from low level to high level, <1> is low level, at this time the first target control signal CTRL_OUT <0> It is also possible to directly change from a low level to a high level without a preset time.

[0103] It should be noted that the first control signal CTRL_IN <0> When it is high, it is in the enabled state, and the first control signal CTRL_IN <0> When it is low level, it is in a disabled state, and the same is true for the second control signal. The preset time is the dead time (DeadTime, DT).

[0104] In some embodiments, please refer to Figures 6 to 8 The dead time control circuit 181 includes a logic processing circuit 181a and a delay processing circuit 181b; the logic processing circuit 181a is used to receive the first control signal CTRL_IN <0> and the second control signal CTRL_IN <1> , and according to the first control signal CTRL_IN <0> and the second control signal CTRL_IN <1> Perform logic processing to generate a first intermediate control signal and a second intermediate control signal; wherein, when one of the first intermediate control signal and the second intermediate control signal changes from the second level state to the first level state, after a preset time interval, the first target control signal CTRL_OUT <0> and the second target control signal CTRL_OUT <1> One of the state changes from the second level to the first level.

[0105] Here, the first intermediate control signal can be CTRL_IN1 <0> Indicates that the second intermediate control signal can be used with CTRL_IN1 <1> express.

[0106] It should be noted that the first level state is 1 (logic high level), and the second level state is 0 (logic low level); the first target control signal CTRL_OUT <0> The first level state is the first target control signal CTRL_OUT <0> In the enabled state, the first target control signal CTRL_OUT <0> The second level state is the first target control signal CTRL_OUT <0> In the non-enabled state, the “first level state” and “second level state” that appear in the subsequent specification can be understood with reference to the above explanation.

[0107] Please continue to refer to Figures 6 to 8 , the delay processing circuit 181b is used to receive the first intermediate control signal CTRL_IN1 <0> and the second intermediate control signal CTRL_IN1 <1> , and according to the first control signal CTRL_IN <0> and the second control signal CTRL_IN <1> , generating the first target control signal CTRL_OUT <0> and the second target control signal CTRL_OUT <1> ; For details, please continue to refer to Figure 6 , in the first intermediate control signal CTRL_IN1 <0> When the second level state changes to the first level state, after a preset time (DT), the first target control signal CTRL_OUT <0> The second level state is changed to the first level state, and other level states remain unchanged; in the second intermediate control signal CTRL_IN1 <1> When the second level state changes to the first level state, after a preset time (DT), the second target control signal CTRL_OUT <1> The second level state is changed to the first level state, and other level states remain unchanged.

[0108] In some embodiments, please refer to Figure 6 and Figure 8 The logic processing circuit 181a includes a first NAND gate 10, a first AND gate 11, and a second AND gate 12; the first input terminal of the first NAND gate 10 and the first input terminal of the first AND gate 11 are both used to receive the first control signal CTRL_IN <0> The second input terminal of the first NAND gate 10 and the second input terminal of the second AND gate 12 are both used to receive the second control signal CTRL_IN <1> The output end of the first NAND gate 10 is connected to the second input end of the first AND gate 11 and the first input end of the second AND gate 12; the output end of the first AND gate 11 is used to output the first intermediate control signal CTRL_IN1 <0> The output terminal of the second AND gate 12 is used to output the second intermediate control signal CTRL_IN1 <1> .

[0109] In some embodiments, please refer to Figure 6 and Figure 8 The delay processing circuit 181b includes a cross-coupling circuit 1811, a first inverting circuit 1812 and a second inverting circuit 1813; the cross-coupling circuit 1811 is used to receive the first intermediate control signal CTRL_IN1 <0> , the second intermediate control signal CTRL_IN1 <1> , a third intermediate control signal and a fourth intermediate control signal, and according to the first intermediate control signal CTRL_IN1 <0> , the second intermediate control signal CTRL_IN1 <1> , the third intermediate control signal and the fourth intermediate control signal are cross-coupled and processed, and the third intermediate control signal and the fourth intermediate control signal are output; the first inverting circuit 1812 is used to receive the third intermediate control signal, invert the third intermediate control signal, and generate the first target control signal CTRL_OUT <0> The second inverting circuit 1813 is used to receive the fourth intermediate control signal, invert the fourth intermediate control signal, and generate a second target control signal CTRL_OUT <1> .

[0110] Here, the third intermediate control signal can be used with CTRL_IN2 <0> Indicates that the fourth intermediate control signal can be used with CTRL_IN2 <1> express.

[0111] In some embodiments, please refer to Figure 6 and Figure 8The cross-coupling circuit 1811 includes a first delay circuit and a second delay circuit; the first delay circuit is used to receive the first intermediate control signal CTRL_IN1 <0> and the fourth intermediate control signal CTRL_IN2 <1> , and the first intermediate control signal CTRL_IN1 <0> and the fourth intermediate control signal CTRL_IN2 <1> Perform logic processing and delay processing to generate the third intermediate control signal CTRL_IN2 <0> ; The second delay circuit is used to receive the second intermediate control signal CTRL_IN1 <1> and the third intermediate control signal CTRL_IN2 <0> , and the second intermediate control signal CTRL_IN1 <1> and the third intermediate control signal CTRL_IN2 <0> Perform logic processing and delay processing to generate the fourth intermediate control signal CTRL_IN2 <1> .

[0112] In some embodiments, please refer to Figure 6 and Figure 8 The first delay circuit includes a second NAND gate 13, a first delay unit 15, a first NOR gate 17 and a third NOR gate 19; the second delay circuit includes a third NAND gate 14, a second delay unit 16, a second NOR gate 18 and a fourth NOR gate 20; the first input end of the second NAND gate 13 is used to receive the first intermediate control signal CTRL_IN1 <0> The second input terminal of the second NAND gate 13 is connected to the output terminal of the fourth NOT gate 20 for receiving the fourth intermediate control signal CTRL_IN2 <1> The output end of the second NAND gate 13 is connected to the input end of the first delay unit 15 and the first input end of the first NOR gate 17; the output end of the first delay unit 15 is connected to the second input end of the first NOR gate 17; the output end of the first NOR gate 17 is connected to the input end of the third NOR gate 19; the output end of the third NOR gate 19 is used to output the third intermediate control signal CTRL_IN2 <0> The first input terminal of the third NAND gate 14 is used to receive the second intermediate control signal CTRL_IN1 <1> The second input terminal of the third NAND gate 14 is connected to the output terminal of the third NOT gate 19 for receiving the third intermediate control signal CTRL_IN2 <0> The output end of the third NAND gate 14 is connected to the input end of the second delay unit 16 and the first input end of the second NOR gate 18; the output end of the second delay unit 16 is connected to the second input end of the second NOR gate 18; the output end of the second NOR gate 18 is connected to the input end of the fourth NOR gate 20; the output end of the fourth NOR gate 20 is used to output the fourth intermediate control signal CTRL_IN2 <1> .

[0113] In some embodiments, please refer to Figure 6 and Figure 8 The first delay unit 15 and the second delay unit 16 are both used to delay the signal input thereto by a preset time (ie, the dead time DT).

[0114] It should be noted that the preset time can be any achievable time, and the present disclosure is not limited to this.

[0115] In some embodiments, please refer to Figure 6 and Figure 8 The first inverting circuit 1812 includes a fifth inverter 21, and the second inverting circuit 1813 includes a sixth inverter 22; the input end of the fifth inverter 21 is used to receive the third intermediate control signal CTRL_IN2 <0> The output terminal of the fifth NOT gate 21 is used to output the first target control signal CTRL_OUT <0> The input terminal of the sixth NOT gate 22 is used to receive the fourth intermediate control signal CTRL_IN2 <1> The output terminal of the sixth NOT gate 22 is used to output the second target control signal CTRL_OUT <1> .

[0116] In some embodiments, in combination Figure 5 and Figure 8 , the first target control signal CTRL_OUT <0> coupled to the first switch transistor 120 (ie, connected to the first switch transistor via the second charge pump circuit 132), the second target control signal CTRL_OUT <1> coupled to the second switch transistor 160 (ie, connected to the second switch transistor 160 through the third charge pump circuit 133); in the first target control signal CTRL_OUT <0> When the first level state is reached, the first switch transistor 120 is turned on; when the first target control signal CTRL_OUT <0> When the first switch transistor 120 is in the second level state, the second target control signal CTRL_OUT is turned off; <1> When the second target control signal CTRL_OUT is in the first level state, the second switch transistor 160 is turned on; <1> When in the second level state, the second switch transistor 160 is turned off.

[0117] In the disclosed embodiment, since the high-side switch circuit 100 includes a first switch transistor 120 and a second switch transistor 160, during the operation of the high-side switch circuit 100, the first switch transistor 120 and the second switch transistor 160 are turned on at the same time, which may cause the transient current of the input load circuit 140 to be too large and burn the chip. Therefore, by setting a dead time control circuit 181, the first control signal and / or the second control signal are delayed and transmitted to the second charge pump circuit 132 and the third charge pump circuit 133 respectively, thereby avoiding the first switch transistor 120 and the second switch transistor 160 from being turned on at the same time, thereby making the high-side switch circuit 100 more reliable.

[0118] In some embodiments, please refer to Figure 5The high-side switch circuit 100 further includes a second body-end switch circuit 191, a first end and a second end of the second body-end switch circuit 191 are respectively connected to the gate end and the second end of the second switch transistor 160. The body end of the second switch transistor 160 is used to control the body end of the second switch transistor 160 to ensure that the second switch transistor 160 is reliably turned on and off.

[0119] It should be noted that the first switch transistor 120 in the embodiment of the present disclosure can be a depletion-type NMOS tube or an enhancement-type NMOS tube, and the second switch transistor 160 can be a depletion-type NMOS tube or an enhancement-type NMOS tube; among them, the manufacturing process of the depletion-type NMOS tube is simple; the enhancement-type NMOS tube has a fast switching speed and a stronger driving capability, and can be selected as needed during implementation.

[0120] The embodiments of the present disclosure provide Figure 5 The high-side switch circuit shown is similar to the above Figure 4 The high-side switch circuit in the embodiment is similar. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0121] In the embodiment of the present disclosure, since the driving circuit performs two lifting processes on the received second voltage, the gate voltages of the first switch transistor and the second switch transistor are relatively high, so that the first switch transistor and the second switch transistor can use NMOS tubes as high-side switches, which can not only reduce the area of ​​the high-side switch circuit, but also stabilize the switch resistance. In addition, the high-side switch circuit can realize the opening or closing of the second charge pump circuit 132 and the third charge pump circuit 133 under the control of the input first control signal and the second control signal, thereby switching the first power supply 110 and the third power supply, so that the high-side switch circuit 100 can work in APT mode or ET mode; thereby broadening the application scenario of the high-side switch circuit 100.

[0122] In some embodiments, such as Figure 5 As shown, multiple functional modules, a second power supply (i.e., a low voltage difference linear regulator), a double charge pump (VX2 CP, i.e., a first charge pump circuit), a logic control circuit (Logic), a dead time control circuit (DeadTime Control), a gate drive charge pump (QPUMP1 / QPUMP2, i.e., a second charge pump circuit / a third charge pump circuit), and a body control (Body control) are integrated into a chip, and connected to other modules or chips through ports 152, 111, 142, 170, 182 and GND.

[0123] In addition, the embodiment of the present disclosure further provides a charge pump circuit 200. The second charge pump circuit 132 and / or the third charge pump circuit 133 in the above embodiments can adopt the structure of the charge pump circuit 200 in the following embodiments. Next, the charge pump circuit 200 is taken as the second charge pump circuit 132 as an example to introduce the charge pump circuit in detail. The structure of the third charge pump circuit 133 is similar to that of the second charge pump circuit 132, and will not be repeated here.

[0124] Fig. 9 A charge pump circuit 200 is provided in an embodiment of the present disclosure, wherein the first end of the charge pump circuit 200 is connected to the gate end of the first switch transistor 120, the second end of the charge pump circuit 200 and the second end of the first switch transistor 120 are both connected to the input end of the load circuit 140, and the first end of the first switch transistor 120 is connected to the first power supply 110; the voltage at the gate end of the first switch transistor 120 is the gate voltage, and the voltage at the input end of the load circuit 140 is the load voltage, wherein: the charge pump circuit 200 is used to adjust the gate voltage according to the load voltage feedback, so that the difference between the load voltage and the gate voltage is a preset voltage, so as to turn on the first switch transistor 120, wherein the preset voltage is greater than or equal to the turn-on voltage of the first transistor. Here, the gate voltage is the bias voltage of the first switch transistor.

[0125] In the embodiment of the present disclosure, the charge pump circuit 200 obtains the load voltage, and after raising the load voltage by at least a preset voltage, outputs it to the gate terminal of the first switching transistor 120; so that the difference between the voltage at the gate terminal of the first switching transistor 120 and the voltage at the second terminal of the first switching transistor 120 (i.e., the load voltage) is greater than or equal to the turn-on voltage of the first transistor, where the preset voltage can be 5V.

[0126] Next, please refer to Fig.10 and Fig.11 , the charge pump circuit 200 provided in the embodiment of the present disclosure is further described.

[0127] In some embodiments, please refer to Fig.10, the charge pump circuit 200 may include a first capacitor 210 and a second capacitor 220. The first plate of the first capacitor 210 is coupled to the fourth power supply 230, the second plate of the first capacitor 210 is coupled to the gate terminal of the first switch transistor 120, the first plate of the second capacitor 220 is coupled to the fifth power supply 240, and the second plate of the second capacitor 220 is coupled to the input terminal of the load circuit (i.e., port 142). In addition, the first plate of the first capacitor 210 is coupled to the sixth power supply 250, the second plate of the first capacitor 210 is coupled to the input terminal of the load circuit 140, the first plate of the second capacitor 220 is coupled to the seventh power supply 260, and the second plate of the second capacitor 220 is coupled to the gate terminal of the first switch transistor 120. The fourth power supply voltage is greater than the sixth power supply voltage, and the seventh power supply voltage is greater than the fifth power supply voltage.

[0128] It should be noted that the voltage output by the fourth power supply 230 and / or the voltage output by the seventh power supply 260 may be the voltage output by the first charge pump circuit 131 in the above embodiment.

[0129] Next, the operating principle of the charge pump circuit is explained.

[0130] The charge pump circuit can turn on the first switch transistor 120 through the first capacitor 210 and the second capacitor 220. When the first switch transistor 120 is turned on through the first capacitor 210, please continue to refer to Fig.10 , the first capacitor 210 is used to charge the second plate of the first capacitor 210 to the load voltage, and then boost the second plate of the first capacitor to a preset voltage through the fourth power supply 230 to obtain a gate voltage, and apply the gate voltage to the gate terminal of the first switch transistor. Specifically, when the first capacitor 210 is initialized, the first plate of the first capacitor 210 is coupled to the sixth power supply 250 so that the first plate voltage is the sixth voltage, and the second plate of the first capacitor 210 is coupled to the load circuit so that the second plate is the load voltage; when the first capacitor 210 is working, the first plate of the first capacitor 210 is coupled to the fourth power supply 230 so that the first plate voltage changes from the sixth voltage to the fourth voltage, and the second plate of the first capacitor 210 is coupled to the gate terminal of the first switch transistor 120 so that the second plate voltage changes from the load voltage to the gate voltage. At this time, since the voltage difference of the two plates changes in the same way, both are the difference between the fourth voltage and the sixth voltage, that is, the preset voltage, the voltage difference between the gate voltage and the load voltage is maintained at the preset voltage.

[0131] When the first switch transistor 120 is turned on by the second capacitor 220, please continue to refer to Fig.10, the second capacitor 220 is used to charge the second plate of the second capacitor 220 to the load voltage, and then boost the second plate of the second capacitor 220 to a preset voltage through the seventh power supply 260 to obtain a gate voltage, and apply the gate voltage to the gate terminal of the first switch transistor 120. Specifically, when the second capacitor 220 is initialized, the first plate of the second capacitor 220 is coupled to the fifth power supply 240 so that the first plate voltage is the fifth voltage, and the second plate of the second capacitor 220 is coupled to the input terminal of the load circuit so that the second plate is the load voltage; when the second capacitor 220 is working, the first plate of the second capacitor 220 is coupled to the seventh power supply 260 so that the first plate voltage changes from the fifth voltage to the seventh voltage, and the second plate of the second capacitor 220 is coupled to the gate terminal of the first switch transistor 120 so that the second plate voltage changes from the load voltage to the gate voltage. At this time, since the voltage difference of the two plates changes in the same way, both are the difference between the seventh voltage and the fifth voltage, that is, the preset voltage, the voltage difference between the gate voltage and the load voltage is maintained at the preset voltage.

[0132] The first boost capacitor and the second capacitor can work alternately. Specifically, when the first capacitor 210 is in the initial state, the second capacitor 220 is in the working state; when the first capacitor 210 is in the working state, the second capacitor 220 is in the initial state. In this way, not only the voltage difference between the gate terminal and the second terminal of the first switch transistor 120 is relatively stable, but also the charge pump circuit 200 can be prevented from overheating and affecting the circuit performance.

[0133] The charge pump circuit can adjust the gate voltage according to the load voltage feedback through the first capacitor 210 and the second capacitor 220, so that the difference between the load voltage and the gate voltage remains greater than or equal to the turn-on voltage of the switching transistor, thereby keeping the first switching transistor 120 turned on.

[0134] It should be noted that, in the embodiment of the present disclosure, only the first capacitor 210 and its corresponding connection circuit, or the second capacitor 220 and its corresponding connection circuit can be set; thus, the difference between the load voltage and the gate voltage can be adjusted only by the first capacitor 210 or the second capacitor 220, thereby reducing the area of ​​the charge pump circuit 200. For example, when only the first capacitor 210 and its corresponding connection circuit are set, the first plate of the first capacitor 210 is coupled to the fourth power supply 230 and the sixth power supply 250, and the second plate of the first capacitor 210 is coupled to the gate terminal of the first switch transistor 120 and the input terminal of the load circuit (i.e., port 142). For another example, when only the second capacitor 220 and its corresponding connection circuit are set, the first plate of the second capacitor 220 is coupled to the fifth power supply 240 and the seventh power supply 260, and the second plate of the second capacitor 220 is coupled to the input terminal of the load circuit and the gate terminal of the first switch transistor 120.

[0135] It should also be noted that Fig.10 and Fig.11 The first power supply and the load circuit are not shown in FIG. For the connection relationship between the first power supply and the load circuit, please refer to Fig. 9 To understand.

[0136] In some embodiments, the voltages of the fourth power supply 230 and the seventh power supply 260 are the same or different; the voltages of the fifth power supply 240 and the sixth power supply 250 are the same or different. Furthermore, the difference between the fourth voltage and the sixth voltage, and the difference between the seventh voltage and the fifth voltage, can be the same or different.

[0137] For example, the voltages of the fourth voltage and the seventh voltage may both be 5V, and the voltages of the sixth voltage and the fifth voltage may both be ground voltage, i.e., 0V. For another example, the voltage of the fourth voltage is 5V, and the voltage of the sixth voltage is 0V; the voltage of the seventh voltage is 8V, and the voltage of the fifth voltage is 2V. In this way, the preset voltage of the first capacitor 210 to turn on the first switch transistor is 5V, and the preset voltage of the second capacitor 220 to turn on the first switch transistor is 6V. In addition, when the voltage difference between the fourth voltage and the sixth voltage is equal to the voltage difference between the seventh voltage and the fifth voltage, the voltage difference between the gate terminal and the second terminal of the first switch transistor 120 is relatively stable.

[0138] In some embodiments, please refer to Fig.10 The charge pump circuit 200 also includes: a first switch circuit 271 and a second switch circuit 272; a first end of the first switch circuit 271 is connected to the second plate of the first capacitor 210, a second end of the first switch circuit 271 is connected to the second plate of the second capacitor 220, and a third end of the first switch circuit 271 is coupled to the gate terminal of the first switch transistor 120; a first end of the second switch circuit 272 is connected to the second plate of the first capacitor 210, a second end of the second switch circuit 272 is connected to the second plate of the second capacitor 220, and a third end of the second switch circuit 272 is coupled to the input end of the load circuit.

[0139] In some embodiments, the second switching circuit 272 is used to connect the second plate of the first capacitor 210 or the second plate of the second capacitor 220 to the input end of the load circuit during initialization; the first switching circuit 271 is used to connect the second plate of the first capacitor 210 or the second plate of the second capacitor 220 to the gate end of the first switching transistor 120 during operation.

[0140] In some embodiments, please refer to Fig.10The charge pump circuit 200 also includes: a third switch circuit 273 and a fourth switch circuit 274; a first end of the third switch circuit 273 is connected to the first plate of the first capacitor 210, a second end of the third switch circuit 273 is connected to the fourth power supply 230, and a third end of the third switch circuit 273 is connected to the sixth power supply 250; a first end of the fourth switch circuit 274 is connected to the first plate of the second capacitor 220, a second end of the fourth switch circuit 274 is connected to the seventh power supply 260, and a third end of the fourth switch circuit 274 is connected to the fifth power supply 240.

[0141] In some embodiments, the third switching circuit 273 is used to connect the sixth power supply 250 to the first plate of the first capacitor 210 when the first capacitor 210 is initialized; and is also used to connect the fourth power supply 230 to the first plate of the first capacitor 210 when the first capacitor 210 is in a working state; the fourth switching circuit 274 is used to connect the fifth power supply 240 to the first plate of the second capacitor 220 when the second capacitor 220 is initialized; and is also used to connect the seventh power supply 260 to the first plate of the second capacitor 220 when the second capacitor 220 is in a working state.

[0142] It should be noted that when the voltage pump circuit has only one capacitor, the related structure of the other capacitor in the above embodiment is omitted and will not be described in detail here.

[0143] In some embodiments, please refer to Fig.11 The third switch circuit 273 includes a first transistor MP1 and a second transistor MN1; the fourth switch circuit 274 includes a third transistor MP2 and a fourth transistor MN2. The first ends of the first transistor MP1 and the second transistor MN1 are connected to the fourth power supply 230 and the sixth power supply 250 respectively; the second ends of the first transistor MP1 and the second transistor MN1 are connected to the first plate of the first capacitor 210; the first ends of the third transistor MP2 and the fourth transistor MN2 are connected to the seventh power supply 260 and the fifth power supply 240 respectively; the second ends of the third transistor MP2 and the fourth transistor MN2 are connected to the first plate of the second capacitor 220.

[0144] The gate terminals of the transistors in the third switch circuit 273 and the fourth switch circuit 274 are connected to the control circuit. The third switch circuit 273 obtains the first clock signal and the second clock signal, and the fourth switch circuit 274 obtains the third clock signal and the fourth clock signal. When the first capacitor 210 and the second capacitor 220 are initialized, the four clock signals are all in the first level state; when in the working state, the four clock signals are all in the second level state. Fig.11, the first clock signal can be represented by CLK_P1, the second clock signal can be represented by CLK_N1, the third clock signal can be represented by CLK_P2, and the fourth clock signal can be represented by CLK_N2.

[0145] In some embodiments, please refer to Fig.11 , the first switch circuit 271 and the second switch circuit 272 are both cross-coupled circuits, the first switch circuit 271 includes a fifth transistor MP3 and a sixth transistor MP4, and the second switch circuit 272 includes a seventh transistor MN3 and an eighth transistor MN4. The first end of the fifth transistor MP3 and the first end of the sixth transistor MP4 are both coupled to the gate end of the first switch transistor 120, the gate end of the fifth transistor MP3 and the second end of the sixth transistor MP4 are both connected to the second plate of the second capacitor 220, and the second end of the fifth transistor MP3 and the gate end of the sixth transistor MP4 are both connected to the second plate of the first capacitor 210; the first end of the seventh transistor MN3 and the gate end of the eighth transistor MN4 are both connected to the second plate of the first capacitor 210, the gate end of the seventh transistor MN3 and the first end of the eighth transistor MN4 are both connected to the second plate of the second capacitor 220, and the second end of the seventh transistor MN3 and the second end of the eighth transistor MN4 are both coupled to the input end of the load circuit.

[0146] In some embodiments, please refer to Fig.11 The charge pump circuit 200 also includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the gate end of the first switch transistor 120, and the other end of the first resistor R1 is connected to the first end of the fifth transistor MP3 and the first end of the sixth transistor MP4; one end of the second resistor R2 is connected to the second end of the seventh transistor MN3 and the second end of the eighth transistor MN4, and the other end of the second resistor R2 is connected to the input end of the load circuit.

[0147] In this disclosure, please continue to refer to Fig.11 The charge pump circuit 200 further includes a third capacitor C3; one end of the third capacitor C3 is connected to the second end of the seventh transistor MN3, the second end of the eighth transistor MN4 and one end of the second resistor R2, and the other end of the third capacitor C3 is connected to the ground.

[0148] In the disclosed embodiment, the first resistor R1, the second resistor R2 and the third capacitor C3 are used for filtering, so that the output signal of the charge pump circuit 200 is more stable.

[0149] In some embodiments, the second transistor MN1, the fourth transistor MN2, the seventh transistor MN3 and the eighth transistor MN4 are NMOS transistors; the first transistor MP1, the third transistor MP2, the fifth transistor MP3 and the sixth transistor MP4 are PMOS transistors.

[0150] Next, take the fourth power supply 230 and the seventh power supply 260 as an example, the voltages are both set to 5V, and the sixth power supply 250 and the fifth power supply 240 are both set to 0V. Fig.11 The circuit shown provides a detailed description of the operation of the charge pump circuit 200 .

[0151] like Fig.11 In the solid arc path, within half a clock cycle, the first transistor MP1, the first capacitor 210 and the fifth transistor MP3 form a path, and the fourth transistor MN2, the second capacitor 220 and the eighth transistor MN4 form a path. Fig.11 In the dotted arc path, in the other half cycle, the second transistor MN1, the first capacitor 210 and the seventh transistor MN3 form a path, and the third transistor MP2, the second capacitor 220 and the sixth transistor MP4 form a path; in this way, the voltage difference between the gate and source voltages of the first switch transistor 120 is stabilized at 5V, thereby realizing the high-side turning on of the first switch transistor 120.

[0152] In other embodiments, the fourth power supply 230 and the seventh power supply 260 can be set to other voltages, for example, 6V, 4V, etc.; the sixth power supply 250 and the fifth power supply 240 can also be set to other voltages, for example, 1V, 1.5V, 2V, etc.

[0153] In some embodiments, please refer to Fig.11 The charge pump circuit 200 also includes a fourth capacitor 281 and a fifth capacitor 282; the fourth capacitor 281 is connected between the first end of the first switch transistor 120 and the gate end of the first switch transistor 120; the fifth capacitor 282 is connected between the second end of the first switch transistor 120 and the gate end of the first switch transistor 120; wherein: the fourth capacitor 281 includes a parasitic capacitor or a metal plate capacitor; the fifth capacitor 282 includes a parasitic capacitor or a metal plate capacitor.

[0154] In this way, the coupling characteristics of the fourth capacitor 281 and the fifth capacitor 282 can be used to realize the ET / APT dual-mode automatic switching and the wide-band ET mode operation. Fig. 9) is a changing value, since the first switching transistor 120 is not an ideal switch, the parasitic capacitance (the fourth capacitor 281 and the fifth capacitor 282) can be used to make the load voltage change better with the first power supply 110; when the capacity of the parasitic capacitance (the fourth capacitor 281 and the fifth capacitor 282) is not large enough, it can also be achieved by adding additional capacitance, that is, setting the fourth capacitor 281 and / or the fifth capacitor 282 as a metal plate capacitor.

[0155] In order to improve the working efficiency of the chip, the width-to-length ratio of the first switch transistor 120 is relatively large, so that the drain-source voltage of the first switch transistor 120 is substantially equal. In the APT mode, the voltage of the first power supply 110 is substantially maintained stable. In the ET mode, in order to improve the working efficiency of the load circuit, the voltage of the first power supply 110 changes within a certain frequency and amplitude range. Under the action of the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the first switch transistor 120 (i.e., the fourth capacitor 281 and the fifth capacitor 282), the gate-source voltage difference of the first switch transistor 120 is always maintained stable, and the final load voltage changes synchronously with the voltage of the first power supply 110, and no additional distortion is introduced to the load circuit.

[0156] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0157] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0158] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A high-side switch circuit, characterized in that: The high-side switch circuit comprises: a first power supply, a first switch transistor and a drive circuit, wherein the first end of the first switch transistor is connected to the first power supply, the second end of the first switch transistor is connected to the load circuit, and the gate end and the second end of the first switch transistor are both connected to the drive circuit; wherein: The first power supply is used to provide a first voltage to the first switching transistor; The driving circuit is used to receive a second voltage, and to perform a boost processing on the second voltage. After obtaining a bias voltage, whether to turn on the first switching transistor is controlled according to the bias voltage; wherein the boost processing makes the difference between the voltage at the gate terminal of the first switching transistor and the voltage at the second terminal of the first switching transistor greater than a preset difference; when the first switching transistor is turned on, the first switching transistor transmits the first voltage to the load circuit.

2. The circuit according to claim 1, characterized in that The high-side switch circuit further includes a second power supply, and the drive circuit includes: a first charge pump circuit and a second charge pump circuit; a first end of the first charge pump circuit is coupled to the second power supply, and a second end of the first charge pump circuit is connected to a first end of the second charge pump circuit; a second end of the second charge pump circuit is connected to a gate end of the first switch transistor; wherein: The second power supply is used to provide the second voltage; The first charge pump circuit is used to raise the second voltage to obtain a preset voltage, and transmit the preset voltage to the second charge pump circuit; The second charge pump circuit is used to raise the preset voltage to obtain the bias voltage, and apply the bias voltage to the gate terminal of the first switching transistor; wherein the preset voltage and the preset difference are equal in value; during the operation of the high-side switching circuit, the second power supply and the first charge pump circuit are always kept in the turned-on state.

3. The circuit according to claim 2, characterized in that The third terminal of the second charge pump circuit is connected to the second terminal of the first switch transistor; wherein: The second charge pump circuit is further configured to receive the second terminal voltage of the first switch transistor, and to raise the preset voltage according to the voltage of the second terminal of the first switch transistor to obtain the bias voltage.

4. The circuit according to claim 2 or 3, characterized in that: The high-side switch circuit further includes a second switch transistor and a third power supply; a first end of the second switch transistor is connected to the third power supply, a second end of the second switch transistor is connected to the load circuit, and a gate end of the second switch transistor and a second end of the second switch transistor are connected to the drive circuit; wherein: The third power supply is used to provide a third voltage to the second switching transistor; The driving circuit, after raising the second voltage to obtain the bias voltage, controls whether to turn on the second switching transistor according to the bias voltage; wherein the raising process also makes the difference between the voltage at the gate terminal of the second switching transistor and the voltage at the second terminal of the second switching transistor greater than the preset difference; when the second switching transistor is turned on, the second switching transistor transmits the third voltage to the load circuit.

5. The circuit according to claim 4, characterized in that The first switch transistor and the second switch transistor are both NMOS transistors.

6. The circuit according to claim 5, characterized in that The driving circuit further includes a third charge pump circuit; a first end of the third charge pump circuit is connected to a second end of the first charge pump circuit, a second end of the third charge pump circuit is connected to a gate end of the second switch transistor, and a third end of the third charge pump circuit is connected to a second end of the second switch transistor; wherein: The third charge pump circuit is used to raise the voltage of the second end of the second switching transistor by the preset difference to obtain the bias voltage, and apply the bias voltage to the gate end of the second switching transistor; the second charge pump circuit and / or the third charge pump circuit are turned on or off according to the working state of the high-side switching circuit.

7. The circuit according to claim 6, characterized in that The high-side switch circuit further includes a logic control circuit; the logic control circuit is connected to the control end of the second charge pump circuit; wherein: The logic control circuit is used to receive an initial control signal, perform logic processing on the initial control signal, generate a first control signal in an enabled state when the initial control signal indicates to turn on the first switch transistor, and transmit the first control signal to the second charge pump circuit; Wherein, when the first control signal is in an enabled state, the second charge pump circuit is turned on and the first switch transistor is turned on; when the first control signal is in a disabled state, the second charge pump circuit is turned off and the first switch transistor is turned off.

8. The circuit according to claim 7, characterized in that The logic control circuit is also connected to the control terminal of the third charge pump circuit; wherein: The logic control circuit is further configured to generate a first control signal in an enabled state and a second control signal in a disabled state when the initial control signal indicates that the first switch transistor is turned on and the second switch transistor is turned off; or, generate a first control signal in a disabled state and a second control signal in an enabled state when the initial control signal indicates that the first switch transistor is turned off and the second switch transistor is turned on; and transmit the first control signal to the second charge pump circuit, and transmit the second control signal to the third charge pump circuit; Among them, when the second control signal is in an enabled state, the third charge pump circuit is turned on and the second switch transistor is turned on; when the second control signal is in a disabled state, the third charge pump circuit is turned off and the second switch transistor is turned off.

9. The circuit according to claim 8, characterized in that The high-side switch circuit further includes: a dead time control circuit; a first output end of the dead time control circuit is connected to the control end of the second charge pump circuit, and a second output end of the dead time control circuit is connected to the control end of the third charge pump circuit; wherein: The dead time control circuit is used to delay the first control signal and / or the second control signal, and then transmit the delayed first control signal to the second charge pump circuit and transmit the delayed second control signal to the third charge pump circuit, respectively, so that after the second charge pump circuit is turned off, the third charge pump circuit is delayed to turn on, or after the third charge pump circuit is turned off, the second charge pump circuit is delayed to turn on.

10. The circuit according to claim 9, characterized in that The dead time control circuit includes a logic processing circuit and a delay processing circuit; The logic processing circuit is used to receive the first control signal and the second control signal, and perform logic processing according to the first control signal and the second control signal to generate a first intermediate control signal and a second intermediate control signal; wherein, if the first control signal and the second control signal are both in the first level state, then the first intermediate control signal and the second intermediate control signal are both in the second level state; otherwise, the level state of the first intermediate control signal is the same as the first control signal, and the level state of the second intermediate control signal is the same as the second control signal; The delay processing circuit is used to receive the first intermediate control signal and the second intermediate control signal, and generate a first target control signal and a second target control signal according to the first intermediate control signal and the second intermediate control signal; wherein, when one of the first intermediate control signal and the second intermediate control signal changes from the second level state to the first level state, after the preset time interval, one of the first target control signal and the second target control signal changes from the second level state to the first level state; The first target control signal is the first control signal after delay processing; the second target control signal is the second control signal after delay processing.

11. The circuit according to claim 10, characterized in that The logic processing circuit includes a first NAND gate, a first AND gate, and a second AND gate; The first input end of the first NAND gate and the first input end of the first AND gate are both used to receive the first control signal, the second input end of the first NAND gate and the second input end of the second AND gate are both used to receive the second control signal, and the output end of the first NAND gate is connected to the second input end of the first AND gate and the first input end of the second AND gate; The output end of the first AND gate is used to output the first intermediate control signal; The output terminal of the second AND gate is used to output the second intermediate control signal.

12. The circuit according to claim 11, characterized in that The delay processing circuit includes a second NAND gate, a first delay unit, a first NOR gate, a third NAND gate, a third NAND gate, a second delay unit, a second NOR gate, a fourth NOR gate, a fifth NOR gate and a sixth NOR gate; The first input end of the second NAND gate is used to receive the first intermediate control signal; the second input end of the second NAND gate is connected to the output end of the fourth NAND gate, and is used to receive the fourth intermediate control signal; the output end of the second NAND gate is connected to the input end of the first delay unit and the first input end of the first NOR gate; the output end of the first delay unit is connected to the second input end of the first NOR gate; the output end of the first NOR gate is connected to the input end of the third NOR gate; the output end of the third NOR gate is used to output a third intermediate control signal; The first input end of the third NAND gate is used to receive the second intermediate control signal; the second input end of the third NAND gate is connected to the output end of the third NOT gate, and is used to receive the third intermediate control signal; the output end of the third NAND gate is connected to the input end of the second delay unit and the first input end of the second NOR gate; the output end of the second delay unit is connected to the second input end of the second NOR gate; the output end of the second NOR gate is connected to the input end of the fourth NOT gate; the output end of the fourth NOT gate is used to output the fourth intermediate control signal; The input end of the fifth NOT gate is used to receive the third intermediate control signal, and the output end of the fifth NOT gate is used to output the first target control signal; The input end of the sixth NOT gate is used to receive the fourth intermediate control signal, and the output end of the sixth NOT gate is used to output the second target control signal.

13. The circuit according to any one of claims 5 to 12, characterized in that The working mode of the first power supply includes an ET mode or an APT mode; the working mode of the third power supply includes an ET mode or an APT mode; wherein the working modes of the first power supply and the third power supply are different.

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