System and method for sharing clock source by platform

Abstract

The invention relates to the technical field of clock source sharing, and particularly discloses a system and a method for sharing a clock source by a platform, which are used for sampling LVPECL clock signals distributed to a Feiteng processor and a 10-gigabit network card by a clock buffer so as to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal; and a signal processing algorithm based on artificial intelligence and deep learning is introduced at a rear end to analyze LVPECL clock sampling signals of the two, so that fine-grained optimal matching interaction characteristics of the LVPECL clock sampling signals of the two are learned and captured, and signal waveform semantic joint representation and clock buffer performance monitoring are carried out. Therefore, the monitoring result of whether the working state of the clock buffer is abnormal or not is obtained. Therefore, the quality of the clock signal can be continuously checked and monitored in an intelligent automatic monitoring mode, and the working condition of the clock buffer can be fed back in time.

Description

Technical Field

[0001] The present application relates to the technical field of shared clock sources, and more specifically, to a system and method for sharing a platform clock source. Background Art

[0002] In the current market, a common design is to separate the central processing unit (CPU) from the network interface card (NIC). However, in order to adapt to more complex and specific needs, it is necessary to integrate the CPU clock signal and peripheral interfaces such as Gigabit / 10G network interfaces and SATA in a unified platform. In addition, a highly accurate reference clock source is required to realize the CPU clock and Gigabit and 10G network interface functions. However, multiple frequencies are required to realize the CPU clock and Gigabit and 10G functions at the same time. If traditional differential crystal oscillators are used to provide these frequencies, they will face high cost issues. At the same time, the presence of multiple high-frequency oscillators will also have an adverse effect on the signal integrity of the circuit and increase the difficulty of printed circuit board layout.

[0003] Therefore, an optimized solution for sharing clock sources among platforms is desired. Summary of the invention

[0004] The present application provides a system and method for sharing clock sources on a platform, which can continuously check and monitor the quality of clock signals in an intelligent automatic monitoring manner, and timely feedback the working status of the clock buffer, thereby reducing maintenance costs and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals.

[0005] In a first aspect, a method for sharing a platform clock source is provided, comprising:

[0006] Burn the required N frequencies into the field programmable crystal oscillator;

[0007] The field programmable crystal oscillator outputs an LVPECL clock signal to a clock buffer, wherein the LVPECL clock signal has a first frequency;

[0008] The clock buffer distributes the LVPECL clock signal to a plurality of key components;

[0009] The field programmable crystal oscillator is controlled by an FPGA chip to switch from a first frequency to a second frequency, where the second frequency is different from the first frequency.

[0010] In a possible implementation, the N frequencies are three frequencies, and the three frequencies are 125 MHz, 155.52 MHz, and 78.125 MHz.

[0011] In a possible implementation, the field programmable crystal oscillator is a CY2XF24F field programmable crystal oscillator.

[0012] In a possible implementation, the clock buffer is a MC100LVEP210 clock buffer.

[0013] In one possible implementation, the multiple key components include a Feiteng processor and a 10 Gigabit network card.

[0014] In a possible implementation, the steps are further included:

[0015] sampling the LVPECL clock signal distributed by the clock buffer to the plurality of key components based on a predetermined sampling period to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal;

[0016] Performing signal waveform feature extraction on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature;

[0017] Performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a joint optimal representation of the clock sampling signal waveform semantics;

[0018] Based on the clock sampling signal waveform semantics and the optimal representation, performance monitoring is performed to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer.

[0019] In one possible implementation, signal waveform feature extraction is performed on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature, including: inputting the first LVPECL clock sampling signal and the second LVPECL clock sampling signal into a signal waveform feature extractor based on a deep separable convolutional neural network model to obtain a first LVPECL clock sampling signal waveform semantic feature vector as the first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature vector as the second LVPECL clock sampling signal waveform semantic feature.

[0020] In a possible implementation, fine-grained optimal matching feature interaction is performed on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a joint optimal representation of the clock sampling signal waveform semantics, including:

[0021] Based on a predetermined scale, fine-grained feature decoupling is performed on the first LVPECL clock sampling signal waveform semantic feature vector and the second LVPECL clock sampling signal waveform semantic feature vector to obtain a set of first LVPECL clock sampling signal waveform semantic sub-component feature vectors and a set of second LVPECL clock sampling signal waveform semantic sub-component feature vectors;

[0022] Calculate a hyperbolic space distance metric factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors;

[0023] Based on the hyperbolic space distance measurement factor, the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors are screened for optimal feature sub-component pairing to obtain an optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing set;

[0024] Input each optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pair in the set of the optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings into a feature multi-dimensional interaction module to obtain a set of clock sampling signal waveform semantic optimal sub-component feature pairing interaction fusion feature vectors;

[0025] The set of the clock sampling signal waveform semantic optimal sub-component feature pairing interactive fusion feature vectors is cascaded to obtain the clock sampling signal waveform semantic joint optimal representation vector as the clock sampling signal waveform semantic joint optimal representation.

[0026] In a possible implementation, calculating a hyperbolic space distance metric factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors includes:

[0027] Extracting a first LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector;

[0028] Extracting a second LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector;

[0029] Calculating the square of a norm of a difference vector between the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector and the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a norm representation of a semantic difference of a clock sampling signal waveform semantic sub-component;

[0030] Calculating the difference between the constant 1 and the square of the one-norm of the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain the one-norm representation of the first LVPECL clock sampling signal waveform semantic sub-component;

[0031] Calculating the difference between the constant 1 and the square of the one-norm of the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a one-norm representation of the second LVPECL clock sampling signal waveform semantic sub-component;

[0032] After calculating the multiplication between the first LVPECL clock sampling signal waveform semantic sub-component-norm representation and the second LVPECL clock sampling signal waveform semantic sub-component-norm representation to obtain a multiplication representation, the clock sampling signal waveform semantic sub-component semantic difference-norm representation is divided by the multiplication representation to obtain a clock sampling signal waveform semantic-norm semantic implicit association representation;

[0033] The semantic-norm semantic implicit association representation of the clock sampling signal waveform is multiplied by a constant 2 and then added to a constant 1, and the obtained feature representation is passed through an inverse hyperbolic cosine function to obtain the hyperbolic space distance measurement factor.

[0034] In one possible implementation, performance monitoring is performed based on the clock sampling signal waveform semantics and the joint optimal representation to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer, including: inputting the clock sampling signal waveform semantics and the joint optimal representation vector into a classifier-based performance monitoring module to obtain the monitoring result.

[0035] In a second aspect, a system for sharing a platform clock source is provided, including:

[0036] Frequency burning module, used to burn the required N frequencies into the field programmable crystal oscillator;

[0037] A clock signal transmission module, used for the field programmable crystal oscillator to output an LVPECL clock signal to a clock buffer, wherein the LVPECL clock signal has a first frequency;

[0038] A clock signal distribution module, used for the clock buffer to distribute the LVPECL clock signal to multiple key components;

[0039] A crystal oscillator frequency switching module is used to control the field programmable crystal oscillator to switch from a first frequency to a second frequency through an FPGA chip, where the second frequency is different from the first frequency.

[0040] The present application provides a system and method for sharing a clock source on a platform, which samples the LVPECL clock signal assigned to the Feiteng processor and the 10 Gigabit network card by the clock buffer through a predetermined sampling period, so as to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal, and introduces a signal processing algorithm based on artificial intelligence and deep learning at the back end to analyze the LVPECL clock sampling signals of the two, so as to learn and capture the fine-grained optimal matching interaction characteristics of the two LVPECL clock sampling signals, so as to perform signal waveform semantic joint representation and clock buffer performance monitoring, so as to obtain a monitoring result of whether there is an abnormality in the working state of the clock buffer. In this way, the quality of the clock signal can be continuously checked and monitored in an intelligent automatic monitoring manner, and the working status of the clock buffer can be fed back in time, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments of the present application are briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application, and are not intended to limit the present application.

[0042] Figure 1 The present invention is a schematic flowchart of a method for sharing a clock source between platforms according to an embodiment of the present application.

[0043] Figure 2 Schematic diagram of the clock architecture of the present invention.

[0044] Figure 3 A schematic flow chart of clock buffer performance monitoring in a method for platform sharing clock sources according to an embodiment of the present application.

[0045] Figure 4 A schematic diagram of data flow for monitoring clock buffer performance in a method for sharing a platform clock source according to an embodiment of the present application.

[0046] Figure 5 In the method for sharing a clock source on a platform according to an embodiment of the present application, a schematic flowchart is provided for performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a joint optimal representation of the clock sampling signal waveform semantics. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work also fall within the scope of protection of the present application.

[0048] Field programmable crystal oscillators, such as the CY2XF24F, are a new type of clock source solution that can be programmed to change its output frequency. This device can dynamically adjust its output frequency according to application requirements without changing the hardware, thereby supporting a variety of different operating modes or protocol requirements. In addition, this flexibility also allows the system to dynamically adjust the clock frequency during operation to optimize power consumption or meet different performance requirements. However, having a programmable clock source alone is not enough to ensure the stability of the entire system. The clock signal may be affected by noise interference or attenuation in the process from the source to various target components (such as Feiteng processors and 10G network cards). To ensure the quality of the clock signal, a clock buffer (such as the MC100LVEP210) is used, which can enhance the clock signal and distribute it evenly to each receiver.

[0049] Based on this, in the technical solution of this application, a method for sharing a platform clock source is proposed, such as Figure 1As shown, the method for sharing the clock source of the platform includes: S1, burning the required N frequencies in the field programmable crystal oscillator, wherein the N frequencies are three frequencies, and the three frequencies are 125MHz, 155.52MHz and 78.125Mhz. S2, the field programmable crystal oscillator outputs an LVPECL clock signal to a clock buffer, and the LVPECL clock signal has a first frequency, wherein the field programmable crystal oscillator is a CY2XF24F field programmable crystal oscillator, and the clock buffer is an MC100LVEP210 clock buffer. S3, the clock buffer distributes the LVPECL clock signal to multiple key components, wherein the multiple key components include a Feiteng processor and a 10G network card. S4, controlling the field programmable crystal oscillator to switch from the first frequency to the second frequency through an FPGA chip, and the second frequency is different from the first frequency. Specifically, in a specific example of the present application, the CY2XF24F field programmable crystal oscillator has three different frequency setting points pre-stored inside, and which frequency to output can be selected through the I2C bus. The frequency switching command is sent by the FPGA control program, which ensures that the frequency switching can be performed correctly under any input frequency conditions.

[0050] It is worth mentioning that when encountering a situation where a special frequency is required during the development phase, although the CY2XF24F is a one-time programming device, new operating frequency parameters can be re-downloaded through the I2C interface without replacing the crystal oscillator. This operation does not permanently change the preset values ​​in the crystal oscillator, but temporarily modifies the parameters during operation, so after power failure, these parameters need to be loaded again through software at each startup. It is worth noting that the CY2XF24F cannot directly modify the frequency currently being output, but allows other preset frequency parameters to be modified and frequency changes to be achieved through switching. This method not only helps to utilize the crystal oscillator resources that have been programmed but not fully used to avoid material waste, but also under certain specific conditions, the system's reference clock frequency can be flexibly adjusted simply through software, which greatly facilitates the system debugging process. In this way, not only the flexibility of clock management is improved, but also the reliability of the system is enhanced.

[0051] That is, in order to use a single crystal oscillator to generate all clock frequencies, we chose Cypress's CY2XF24F field programmable crystal oscillator, and used the clock buffer MC100LVEP210 to provide reference clocks for each major device. CY2XF24F can store 4 pre-programmed frequency points internally, and then use the IIC bus to select which frequency to output. The IIC command for switching frequency is issued by the FPGA program, and the FPGA program is specially processed to ensure that the switching command can be issued normally under any input frequency.

[0052] In addition, during the debugging process, some very special frequencies are sometimes required. Although CY2XF24F is a one-time programmable device, it does not need to replace the crystal oscillator. The parameters of the new operating frequency point can be downloaded to CY2XF24F using the IIC interface. This does not modify the internal parameters that have been programmed, but only the parameters during operation are modified. That is to say, the parameters downloaded using IIC will be lost after power failure, and the software needs to be downloaded every time. CY2XF24F cannot modify the currently output frequency point, but can modify other frequency point parameters and then switch to them. The significance of this is that the remaining crystal oscillators that have been programmed in other projects but have inconsistent frequency point selections can be used without causing material waste. In some special cases, the reference clock of the system can be modified arbitrarily using only software, which is convenient for system debugging.

[0053] Optionally, in one embodiment of the present application, Figure 2 As shown, the LVPECL clock output by CY2XF24F is connected to the input of MC100LVEP210, and the output of MC100LVEP210 is connected to the 10G interface chip and FPGA respectively (other network interfaces are implemented by FPGA). The control interface of CY2XF24F is also connected to FPGA. The three required frequencies are pre-burned in CY2XF24F. When the system is powered on, CY2XF24F will output the first frequency by default. At this time, the entire clock network works at 125MHz, and the GTP of FPGA can normally lock the signal of Gigabit Ethernet. At this time, the network card works in Gigabit mode. When it is necessary to switch to 10G mode, switch its working frequency 2 through the control interface of CY2XF24F. At this time, the entire clock network works at 155.52MHz. After that, the 10G network chip is re-initialized and it can normally lock the signal of 10G Ethernet, so that the system can work in 10G mode.

[0054] Furthermore, considering that the quality of the clock signal directly affects the data transmission rate and accuracy in the system, especially for key components that require high-precision clock signals, such as Feiteng processors and 10G network cards. And because the clock signal may be affected by various factors during the transmission process, such as electromagnetic interference, signal attenuation, or clock jitter. Therefore, in order to ensure the quality of the clock signal, it is necessary to monitor the performance of the clock buffer to determine whether the clock buffer is in normal working condition. In this way, it can ensure that the clock buffer MC100LVEP210 is in good working condition to ensure the stability and reliability of the entire system.

[0055] Based on this, the technical concept of the present application is to sample the LVPECL clock signal assigned to the Feiteng processor and the 10 Gigabit network card by the clock buffer through a predetermined sampling period, so as to obtain the first LVPECL clock sampling signal and the second LVPECL clock sampling signal, and introduce a signal processing algorithm based on artificial intelligence and deep learning at the back end to analyze the two LVPECL clock sampling signals, so as to learn and capture the fine-grained optimal matching interaction characteristics of the two LVPECL clock sampling signals, so as to perform signal waveform semantic joint representation and clock buffer performance monitoring, so as to obtain the monitoring result of whether there is any abnormality in the working state of the clock buffer. In this way, the quality of the clock signal can be continuously checked and monitored in an intelligent automatic monitoring manner, and the working status of the clock buffer can be fed back in time, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals.

[0056] Figure 3 A schematic flow chart of clock buffer performance monitoring in a method for platform sharing clock sources according to an embodiment of the present application. Figure 4 This is a schematic diagram of data flow for monitoring clock buffer performance in the platform sharing clock source method of the embodiment of the present application. Figure 3 and Figure 4 As shown, the method for sharing clock sources on the platform also includes the steps of: S11, sampling the LVPECL clock signal allocated by the clock buffer to the multiple key components based on a predetermined sampling period to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal; S12, respectively extracting signal waveform features of the first LVPECL clock sampling signal and the second LVPECL clock sampling signal to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature; S13, performing fine-grained optimal matching feature interaction on the waveform semantic feature of the first LVPECL clock sampling signal and the waveform semantic feature of the second LVPECL clock sampling signal to obtain a joint optimal representation of the waveform semantics of the clock sampling signal; S14, performing performance monitoring based on the joint optimal representation of the waveform semantics of the clock sampling signal to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer.

[0057] In the method for sharing the clock source of the above-mentioned platform, the S11 samples the LVPECL clock signal assigned to the multiple key components by the clock buffer based on a predetermined sampling period to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal. It should be understood that the clock signal is a vital component in a digital system and is used to synchronize the operation of various components. Since the clock signal may be affected by various factors during the transmission process, such as power supply fluctuations, electromagnetic interference, temperature changes, etc., these may cause signal distortion or jitter. Therefore, it is necessary to sample and analyze the clock signal in order to discover and solve these problems in a timely manner. By sampling the clock signals assigned to multiple key components by the clock buffer using a predetermined sampling period, the first LVPECL clock signal and the second LVPECL clock signal assigned to the Feiteng processor and the 10 Gigabit network card by the clock buffer can be obtained. This signal can be used to determine the synchronization state and quality of the clock signal, thereby determining the working condition of the clock buffer.

[0058] In the method for sharing a clock source on the platform, the S12 extracts signal waveform features from the first LVPECL clock sampling signal and the second LVPECL clock sampling signal to obtain waveform semantic features of the first LVPECL clock sampling signal and waveform semantic features of the second LVPECL clock sampling signal. It should be understood that the first LVPECL clock sampling signal and the second LVPECL clock sampling signal are input into a signal waveform feature extractor based on a deep separable convolutional neural network model for feature mining to extract waveform semantic features from the first LVPECL clock sampling signal and the second LVPECL clock sampling signal, respectively, thereby obtaining waveform semantic feature vectors of the first LVPECL clock sampling signal and waveform semantic feature vectors of the second LVPECL clock sampling signal.

[0059] Optionally, in one embodiment of the present application, signal waveform feature extraction is performed on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature, respectively, including: inputting the first LVPECL clock sampling signal and the second LVPECL clock sampling signal into a signal waveform feature extractor based on a deep separable convolutional neural network model to obtain a first LVPECL clock sampling signal waveform semantic feature vector as the first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature vector as the second LVPECL clock sampling signal waveform semantic feature.

[0060] In the method for sharing clock sources on the above-mentioned platform, the S13 performs fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain the clock sampling signal waveform semantic joint optimal representation. It should be understood that since the first LVPECL clock sampling signal waveform semantic feature vector and the second LVPECL clock sampling signal waveform semantic feature vector respectively contain the waveform semantic features of the first LVPECL clock signal and the second LVPECL clock signal assigned to the Feiteng processor and the 10 Gigabit network card by the clock buffer, if the performance of the clock buffer is to be judged and monitored, it is necessary to jointly analyze the waveform semantics of the LVPECL clock signals of the two to detect the quality of the two clock signals and whether they are synchronized. Based on this, in order to enhance the understanding and joint representation capabilities of the waveform semantic features of the two clock signals, in the technical solution of the present application, the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature are further fine-grained optimal matching feature interaction to obtain the clock sampling signal waveform semantic joint optimal representation.

[0061] Figure 5 In the platform sharing clock source method of the embodiment of the present application, a schematic flow chart of performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a clock sampling signal waveform semantic joint optimal representation. Figure 5As shown, optionally, in one embodiment of the present application, fine-grained optimal matching feature interaction is performed on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a joint optimal representation of the clock sampling signal waveform semantics, including: S131, based on a predetermined scale, fine-grained feature decoupling is performed on the first LVPECL clock sampling signal waveform semantic feature vector and the second LVPECL clock sampling signal waveform semantic feature vector to obtain a set of first LVPECL clock sampling signal waveform semantic sub-component feature vectors and a set of second LVPECL clock sampling signal waveform semantic sub-component feature vectors; S132, calculating the hyperbolic space distance measurement factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors; S133, based on the hyperbolic space distance measurement factor, The set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors are screened for the best feature sub-component pairing to obtain the set of the best first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings; S134, each best first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing in the set of the best first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings is input into the feature multi-dimensional interaction module to obtain the set of clock sampling signal waveform semantic optimal sub-component feature pairing interactive fusion feature vectors; S135, the set of the clock sampling signal waveform semantic optimal sub-component feature pairing interactive fusion feature vectors is cascaded to obtain the clock sampling signal waveform semantic joint optimal representation vector as the clock sampling signal waveform semantic joint optimal representation.

[0062] Optionally, in one embodiment of the present application, a hyperbolic space distance measurement factor is calculated between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors, including: extracting the first LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector; extracting the second LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector; calculating the distance measurement factor between the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector and the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector. The square of the norm of the differential vector of the predetermined first LVPECL clock sampling signal waveform semantic sub-component semantic difference is obtained to obtain the norm representation of the semantic difference of the clock sampling signal waveform semantic sub-component; the difference between the constant 1 and the square of the norm of the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector is calculated to obtain the norm representation of the first LVPECL clock sampling signal waveform semantic sub-component; the difference between the constant 1 and the square of the norm of the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector is calculated to obtain the norm representation of the second LVPECL clock sampling signal waveform semantic sub-component; the first LVP After multiplying the ECL clock sampling signal waveform semantic sub-component-norm representation and the second LVPECL clock sampling signal waveform semantic sub-component-norm representation to obtain the multiplication representation, the clock sampling signal waveform semantic sub-component semantic difference-norm representation is divided by the multiplication representation to obtain the clock sampling signal waveform semantic-norm semantic implicit association representation; the clock sampling signal waveform semantic-norm semantic implicit association representation is multiplied by a constant 2 and then added to a constant 1, and the obtained feature representation is passed through an inverse hyperbolic cosine function to obtain the hyperbolic space distance measurement factor.

[0063] Optionally, in one embodiment of the present application, based on the hyperbolic space distance measurement factor, the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors are screened for optimal feature sub-component pairing to obtain an optimal set of first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings, including: selecting the position of the second LVPECL clock sampling signal waveform semantic sub-component feature vector corresponding to the minimum value of multiple hyperbolic space distance measurement factors as the optimal pairing position value of the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector; pairing the first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector corresponding to the optimal pairing position value to obtain an optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing.

[0064] Optionally, in one embodiment of the present application, each optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing in the set of the optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing is input into a feature multi-dimensional interaction module to obtain a set of clock sampling signal waveform semantic optimal sub-component feature pairing interactive fusion feature vectors, including: The first LVPECL clock sampling signal waveform semantic sub-component feature vector and the second LVPECL clock sampling signal waveform semantic sub-component feature vector are respectively subjected to positional difference, positional dot multiplication and positional summation processing to obtain a clock sampling signal waveform semantic sub-component differential feature vector, a clock sampling signal waveform semantic sub-component dot product feature vector and a clock sampling signal waveform semantic sub-component sum feature vector; the positional weighted sum of the clock sampling signal waveform semantic sub-component differential feature vector, the clock sampling signal waveform semantic sub-component dot product feature vector and the clock sampling signal waveform semantic sub-component sum feature vector is calculated to obtain a clock sampling signal waveform semantic optimal sub-component feature pairing interactive fusion feature vector.

[0065] In summary, in the embodiment of the present application, the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature are fine-grained optimal matching feature interaction is performed using the following feature interaction formula to obtain the clock sampling signal waveform semantic joint optimal representation; Among them, the feature interaction formula is: in, is the first LVPECL clock sampling signal waveform semantic feature vector, is the semantic feature vector of the second LVPECL clock sampling signal waveform, Decouple operations for fine-grained features, are the first, second, and third components of the set of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform. and The first LVPECL clock sampling signal waveform semantic sub-component feature vector, are the first, second, and third components of the set of semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform. and The second LVPECL clock sampling signal waveform semantic sub-component feature vector, represents the one-norm of a vector, is the inverse hyperbolic cosine function, for and The hyperbolic space distance metric between To obtain The minimum value corresponds to parameter, is the optimal pairing position value, The first of the set of semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform is The second LVPECL clock sampling signal waveform semantic sub-component feature vector, , and They are positional subtraction, positional dot multiplication, and positional addition. , and are weighted hyperparameters, The first one in the set of semantic optimal sub-component feature pairing interaction fusion feature vectors of the clock sampling signal waveform The clock sampling signal waveform semantic optimal sub-component feature pairing interactive fusion feature vector, is the cascade operation of vectors, The clock sampling signal waveform semantic joint optimal representation vector is provided.

[0066] Specifically, the data processing process of the fine-grained optimal matching feature interaction first decouples the first LVPECL clock sampling signal waveform semantic feature vector and the second LVPECL clock sampling signal waveform semantic feature vector based on a predetermined scale to decompose them into multiple sub-component feature vectors. In this way, feature comparison can be performed at a lower level, which can help capture subtle differences in the semantics of the clock signal waveform in a more detailed manner, such as the phase, frequency stability, jitter, etc. of the signal. This fine-grained analysis helps to reveal the intrinsic characteristics of the clock signal and its changing laws. Then, after feature decoupling, by calculating the hyperbolic space distance measurement factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors, the fine-grained semantic association relationship between the features can be better described and captured. The reason for using the hyperbolic space distance metric instead of the traditional Euclidean distance or other metric methods is that the hyperbolic space distance metric can effectively process data with hierarchical structures or high-dimensional sparse data, which is particularly useful for analyzing complex patterns in clock signals because it can more accurately reflect the hierarchical relationship and interaction between the semantic features of different component waveforms in the two clock signals. Then, based on the hyperbolic space distance metric factor, the best feature sub-component pairing screening can be found to find the pairing that best represents the semantic similarity between the two feature vector sets. That is, based on the above metric, the next step is to optimally pair the sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors, with the aim of finding a pair of feature vectors with the smallest distance in the hyperbolic space, thereby achieving the best match. This process ensures that the selected pairing is optimal and can retain the most valuable sub-component information in the semantics of the two LVPECL clock sampling signal waveforms to the greatest extent, thereby improving the effect of subsequent feature fusion. After the best pairing, the best first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings are input into the feature multi-dimensional interaction module to interact with each other and generate new feature vectors. Through these interactive operations (such as addition, multiplication, etc.), new feature representations can be created that can better reflect the complex relationship between different LVPECL clock sampling signal waveform semantics in the original data. This is very important for understanding and diagnosing problems in clock signals because it can help identify abnormal patterns in the signal.Finally, the set of interactive fusion feature vectors of the optimal sub-component feature pairing of the clock sampling signal waveform semantics is cascaded and fused to form a comprehensive and optimized joint optimal representation of the clock sampling signal waveform semantics. This comprehensive representation not only contains the original clock sampling signal waveform semantic information, but also integrates the new information generated by fine-grained matching and multi-dimensional interaction, so as to more comprehensively characterize the characteristics of the clock signal. It provides a basis for the subsequent working status monitoring of the clock buffer.

[0067] In the method for sharing clock sources on the above platforms, the S14, based on the clock sampling signal waveform semantics joint optimal representation, performance monitoring is performed to determine the monitoring result, and the monitoring result is used to indicate whether the working state of the clock buffer is abnormal. Optionally, in one embodiment of the present application, based on the clock sampling signal waveform semantics joint optimal representation, performance monitoring is performed to determine the monitoring result, and the monitoring result is used to indicate whether the working state of the clock buffer is abnormal, including: inputting the clock sampling signal waveform semantics joint optimal representation vector into a performance monitoring module based on a classifier to obtain the monitoring result. That is, the first LVPECL clock sampling signal waveform semantics and the second LVPECL clock sampling signal waveform semantics are used to perform classification processing, so as to perform signal waveform semantics joint representation and clock buffer performance monitoring, thereby obtaining a monitoring result of whether the working state of the clock buffer is abnormal. In this way, the quality of the clock signal can be continuously checked and monitored in an intelligent automatic monitoring manner, and the working status of the clock buffer can be fed back in time, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals.

[0068] Considering that the first LVPECL clock sampling signal waveform semantic feature vector and the second LVPECL clock sampling signal waveform semantic feature vector respectively represent the signal waveform semantic features of the first LVPECL clock sampling signal and the second LVPECL clock sampling signal, when performing feature interaction based on feature fine-grained optimal matching, the time domain and source domain distribution differences (including noise or interference) of the clock sampling signals will also cause the timing feature interaction representation of the clock sampling signal waveform semantic joint optimal representation vector to have a feature instance decision missing based on the interactive fusion distribution of different local features, thereby affecting the accuracy of the monitoring results obtained through the classifier-based performance monitoring module.

[0069] Preferably, inputting the clock sampling signal waveform semantic joint optimal representation vector into a classifier-based performance monitoring module to obtain a monitoring result comprises:

[0070] Calculate the distance between each pair of eigenvalues ​​of the clock sampling signal waveform semantic joint optimal representation vector, such as the L2 distance, and take the square root of the distance to obtain the clock sampling signal waveform semantic joint distance representation matrix, that is, in, represents the clock sampling signal waveform semantic joint optimal representation vector, and The first one represents the semantic joint optimal representation vector of the clock sampling signal waveform and Eigenvalues, The first one represents the semantic joint optimal representation vector of the clock sampling signal waveform and The distance between eigenvalues, Representing the clock sampling signal waveform semantic joint distance representation matrix The eigenvalue of the position;

[0071] The clock sampling signal waveform semantic joint autocorrelation matrix of the clock sampling signal waveform semantic joint optimal representation vector as a row vector is obtained, that is, ,in, represents the clock sampling signal waveform semantic joint optimal representation vector, represents the transpose of a vector, represents matrix multiplication, Represents the semantic joint autocorrelation matrix of the clock sampling signal waveform;

[0072] The clock sampling signal waveform semantic joint optimal representation vector is matrix-multiplied with the clock sampling signal waveform semantic joint distance representation matrix to obtain the clock sampling signal waveform semantic joint primary mapping vector, that is, ,in, represents the clock sampling signal waveform semantic joint optimal representation vector, Represents the semantic joint distance representation matrix of the clock sampling signal waveform, represents matrix multiplication, Represents the clock sampling signal waveform semantics joint first-level mapping vector;

[0073] The clock sampling signal waveform semantic joint first-level mapping vector is matrix-multiplied with the matrix product of the clock sampling signal waveform semantic joint distance representation matrix and the clock sampling signal waveform semantic joint autocorrelation matrix to obtain a clock sampling signal waveform semantic joint multi-level mapping vector ,in, Represents the clock sampling signal waveform semantic joint first-level mapping vector, Represents the semantic joint distance representation matrix of the clock sampling signal waveform, represents matrix multiplication, Represents the semantic joint autocorrelation matrix of the clock sampling signal waveform, Represents the semantic joint multi-level mapping vector of the clock sampling signal waveform;

[0074] The clock sampling signal waveform semantics joint multi-level mapping vector is interpolated with the clock sampling signal waveform semantics joint associated eigenvector composed of the eigenvalues ​​of the clock sampling signal waveform semantics joint auto-correlation matrix to obtain an optimized clock sampling signal waveform semantics joint optimal representation vector, wherein interpolation or zero padding is performed when the eigenvalue is insufficient;

[0075] The optimized clock sampling signal waveform semantics and the optimal representation vector are input into a classifier-based performance monitoring module to obtain a monitoring result.

[0076] Therefore, through the linear target mapping representation based on the similarity distance representation matrix of the clock sampling signal waveform semantic joint optimal representation vector, the self-correlation of the clock sampling signal waveform semantic joint optimal representation vector is instantiated with a secondary target mapping representation based on a multi-level distribution hierarchy, and the correlation mismatch negative impact factor is compensated by the association fusion kernel bias to improve the instance determination degree of the eigenvalue of the clock sampling signal waveform semantic joint optimal representation vector under the similarity restriction, that is, the significance degree of the eigenvalue as an instance for classification regression judgment, and improve the accuracy of the monitoring results of the clock sampling signal waveform semantic joint optimal representation vector obtained by the classifier-based performance monitoring module. In this way, the working status of the clock buffer can be monitored more accurately, reducing the maintenance cost and downtime caused by clock buffer problems.

[0077] In summary, according to the method of sharing the clock source of the platform of the embodiment of the present application, the LVPECL clock signal allocated to the Feiteng processor and the 10 Gigabit network card by the clock buffer is sampled through a predetermined sampling period, so as to obtain the first LVPECL clock sampling signal and the second LVPECL clock sampling signal, and introduce a signal processing algorithm based on artificial intelligence and deep learning at the back end to analyze the LVPECL clock sampling signals of the two, so as to learn and capture the fine-grained optimal matching interaction characteristics of the two LVPECL clock sampling signals, so as to perform signal waveform semantic joint representation and clock buffer performance monitoring, so as to obtain the monitoring result of whether there is an abnormality in the working state of the clock buffer. In this way, the quality of the clock signal can be continuously checked and monitored in an intelligent automatic monitoring manner, and the working status of the clock buffer can be fed back in time, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals.

[0078] Based on the above embodiments, the present application also discloses a system for sharing a clock source on a platform, comprising: a frequency burning module, used to burn the required N frequencies in a field programmable crystal oscillator; a clock signal transmission module, used for the field programmable crystal oscillator to output an LVPECL clock signal to a clock buffer, wherein the LVPECL clock signal has a first frequency; a clock signal distribution module, used for the clock buffer to distribute the LVPECL clock signal to multiple key components; and a crystal oscillator frequency switching module, used to control the field programmable crystal oscillator to switch from a first frequency to a second frequency through an FPGA chip, wherein the second frequency is different from the first frequency.

[0079] Here, those skilled in the art will appreciate that the specific functions and operations of each module in the system for sharing a clock source on the platform have been described in detail above. Figures 1 to 5 The method for sharing a clock source on a platform of FIG. 1 has been described in detail, and therefore, its repeated description will be omitted.

[0080] The basic principle of the present invention is described above in conjunction with specific embodiments. However, it should be pointed out that the advantages, strengths, effects, etc. mentioned in the present invention are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present invention. In addition, the specific details of the above embodiments are only for the purpose of illustration and facilitation of understanding, rather than limitation, and the above details do not limit the present invention to being implemented by adopting the above specific details.

[0081] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments. In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the module division is only a logical function division, and there may be other division methods in actual implementation. The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0082] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0083] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference to a figure in a claim should not be considered as limiting the claim to which it relates.

[0084] In addition, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units stated in the device claim can also be implemented by one unit through software or hardware.

[0085] Finally, it should be noted that the above description has been given for the purpose of illustration and description. In addition, the above embodiments are only used to illustrate the technical solution of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for sharing a clock source on a platform, characterized in that: include: Burn the required N frequencies into the field programmable crystal oscillator; The field programmable crystal oscillator outputs an LVPECL clock signal to a clock buffer, wherein the LVPECL clock signal has a first frequency; The clock buffer distributes the LVPECL clock signal to a plurality of key components; The field programmable crystal oscillator is controlled by an FPGA chip to switch from a first frequency to a second frequency, where the second frequency is different from the first frequency.

2. The method for sharing a platform clock source according to claim 1, characterized in that: The N frequencies are three frequencies, and the three frequencies are 125 MHz, 155.52 MHz, and 78.125 MHz.

3. The method for sharing a platform clock source according to claim 1, characterized in that: The field programmable crystal oscillator is a CY2XF24F field programmable crystal oscillator.

4. The method for sharing a platform clock source according to claim 1, characterized in that: The clock buffer is a MC100LVEP210 clock buffer.

5. The method for sharing a platform clock source according to claim 1, characterized in that: The multiple key components include Feiteng processor and 10 Gigabit network card.

6. The method for sharing a platform clock source according to claim 1, characterized in that: Also includes the steps: sampling the LVPECL clock signal distributed by the clock buffer to the plurality of key components based on a predetermined sampling period to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal; Performing signal waveform feature extraction on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature; Performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a joint optimal representation of the clock sampling signal waveform semantics; Based on the clock sampling signal waveform semantics and the optimal representation, performance monitoring is performed to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer.

7. The method for sharing a platform clock source according to claim 6, characterized in that: Signal waveform feature extraction is performed on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature, including: inputting the first LVPECL clock sampling signal and the second LVPECL clock sampling signal into a signal waveform feature extractor based on a deep separable convolutional neural network model to obtain a first LVPECL clock sampling signal waveform semantic feature vector as the first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature vector as the second LVPECL clock sampling signal waveform semantic feature.

8. The method for sharing a platform clock source according to claim 7, characterized in that: Performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a joint optimal representation of the clock sampling signal waveform semantics, including: Based on a predetermined scale, fine-grained feature decoupling is performed on the first LVPECL clock sampling signal waveform semantic feature vector and the second LVPECL clock sampling signal waveform semantic feature vector to obtain a set of first LVPECL clock sampling signal waveform semantic sub-component feature vectors and a set of second LVPECL clock sampling signal waveform semantic sub-component feature vectors; Calculate a hyperbolic space distance metric factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors; Based on the hyperbolic space distance measurement factor, the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors are screened for optimal feature sub-component pairing to obtain an optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing set; Input each optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pair in the set of the optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings into a feature multi-dimensional interaction module to obtain a set of clock sampling signal waveform semantic optimal sub-component feature pairing interaction fusion feature vectors; The set of the clock sampling signal waveform semantic optimal sub-component feature pairing interactive fusion feature vectors is cascaded to obtain the clock sampling signal waveform semantic joint optimal representation vector as the clock sampling signal waveform semantic joint optimal representation.

9. The method for sharing a platform clock source according to claim 8, characterized in that: Calculating a hyperbolic space distance metric factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors, comprising: Extracting a first LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector; Extracting a second LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector; Calculating the square of a norm of a difference vector between the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector and the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a norm representation of a semantic difference of a clock sampling signal waveform semantic sub-component; Calculating the difference between the constant 1 and the square of the one-norm of the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain the one-norm representation of the first LVPECL clock sampling signal waveform semantic sub-component; Calculating the difference between the constant 1 and the square of the one-norm of the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a one-norm representation of the second LVPECL clock sampling signal waveform semantic sub-component; After calculating the multiplication between the first LVPECL clock sampling signal waveform semantic sub-component-norm representation and the second LVPECL clock sampling signal waveform semantic sub-component-norm representation to obtain a multiplication representation, the clock sampling signal waveform semantic sub-component semantic difference-norm representation is divided by the multiplication representation to obtain a clock sampling signal waveform semantic-norm semantic implicit association representation; The semantic-norm semantic implicit association representation of the clock sampling signal waveform is multiplied by a constant 2 and then added to a constant 1, and the obtained feature representation is passed through an inverse hyperbolic cosine function to obtain the hyperbolic space distance measurement factor.

10. A system for sharing a clock source on a platform, characterized in that: include: Frequency burning module, used to burn the required N frequencies into the field programmable crystal oscillator; A clock signal transmission module, used for the field programmable crystal oscillator to output an LVPECL clock signal to a clock buffer, wherein the LVPECL clock signal has a first frequency; A clock signal distribution module, used for the clock buffer to distribute the LVPECL clock signal to multiple key components; A crystal oscillator frequency switching module is used to control the field programmable crystal oscillator to switch from a first frequency to a second frequency through an FPGA chip, where the second frequency is different from the first frequency.

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