Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device which can be reduced in size compared with a conventional surface mounting type package and can improve reliability compared with a conventional CSP. The semiconductor device includes: a semiconductor chip having a redistribution line; a lead frame having a die pad on which the semiconductor chip is mounted and a lead connected to the die pad, the lead frame electrically connecting the redistribution line and the die pad by means of a solder or a conductive adhesive; and a sealing member that seals the semiconductor chip.

Description

Technical Field

[0001] The disclosed technology relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The following technology is known as a technology related to semiconductor devices: Patent Document 1 describes a semiconductor device in which a vibrator is mounted on a first surface of a lead frame, an integrated circuit is mounted on a second surface of the lead frame, and the vibrator and the integrated circuit are connected to the lead frame by bonding wires.

[0003] Patent document 2 describes a semiconductor device comprising: a semiconductor element; at least one electrode portion arranged on one surface of the semiconductor element; an insulating layer formed in a manner covering a portion of the one surface of the semiconductor element except the electrode portion; wiring arranged on the insulating layer; and external terminals formed on the wiring.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-232544

[0007] Patent Document 2: Japanese Patent Application Publication No. 2011-60805 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] Surface-mounted semiconductor packages such as SOP (Small Outline Package) and QFP (Quad Flat Package) include a semiconductor chip, a lead frame, and a sealing member. The lead frame has a die pad and leads. The semiconductor chip is mounted on the lead frame, and the semiconductor chip and the leads are connected via bonding wires. In such a surface-mounted package, since bonding wires are used to connect the semiconductor chip and the leads, the size of the package is significantly larger than the size of the semiconductor chip. In addition, the inductance component generated by the bonding wire may affect the electrical characteristics. In addition, there is a risk of breaking or peeling of the bonding wire.

[0010] As a package that can solve the above problems, CSP (chip size package) is known. CSP is a semiconductor package that does not have bonding wires and has a package size that is roughly the same as the size of the semiconductor chip. In CSP, the semiconductor chip is exposed, so there are concerns about reliability, and there is also a problem that it is not easy to handle.

[0011] The disclosed technology has been made in view of the above-mentioned points, and its purpose is to reduce the size compared with the conventional surface mount type package and to improve the reliability compared with the conventional CSP.

[0012] Solutions for solving problems

[0013] The semiconductor device involved in the disclosed technology includes: a semiconductor chip having a redistribution wiring; a lead frame having a die pad carrying the semiconductor chip and leads connected to the die pad, the redistribution wiring and the die pad being electrically connected by solder or a conductive adhesive; and a sealing component that seals the semiconductor chip.

[0014] The manufacturing method of a semiconductor device involved in the disclosed technology includes the following steps: preparing a semiconductor chip with redistribution wiring; connecting the die pad of a lead frame having a die pad and leads connected to the die pad to the redistribution wiring by solder or a conductive adhesive; and sealing the semiconductor chip by a sealing component.

[0015] Effects of the Invention

[0016] According to the disclosed technology, the size can be reduced compared to conventional surface mount packages, and the reliability can be improved compared to conventional CSPs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a perspective view showing an example of the structure of a semiconductor device.

[0018] Figure 2 It is along Figure 1 Cross-sectional view of line 2-2 in FIG.

[0019] Figure 3 It is a plan view showing an example of the structure of a lead frame according to an embodiment of the disclosed technology.

[0020] Figure 4 This is a cross-sectional view showing an example of the structure of a semiconductor chip according to an embodiment of the disclosed technology.

[0021] Figure 5A This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0022] Figure 5B This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0023] Figure 5C This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0024] Figure 5D This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0025] Figure 5E This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0026] Fig. 5F This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0027] Figure 5G This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0028] Figure 5H This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the disclosed technology.

[0029] Figure 6 This is a cross-sectional view comparing the size of a semiconductor device according to an embodiment of the disclosed technology with the size of a surface-mount semiconductor device according to a comparative example.

[0030] Fig. 7A It is a cross-sectional view showing another structural example of a semiconductor device according to an embodiment of the disclosed technology.

[0031] Figure 7B It is a cross-sectional view showing another structural example of a semiconductor device according to an embodiment of the disclosed technology.

[0032] Figure 7C It is a cross-sectional view showing another structural example of a semiconductor device according to an embodiment of the disclosed technology.

[0033] Fig.7D It is a cross-sectional view showing another structural example of a semiconductor device according to an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0034] Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. In addition, in each of the drawings, the same or equivalent components and parts are marked with the same reference numerals, and repeated descriptions are omitted.

[0035] Figure 1 It is a perspective view showing an example of the structure of a semiconductor device 10 according to an embodiment of the disclosed technology. Figure 2 It is along Figure 1 The semiconductor device 10 includes a semiconductor chip 20 , a lead frame 30 , and a sealing member 40 . Figure 3 1 is a plan view showing an example of the structure of the lead frame 30 . Figure 4 2 is a cross-sectional view showing an example of the structure of the semiconductor chip 20 .

[0036] like Figure 4 As shown, the semiconductor chip 20 has a semiconductor substrate 21 on which a circuit element 22 is formed, an insulating film 23 covering the semiconductor substrate 21, and an electrode 24 provided on the insulating film 23 and connected to the circuit element 22. The semiconductor substrate 21 is, for example, a silicon substrate. The circuit element 22 is, for example, a transistor, a diode, a resistor, or a capacitor. The insulating film 23 is, for example, composed of an insulator such as SiO2. The electrode 24 is connected to the circuit element 22 via a through hole 25 penetrating the insulating film 23. The through hole 25 and the electrode 24 are, for example, composed of a conductor such as Al.

[0037] The semiconductor chip 20 has a redistribution layer 50 provided on the insulating film 23. The redistribution layer 50 has the same size as the plane size of the semiconductor substrate 21. The redistribution layer 50 has an insulating film 51 composed of an insulator such as polyimide and PBO (polybenzoxazole), and redistribution 52 provided on the surface of the insulating film 51. The redistribution 52 is connected to the electrode 24 exposed in the opening formed in the insulating film 51. The redistribution 52 is composed of a conductor such as Cu, for example.

[0038] The surface of the redistribution layer 50 is covered with an insulating film 53 made of an insulator such as a photosensitive resin. The terminal pad 54 is connected to the redistribution 52 exposed in the opening formed in the insulating film 53. A plurality of connection terminals 55 are provided on the surface of the terminal pad 54. The connection terminal 55 may also have the form of a solder ball. The redistribution 52 and the terminal pad 54 are made of a conductor such as Cu, for example.

[0039] The semiconductor chip 20 has a redistribution layer 50 having the same size as the plane size of the semiconductor substrate 21 and is a BGA (Ball Grid Array) type chip component having a CSP form.

[0040] like Figure 2 As shown, the semiconductor chip 20 is mounted on a lead frame 30. The lead frame 30 is made by sequentially performing precision pressing (punching, drawing, bending) on ​​a thin plate having excellent electrical conductivity, mechanical strength, thermal conductivity, and corrosion resistance, such as a Cu alloy material or a Fe alloy material. The lead frame 30 has a die pad 31 on which the semiconductor chip 20 is mounted and leads 33 connected to the die pad 31. Figure 3 In FIG. 1 , the region indicated by the rectangular dotted line is the region of the die pad 31 which is the mounting region of the semiconductor chip 20 .

[0041] The die pad 31 has a plurality of electrically separated segments 32 that correspond to the plurality of connection terminals 55 of the semiconductor chip 20. The plurality of connection terminals 55 are connected to corresponding segments 32 among the plurality of segments 32. Figure 3 , the connection portion with the connection terminal 55 is indicated by a circular dotted line. The connection terminal 55 is composed of a solder ball. That is, the redistribution wiring 52 of the semiconductor chip 20 and the die pad 31 of the lead frame 30 are electrically connected by solder. In the semiconductor device 10 involved in the present embodiment, no bonding wire is used in the electrical connection between the semiconductor chip 20 and the lead frame 30. In addition, a method in which the connection terminal 55 is not composed of a solder ball can also be applied. In this case, for example, the connection between the redistribution wiring 52 and the die pad 31 can also be performed using a solder paste or a conductive adhesive supplied to the die pad 31.

[0042] The sealing member 40 seals the die pad 31 and the semiconductor chip 20. That is, the die pad 31 and the semiconductor chip 20 are buried inside the sealing member 40. The sealing member 40 is made of a thermosetting epoxy resin. The leads 33 connected to each of the divided pieces 32 of the die pad 31 extend to the outside of the sealing member 40.

[0043] The semiconductor device 10 according to the present embodiment has a QFP configuration in which leads 33 are arranged along four sides of a sealing member 40 formed into a rectangular shape. Figure 3 As shown, the lead 33 is formed into a desired shape.

[0044] Below, refer to Figure 5A to Figure 5H The manufacturing method of the semiconductor device 10 is described. First, a circuit element 22 such as a transistor, a diode, a resistor, or a capacitor is formed on a semiconductor substrate 21 using a known semiconductor manufacturing process. Figure 5A Next, an insulating film 23 made of an insulator such as SiO2 is formed on the circuit formation surface of the semiconductor substrate 21 using a CVD (Chemical Vapor Deposition) method. Figure 5A ). Next, a contact hole is formed at a predetermined position of the insulating film 23 using lithography. Next, a conductive film composed of a conductive material such as Al is formed on the surface of the insulating film 23 using a sputtering method. Thus, a conductive material is embedded in the contact hole formed in the insulating film 23, forming a through hole 25 connected to the circuit element 22. Next, the conductive film is patterned using lithography, thereby forming an electrode 24 ( Figure 5A ).

[0045] Next, a resin such as polyimide or PBO is applied onto the insulating film 23 and then the resin is cured to form an insulating film 51 ( Figure 5B ).

[0046] Next, an opening is formed in the insulating film 51 using a lithography technique. The electrode 24 is exposed in the opening. Next, a conductive film made of a conductor such as Cu is formed to cover the surface of the insulating film 51 using a plating method. Next, the conductive film is patterned using a lithography technique. Thus, a redistribution wiring 52 ( Figure 5C ). The planar size of the redistribution layer 50 composed of the insulating film 51 and the redistribution wiring 52 is the same as the planar size of the semiconductor substrate 21.

[0047] Next, a photosensitive resin is applied to the surface of the insulating film 51, and then the photosensitive resin is cured to form the insulating film 53 ( Figure 5D ).

[0048] Next, an opening is formed in the insulating film 53 using a lithographic technique. The redistribution wiring 52 is partially exposed in the opening. Next, a conductive film made of a conductor such as Cu is formed to cover the surface of the insulating film 53 using a plating method. Next, the conductive film is patterned using a lithographic technique to form a terminal pad 54 ( Figure 5E Next, a connection terminal 55 composed of a solder ball is formed on the terminal pad 54 ( Figure 5E ). After the above steps, the semiconductor chip 20 is manufactured.

[0049] Next, the semiconductor chip 20 is mounted on the die pad 31 of the lead frame 30 and subjected to a reflow process ( Fig. 5F ). Thus, the semiconductor chip 20 and the lead frame 30 are connected through the solder balls constituting the connection terminals 55. That is, the semiconductor chip 20 is connected to the lead frame 30 in a flip chip connection manner. The plurality of connection terminals 55 of the semiconductor chip 20 are respectively connected to the corresponding divided pieces 32 among the plurality of divided pieces 32 of the die pad 31. The redistribution wiring 52 provided in the semiconductor chip 20 is electrically connected to the divided pieces 32 and the leads of the die pad 31.

[0050] Next, the die pad 31 and the semiconductor chip 20 are sealed with a sealing member 40 ( Figure 5G The sealing member 40 is formed, for example, by a transfer method. The transfer method is a sealing method in which a lead frame carrying a semiconductor chip is placed in a potting mold, and a molten resin is filled into the mold cavity and solidified. The die pad 31 and the semiconductor chip 20 are buried inside the sealing member 40. The leads 33 connected to each segment 32 of the die pad 31 extend to the outside of the sealing member 40 ( Figure 5H ).

[0051] As described above, the semiconductor device 10 involved in this embodiment includes: a semiconductor chip 20, which has a redistribution 52; a lead frame 30, which has a core pad 31 carrying the semiconductor chip 20 and a lead 33 connected to the core pad 31, and the redistribution 52 and the core pad 31 are electrically connected by solder or a conductive adhesive; and a sealing component, which seals the semiconductor chip 20.

[0052] The semiconductor chip 20 has a semiconductor substrate 21 on which a circuit element 22 is formed, an insulating film 23 covering the semiconductor substrate 21, an electrode 24 provided on the insulating film 23 and connected to the circuit element 22 and to the redistribution 52, and a connection terminal 55 connected to the redistribution 52. The redistribution 52 is provided on a redistribution layer 50 having the same size as the plane size of the semiconductor substrate 21.

[0053] Figure 6 This is a cross-sectional view comparing the dimensions of the semiconductor device 10 according to the present embodiment with the dimensions of a surface-mount semiconductor device 10X according to a comparative example.

[0054] The semiconductor device 10X involved in the comparative example includes a semiconductor chip 20X, a lead frame 30X, and a sealing member 40X. The lead frame 30X has a die pad 31X and a lead 33X. The semiconductor chip 20X is mounted on the lead frame 30X, and the semiconductor chip 20X and the lead 33X are connected via a bonding wire 60X. In such a surface-mounted package, since the bonding wire 60X is used to connect the semiconductor chip 20X and the lead 33X, the size of the package is significantly larger than the size of the semiconductor chip 20X. In addition, the inductance component generated by the bonding wire 60X may affect the electrical characteristics. In addition, there is a risk of disconnection or peeling of the bonding wire 60X.

[0055] As a package that solves the above problems, CSP is known. CSP is a semiconductor package that does not have bonding wires and has a package size that is approximately the same as the size of the semiconductor chip. In CSP, the semiconductor chip is exposed, so there are concerns about reliability, and there is also a problem that it is not easy to handle.

[0056] On the other hand, according to the semiconductor device 10 according to the embodiment of the disclosed technology, no bonding wire is used for connecting the semiconductor chip 20 and the lead frame 30. Figure 6 As shown, the package size can be made significantly smaller than the semiconductor device 10X according to the comparative example. In addition, no inductance component is generated by the bonding wire. Furthermore, the risk of disconnection or peeling of the bonding wire can be avoided.

[0057] Furthermore, the semiconductor chip 20 according to the present embodiment has a CSP form, but since the semiconductor chip 20 is sealed by the sealing member 40 , the problems of reliability and handling in the conventional CSP are solved.

[0058] The structure of the semiconductor device 10 can be modified in various ways. Figure 7A to Figure 7D 1 and 2 are cross-sectional views showing other structural examples of the semiconductor device 10. Fig. 7A As shown, the side surface of the semiconductor chip 20 may be exposed from the sealing member 40. Thus, the usage amount of the resin as the material of the sealing member 40 can be reduced while ensuring reliability.

[0059] In addition, if Figure 7B As shown, the semiconductor device 10 may also have a QFN (Quad Flat Non-leaded package). In the QFN, electrode pads 34 are used as connection terminals instead of leads. By setting the package form to QFN, the package size can be reduced compared to QFP.

[0060] In addition, if Figure 7C As shown, the semiconductor device 10 may also have a BGA form. In BGA, solder balls 35 are arranged in a grid pattern on the back surface of the package instead of leads. By using a BGA as the package form, the package size can be reduced compared to a QFP.

[0061] In addition, if Fig.7D As shown, the semiconductor device 10 may include a plurality of semiconductor chips 20 . The plurality of semiconductor chips 20 are respectively mounted on a lead frame 30 and sealed by a sealing member 40 .

[0062] Regarding the above embodiment, the following supplementary notes are also disclosed.

[0063] (Note 1)

[0064] A semiconductor device comprising:

[0065] A semiconductor chip having a rewiring pattern;

[0066] a lead frame having a die pad on which the semiconductor chip is mounted and leads connected to the die pad, wherein the redistribution wiring is electrically connected to the die pad by solder or a conductive adhesive; and

[0067] A sealing member seals the semiconductor chip.

[0068] (Note 2)

[0069] A semiconductor device according to Supplementary Note 1, wherein:

[0070] The semiconductor chip has:

[0071] a semiconductor substrate having circuit elements formed thereon;

[0072] an insulating film covering the semiconductor substrate;

[0073] an electrode provided on the insulating film and connected to the circuit element and to the redistribution wiring; and

[0074] a connecting terminal connected to the rewiring,

[0075] The redistribution wiring is provided in a redistribution wiring layer having the same size as a plane size of the semiconductor substrate.

[0076] (Note 3)

[0077] The semiconductor device according to Supplement 1 or Supplement 2, wherein:

[0078] The semiconductor chip has a plurality of connection terminals connected to the redistribution wiring.

[0079] The die pad has a plurality of electrically separated segments corresponding to the plurality of connection terminals, respectively.

[0080] The plurality of connection terminals are respectively connected to corresponding split pieces among the plurality of split pieces.

[0081] (Note 4)

[0082] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0083] A side surface of the semiconductor chip is exposed from the sealing member.

[0084] (Note 5)

[0085] The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein:

[0086] The plurality of semiconductor chips are mounted on the lead frame.

[0087] The sealing member seals a plurality of semiconductor chips.

[0088] (Note 6)

[0089] A method for manufacturing a semiconductor device comprises the following steps:

[0090] preparing a semiconductor chip having redistribution wiring;

[0091] connecting the die pad of a lead frame having a die pad and leads connected to the die pad to the redistribution wiring by solder or a conductive adhesive; and

[0092] The semiconductor chip is sealed by a sealing member.

[0093] Explanation of symbols

[0094] 10: semiconductor device; 20: semiconductor chip; 21: semiconductor substrate; 22: circuit element; 23: insulating film; 24: electrode; 30: lead frame; 31: die pad; 32: dividing sheet; 33: lead; 40: sealing member; 50: redistribution layer; 52: redistribution; 55: connection terminal.

Claims

1. A semiconductor device comprising: A semiconductor chip having a rewiring pattern; A lead frame having a die pad on which the semiconductor chip is mounted and leads connected to the die pad, wherein the redistribution wiring is electrically connected to the die pad by solder or a conductive adhesive; as well as A sealing member seals the semiconductor chip.

2. The semiconductor device according to claim 1, wherein The semiconductor chip has: a semiconductor substrate having circuit elements formed thereon; an insulating film covering the semiconductor substrate; an electrode provided on the insulating film and connected to the circuit element and to the redistribution wiring; and a connecting terminal connected to the rewiring, The redistribution wiring is provided in a redistribution wiring layer having the same size as a plane size of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein The semiconductor chip has a plurality of connection terminals connected to the redistribution wiring. The die pad has a plurality of electrically separated segments corresponding to the plurality of connection terminals, respectively. The plurality of connection terminals are respectively connected to corresponding split pieces among the plurality of split pieces.

4. The semiconductor device according to claim 1, wherein A side surface of the semiconductor chip is exposed from the sealing member.

5. The semiconductor device according to claim 1, wherein The plurality of semiconductor chips are mounted on the lead frame. The sealing member seals a plurality of semiconductor chips.

6. A method for manufacturing a semiconductor device, comprising the following steps: preparing a semiconductor chip having rewiring; connecting the die pad of a lead frame having a die pad and leads connected to the die pad to the redistribution wiring by solder or a conductive adhesive; as well as The semiconductor chip is sealed by a sealing member.

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