MEMS resonator, manufacturing method thereof and electrical product

Abstract

The embodiment of the invention provides an MEMS resonator, a manufacturing method thereof and an electrical product. The MEMS resonator comprises a device structure which comprises a substrate layer, a first cavity located in the substrate layer or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer and a first electrode layer located on the upper side of the piezoelectric layer; wherein the lower side of the substrate layer is provided with a pin, and the pin is electrically connected with the first electrode layer through a first conductive hole penetrating through the substrate layer and a second conductive hole penetrating through the device layer. According to the embodiment of the invention, the size of a chip can be reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a MEMS resonator and a manufacturing method thereof, and an electrical product. Background Art

[0002] Currently, the MEMS oscillator technology with electrostatically driven silicon-based MEMS (Microelectromechanical Systems) resonators as core devices is becoming increasingly mature and is expected to become a substitute for traditional quartz oscillators, thus having smaller size, lower manufacturing cost and higher reliability.

[0003] With the development of piezoelectric thin film materials, compared with electrostatically driven silicon-based MEMS resonators, piezoelectrically driven silicon-based MEMS resonators exhibit lower motional impedance and higher electromechanical coupling coefficient, which is beneficial to reducing the power consumption and phase noise of the oscillator.

[0004] Piezoelectrically driven silicon-based MEMS resonators do not require an electrostatic bias voltage, thereby reducing the error term on the output signal caused by power supply jitter. At the same time, piezoelectrically driven silicon-based MEMS resonators do not require the formation of sub-micron silicon layer slits during processing, which reduces the difficulty of the process, is beneficial to improving the device yield, and is also conducive to further miniaturization of the device. Summary of the invention

[0005] However, the inventors have found that in the current MEMS resonator structure, the signal pin of the upper electrode layer needs to include two parts, one for probe contact during device testing, and the other for bonding with the silicon cap layer; therefore, it is not conducive to reducing the chip size.

[0006] In order to solve at least one of the above problems or other similar problems, the embodiments of the present application provide a MEMS resonator and a manufacturing method thereof, and an electrical product.

[0007] According to a first aspect of an embodiment of the present application, a MEMS resonator is provided, including:

[0008] A device structure, comprising a substrate layer, a first cavity located inside the substrate layer or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, and the pin is electrically connected to the first electrode layer via a first conductive hole penetrating the substrate layer and a second conductive hole penetrating the device layer.

[0009] According to a second aspect of an embodiment of the present application, the MEMS resonator includes:

[0010] A cap structure includes a second cavity, wherein the cap structure is bonded to the device structure on an upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in a thickness direction.

[0011] According to a third aspect of the embodiment of the present application, the device layer is a doped silicon layer, and the doping concentration of at least part of the doped silicon layer is greater than 10 19 cm -3 .

[0012] According to a fourth aspect of the embodiment of the present application, the doping concentration of at least part of the doped silicon layer is greater than 10 20 cm -3 .

[0013] According to a fifth aspect of the embodiment of the present application, the substrate layer has the first conductive hole penetrating the substrate layer in the thickness direction, and the first conductive hole has a first conductive structure insulated from the substrate layer;

[0014] The device layer has a second conductive hole that penetrates the device layer in a thickness direction, and the second conductive hole has a second conductive structure that is insulated from the device layer;

[0015] One end of the first conductive structure is electrically connected to the pin, and the other end of the first conductive structure is electrically connected to one end of the second conductive structure. The other end of the second conductive structure is electrically connected to the first electrode layer via a third conductive structure.

[0016] According to a sixth aspect of the embodiments of the present application, the first conductive structure includes polycrystalline silicon or single crystal silicon, and the resistivity of the polycrystalline silicon or single crystal silicon is lower than 0.05Ω·cm.

[0017] According to a seventh aspect of the embodiments of the present application, the second conductive structure includes polycrystalline silicon or single crystal silicon, and the resistivity of the polycrystalline silicon or single crystal silicon is lower than 0.05Ω·cm.

[0018] According to an eighth aspect of the embodiment of the present application, there is a first insulating layer between the substrate layer and the device layer, and there is also the first insulating layer between the first conductive structure in the first conductive hole and the substrate layer.

[0019] According to a ninth aspect of the embodiment of the present application, a second insulating layer is provided between the second conductive structure and the device layer in the second conductive hole, and the second insulating layer is also at least partially located on the surface of the device layer facing the substrate layer.

[0020] According to the tenth aspect of the embodiment of the present application, there are also a first metal layer and a second metal layer between the device layer and the substrate layer, a portion of the first metal layer is insulated from the rest and electrically connected to the first conductive structure, a portion of the second metal layer is insulated from the rest and electrically connected to the second conductive structure, and the portion of the first metal layer is electrically connected to the portion of the second metal layer.

[0021] According to an eleventh aspect of the embodiment of the present application, a groove penetrating the device layer and the piezoelectric layer is provided between the first cavity and the second cavity.

[0022] According to a twelfth aspect of the embodiment of the present application, there is also a second electrode layer between the device layer and the piezoelectric layer.

[0023] According to a thirteenth aspect of the embodiment of the present application, there is a third insulating layer between the second electrode layer and the third conductive structure.

[0024] According to the fourteenth aspect of the embodiment of the present application, the device structure has at least one first pin for a driving end, and the first pin is electrically connected to the first electrode layer via the first conductive via and the second conductive via, respectively.

[0025] According to a fifteenth aspect of the embodiment of the present application, the device structure further comprises a second pin having an electrical polarity different from that of the first pin,

[0026] The second pin is electrically connected to the device layer via a third conductive via penetrating the substrate layer, or the second pin is electrically connected to the second electrode layer or the device layer via a third conductive via penetrating the substrate layer and a fourth conductive via penetrating the device layer.

[0027] According to a sixteenth aspect of an embodiment of the present application, a method for manufacturing a MEMS resonator is provided, comprising:

[0028] A device structure is formed, the device structure comprising a substrate layer, a first cavity located inside the substrate layer or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, the pin being electrically connected to the first electrode layer via a first conductive hole penetrating the substrate layer and a second conductive hole penetrating the device layer.

[0029] According to a seventeenth aspect of the embodiment of the present application, the method further includes:

[0030] forming a cap structure, the cap structure comprising a second cavity;

[0031] The cap structure is bonded to the device structure on the upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in the thickness direction.

[0032] According to an eighteenth aspect of the embodiment of the present application, forming a device structure includes:

[0033] forming a first conductive structure in the substrate layer;

[0034] forming a first metal layer on the substrate layer; and

[0035] The first cavity is formed inside or on the upper side of the substrate layer.

[0036] According to a nineteenth aspect of the embodiment of the present application, the forming of the device structure further includes:

[0037] forming a second conductive structure in the silicon wafer;

[0038] forming a second metal layer on the lower side of the silicon wafer; and

[0039] The first metal layer and the second metal layer are bonded to form the device layer.

[0040] According to the twentieth aspect of the embodiment of the present application, a portion of the first metal layer is insulated from the rest and electrically connected to the first conductive structure, a portion of the second metal layer is insulated from the rest and electrically connected to the second conductive structure, and the portion of the first metal layer is electrically connected to the portion of the second metal layer.

[0041] According to a twenty-first aspect of the embodiment of the present application, the forming of the device structure further includes:

[0042] forming the piezoelectric layer on the device layer;

[0043] forming the first electrode layer on the upper side of the piezoelectric layer; and

[0044] The first electrode layer is electrically connected to the second conductive structure.

[0045] According to the twenty-second aspect of the embodiment of the present application, the forming of the device structure further includes:

[0046] forming leads on the underside of the substrate layer; and

[0047] The pin is electrically connected to the first conductive structure.

[0048] According to a twenty-third aspect of the embodiment of the present application, there is provided an electrical product, wherein the electrical product has a MEMS resonator as described in any one of the first to fifteenth aspects above.

[0049] One of the beneficial effects of the embodiments of the present application is that the signal pins are led out from one side (lower side) of the substrate layer, and the pins in the first electrode layer (upper electrode) only need to include the part that is contacted by the probe during device testing, and do not need to include the part bonded to the silicon cap. The signal lead-out holes and pins can be located directly below the upper electrode pins, or have a certain overlap with the upper electrode pins, thereby reducing the chip size.

[0050] With reference to the following description and accompanying drawings, the embodiments of the present application are disclosed in detail. It should be understood that the embodiments of the present application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of the present application include many changes, modifications and equivalents.

[0051] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0052] It should be emphasized that the terms “include / comprises / has” when used herein refer to the existence of a feature, an integer, or a component, but do not exclude the existence or addition of one or more other features, integers, or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The above and other objects, features and advantages of the embodiments of the present application will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which:

[0054] Figure 1 is a schematic diagram of a MEMS resonator;

[0055] Figure 2 is a schematic diagram of a MEMS resonator according to an embodiment of the present application;

[0056] Figure 3 is another schematic diagram of a MEMS resonator according to an embodiment of the present application;

[0057] Figure 4 is another schematic diagram of a MEMS resonator according to an embodiment of the present application;

[0058] Figure 5 is another schematic diagram of a MEMS resonator according to an embodiment of the present application;

[0059] Fig. 6A is a schematic diagram of a method for manufacturing a MEMS resonator according to an embodiment of the present application;

[0060] Figure 6B is a schematic diagram of a method for manufacturing a MEMS resonator according to an embodiment of the present application;

[0061] Figure 7is an exemplary diagram of a device structure formed in an embodiment of the present application;

[0062] Figure 8 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0063] Fig. 9 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0064] Fig.10 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0065] Fig.11 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0066] Fig.12 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0067] Fig.13 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0068] Fig.14 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0069] Fig.15 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0070] Fig.16 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0071] Fig.17 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0072] Fig.18 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0073] Fig.19 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0074] Fig. 20 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0075] Fig.21 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0076] Fig. 22 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0077] Fig.23 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0078] Fig.24 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0079] Fig.25 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0080] Fig.26 is an exemplary diagram of manufacturing a MEMS resonator according to an embodiment of the present application;

[0081] Fig. 27 is another exemplary diagram of manufacturing a MEMS resonator according to an embodiment of the present application;

[0082] Fig.28 is another exemplary diagram of manufacturing a MEMS resonator according to an embodiment of the present application;

[0083] Fig.29 is another exemplary diagram of manufacturing a MEMS resonator according to an embodiment of the present application;

[0084] Fig.30 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0085] Fig.31 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0086] Fig.32 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0087] Fig.33 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0088] Fig.34 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0089] Fig.35 is another exemplary diagram of a MEMS resonator according to an embodiment of the present application;

[0090] Fig.36 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0091] Fig.37 yes Fig.36 A top view of

[0092] Fig.38 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0093] Fig.39 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0094] Fig.40is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0095] Fig.41 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0096] Fig.42 is another exemplary diagram of forming a device structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0097] With reference to the accompanying drawings, the above and other features of the present application will become apparent through the following description. In the description and the accompanying drawings, specific embodiments of the present application are specifically disclosed, which show some embodiments in which the principles of the present application can be adopted. It should be understood that the present application is not limited to the described embodiments. On the contrary, the present application includes all modifications, variations and equivalents falling within the scope of the attached claims.

[0098] In the embodiments of the present application, the term "and / or" includes any one and all combinations of one or more of the associated listed terms. The terms "include", "comprises", "has", etc. refer to the existence of the stated features, elements, components or components, but do not exclude the existence or addition of one or more other features, elements, components or components.

[0099] In the embodiments of the present application, the singular forms "a", "the", etc. may include plural forms, and should be broadly understood as "a kind" or "a type" rather than being limited to the meaning of "one"; in addition, the term "said" should be understood to include both singular and plural forms, unless the context clearly indicates otherwise. In addition, the term "according to" should be understood as "at least partially based on...", and the term "based on" should be understood as "at least partially based on...", unless the context clearly indicates otherwise. In addition, the terms "close to" and "far away" in this application are only used to illustrate the relative positional relationship of the components, and do not indicate the size or specific degree of distance. For example, "far away" can also be referred to as "deviate from", etc.

[0100] In addition, in the following description of the present application, for the convenience of explanation, one side of the substrate (also referred to as a base or substrate) is referred to as the lower side or the lower side, the side opposite to the substrate is referred to as the upper side or the upper side, the side close to the center of the resonator is referred to as the inner side, and the side away from the center of the resonator is referred to as the outer side. However, it is worth noting that these are only for the convenience of explanation and do not limit the orientation of the MEMS resonator of the embodiment of the present application during manufacture and use.

[0101] Figure 1 FIG. 1 is a schematic diagram of a MEMS resonator according to an embodiment of the present application, showing the structure of a piezoelectrically driven silicon-based MEMS resonator. Figure 1As shown, 1101 is the substrate layer, 1102 is the lower cavity (close to the device layer side), 1201 is the device layer, 1202 is the piezoelectric layer, 1203 is the upper electrode layer, 1204 is the silicon dioxide bonding layer, 1301 is the silicon cap layer, 1302 is the upper cavity (close to the piezoelectric layer side), 1303 is the metal bonding layer, 1304 is the conductive hole, and 1305 is the external pin.

[0102] like Figure 1 As shown, there is a cavity 1102 located in the substrate layer 1101 below the device layer 1201, and a bonded silicon cap layer 1301 is located above the piezoelectric layer 1202, and there is a conductive hole 1304 for leading out the signal in the silicon cap layer 1301. In this structure, because the surface metal of the pin part that contacts the probe will be damaged, this pin part can no longer be reused for bonding, so the signal pin located in the upper electrode layer 1203 needs to include two parts, one for the probe contact during device testing, and the other for bonding with the silicon cap layer 1301. Therefore, Figure 1 The structure shown is not conducive to chip size reduction.

[0103] The implementation of the embodiments of the present application will be described below with reference to the accompanying drawings.

[0104] The present application provides a MEMS resonator. Figure 2 Schematic diagram of a MEMS resonator according to an embodiment of the present application. Figure 2 As shown, the MEMS resonator comprises:

[0105] The device structure 200 includes a substrate layer 101, a first cavity 102 located inside the substrate layer 101 or on the upper side of the substrate layer 101, a device layer 201 located on the upper side of the substrate layer 101, a piezoelectric layer 202 located on the upper side of the device layer 201, and a first electrode layer 203 located on the upper side of the piezoelectric layer 202; wherein a pin 108 is provided on the lower side of the substrate layer 101, and the pin 108 is electrically connected to the first electrode layer 203 via a first conductive hole 103 penetrating the substrate layer 101 and a second conductive hole 211 penetrating the device layer 201.

[0106] In some embodiments, Figure 2 As shown, the MEMS resonator also includes:

[0107] The cap structure 300 includes a second cavity 302 . The cap structure 300 is bonded to the device structure 200 on the upper side of the first electrode layer 203 . The first cavity 102 and the second cavity 302 at least partially overlap in the thickness direction.

[0108] In some embodiments, the device layer is a doped silicon layer, and the doping concentration of at least a portion of the doped silicon layer is greater than 1019 cm -3 For another example, the doping concentration of at least a portion of the doped silicon layer is greater than 10 20 cm -3 The present application is not limited thereto, and the doping concentration can be adjusted according to specific requirements.

[0109] In the embodiments of the present application, "electrical connection" can be understood as electrical connection or electrical conduction connection through conductive materials, that is, the two electrically connected components can be electrically connected, but it does not limit whether voltage has been applied or whether current is flowing. Those skilled in the art can understand that electrical connection (electrical conduction) is independent of voltage or current state.

[0110] In some embodiments, Figure 2 As shown, the substrate layer 101 has a first conductive hole 103 penetrating the substrate layer 101 in the thickness direction, and the first conductive hole 103 has a first conductive structure 105 insulated from the substrate layer 101; the device layer 201 has a second conductive hole 211 penetrating the device layer 201 in the thickness direction, and the second conductive hole 211 has a second conductive structure 213 insulated from the device layer 201;

[0111] One end of the first conductive structure 105 is electrically connected to the pin 108 , and the other end is electrically connected to one end of the second conductive structure 213 . The other end of the second conductive structure 213 is electrically connected to the first electrode layer 203 via the third conductive structure 208 .

[0112] In some embodiments, Figure 2 As shown, there is a first insulating layer 104 between the substrate layer 101 and the device layer 201 , and there is also a first insulating layer 104 between the first conductive structure 105 in the first conductive hole 103 and the substrate layer 101 .

[0113] In some embodiments, the substrate layer 101 is a single crystal silicon substrate. The first conductive structure 105 and / or the second conductive structure 213 include polycrystalline silicon. For example, the resistivity of the polycrystalline silicon is lower than 0.05Ω·cm. The present application is not limited thereto, and the conductivity may also be other values.

[0114] In some embodiments, the substrate layer 101 is a single crystal silicon substrate, and the first conductive structure 105 and / or the second conductive structure 213 include single crystal silicon, that is, the first conductive structure 105 and / or the second conductive structure 213 and the substrate layer 101 can be made of the same material and have the same resistivity. For example, the resistivity of the single crystal silicon is lower than 0.05Ω·cm. The present application is not limited thereto, and the conductivity can also be other values.

[0115] For example, the monocrystalline silicon or polycrystalline silicon may be doped with B (boron), P (phosphorus), or As (arsenic), and its resistivity may be 0.01Ω·cm, 0.05Ω·cm, 0.001Ω·cm, 0.005Ω·cm, etc. For another example, the second conductive hole 211 contains doped polycrystalline silicon, and the resistivity of the polycrystalline silicon is lower than 0.05Ω·cm. The doping concentration or doping type in the second conductive hole 211 is different from the doping concentration or type of the device layer. For another example, the substance in the second conductive hole 211 is monocrystalline silicon, and its material is the same as that of the device layer.

[0116] In some embodiments, Figure 2 As shown, there are also a first metal layer 106 and a second metal layer 205 between the device layer 201 and the substrate layer 101, a portion of the first metal layer 106 is insulated from the rest and electrically connected to the first conductive structure 105, a portion of the second metal layer 205 is insulated from the rest and electrically connected to the second conductive structure 213, and the portion of the first metal layer 106 is electrically connected to the portion of the second metal layer 205.

[0117] For example, there is no insulating layer between the first metal layer 106 and the second metal layer 205 , and metal-metal bonding is adopted between the substrate layer 101 and the device layer 201 .

[0118] In some embodiments, Figure 2 As shown, a second insulating layer 212 is provided between the second conductive structure 213 in the second conductive hole 211 and the device layer 201 , and the second insulating layer 212 is also at least partially located on the surface of the device layer 201 facing the substrate layer 101 .

[0119] In some embodiments, Figure 2 As shown, a groove 209 penetrating the device layer 201 and the piezoelectric layer 202 is provided between the first cavity 102 and the second cavity 302 .

[0120] In some embodiments, Figure 2 As shown, the device structure 200 has at least one first pin 1081 for a driving end, and the first pin 1081 is electrically connected to the first electrode layer 203 via the first conductive via 103 and the second conductive via 211 respectively.

[0121] In some embodiments, Figure 2 As shown, the device structure 200 further comprises a second pin 1082 (for example, used as a ground terminal) having an electrical polarity different from that of the first pin. The second pin 1082 is electrically connected to the device layer 201 via a third conductive via 401 penetrating the substrate layer 101 .

[0122] For example, Figure 2 As shown, the device structure 200 has a third conductive via 401 , and the third conductive via 401 also has a first conductive structure 105 ; the second pin 1082 is electrically connected to the device layer 201 via the first conductive structure 105 , the first metal layer 106 and the second metal layer 205 .

[0123] like Figure 2 As shown, the device structure 200 may further include an insulating layer 107 , and the cap structure 300 may further include a substrate 301 , a getter layer 306 , an insulating layer 307 , and the like. Figure 2 The structure of the MEMS resonator of the embodiment of the present application is exemplarily shown, but the present application is not limited thereto, and for example, other components may also be included.

[0124] Figure 3 is another schematic diagram of the MEMS resonator of the embodiment of the present application, and Figure 2 The same contents will not be repeated. Figure 3 As shown, the second pin 1082 is electrically connected to the device layer 201 via a third conductive via 401 penetrating the substrate layer 101 and a fourth conductive via 402 penetrating the device layer 201 .

[0125] For example, Figure 3 As shown, the device structure 200 has a third conductive hole 401 and a fourth conductive hole 402, the third conductive hole 401 also has a first conductive structure 105, and the fourth conductive hole 402 has a second conductive structure 213; the second pin 1082 is electrically connected to the device layer 201 via the first conductive structure 105, the first metal layer 106 and the second metal layer 205, the second conductive structure 213, and the third conductive structure 208.

[0126] In some embodiments, a second electrode layer is further provided between the device layer and the piezoelectric layer.

[0127] Figure 4 is another schematic diagram of the MEMS resonator of the embodiment of the present application, and Figure 2 The same contents will not be repeated. Figure 4 As shown, there is also a second electrode layer 210 between the device layer 201 and the piezoelectric layer 202 .

[0128] In some embodiments, Figure 4 As shown, there is a third insulating layer 207 between the second electrode layer 210 and the third conductive structure 208 .

[0129] In some embodiments, Figure 4As shown, the device structure 200 has at least one first pin 1081 for a driving end, and the first pin 1081 is electrically connected to the first electrode layer 203 via the first conductive via 103 and the second conductive via 211 respectively.

[0130] In some embodiments, Figure 4 As shown, the device structure 200 further includes a second pin 1082 (for example, for grounding), and the second pin 1082 is electrically connected to the device layer 201 via a third conductive hole 401 penetrating the substrate layer 101 .

[0131] For example, Figure 4 As shown, the device structure 200 has a third conductive via 401 , and the third conductive via 401 also has a first conductive structure 105 ; the second pin 1082 is electrically connected to the device layer 201 via the first conductive structure 105 , the first metal layer 106 and the second metal layer 205 .

[0132] Figure 5 is another schematic diagram of the MEMS resonator of the embodiment of the present application, and Figure 3 The same contents will not be repeated. Figure 5 As shown, the second pin 1082 is electrically connected to the second electrode layer 210 via a third conductive via 401 penetrating the substrate layer 101 and a fourth conductive via 402 penetrating the device layer 201 .

[0133] For example, Figure 5 As shown, the device structure 200 has a third conductive hole 401 and a fourth conductive hole 402, the third conductive hole 401 also has a first conductive structure 105, and the fourth conductive hole 402 has a second conductive structure 213; via the first conductive structure 105, the first metal layer 106, the second metal layer 205, and the second conductive structure 213, the second pin 1082 is electrically connected to the second electrode layer 210, and then electrically connected to the device layer 201.

[0134] The above describes the structure of the embodiment of the present application, but the present application is not limited thereto. The specific contents of each device or component can also refer to the relevant technology; in addition, Figures 1 to 5 Devices or components not shown, or reduced Figures 1 to 5 One or more devices or components.

[0135] In an embodiment of the present application, signal pins are led out from one side (lower side) of the substrate layer, and the pins in the first electrode layer (upper electrode) only need to include the part that is contacted by the probe during device testing, and do not need to include the part bonded to the silicon cap. The signal lead-out holes and pins can be located directly below the upper electrode pins, or have a certain overlap with the upper electrode pins, thereby reducing the chip size.

[0136] The following further describes the method for manufacturing the MEMS resonator according to the embodiment of the present application.

[0137] Fig. 6A is a schematic diagram of a method for manufacturing a MEMS resonator according to an embodiment of the present application. Fig. 6A As shown, the manufacturing method comprises:

[0138] 601. Form a device structure, the device structure comprising a substrate layer, a first cavity located inside the substrate layer or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, and the pin is electrically connected to the first electrode layer via a first conductive hole penetrating the substrate layer and a second conductive hole penetrating the device layer.

[0139] In some embodiments, Fig. 6A As shown, the manufacturing method also includes:

[0140] 602, forming a cap structure, wherein the cap structure includes a second cavity;

[0141] 603 , bond the cap structure to the device structure on the upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in the thickness direction.

[0142] It is worth noting that the above Fig. 6A The embodiments of the present application are only schematically described, but the present application is not limited thereto. For example, the execution order of the various steps can be appropriately adjusted, and other steps can be added or some steps can be reduced. Those skilled in the art can make appropriate modifications based on the above content, and are not limited to the above attached. Fig. 6A Records of.

[0143] Figure 6B FIG. 1 is a schematic diagram of forming a device structure according to an embodiment of the present application, and exemplarily shows a part of the process of forming a device structure according to an embodiment of the present application. Figure 6B As shown, the method includes:

[0144] 6011, forming a first conductive structure in a substrate layer; and

[0145] 6012, forming a first metal layer on the substrate layer;

[0146] For example, there is a first insulating layer between the first conductive structure and the substrate layer, and the first insulating layer also covers the substrate surface area outside the first conductive structure.

[0147] 6013. Form a first cavity inside or on the upper side of the substrate layer.

[0148] like Figure 6B As shown, the method also includes:

[0149] 6014, forming a second conductive structure in the silicon wafer;

[0150] 6015, forming a second metal layer on the lower side of the silicon wafer; and

[0151] 6016. Bond the first metal layer and the second metal layer to form the device layer.

[0152] For example, a second conductive structure is formed on the wafer where the device layer is located, with an insulating layer between the second conductive structure and the device layer. The substrate layer is bonded to the wafer where the device layer is located through a metal layer, so that the first conductive structure and the second conductive structure are electrically connected through the metal layer.

[0153] In one or more of the above steps, for example, etching and other operations may be performed. A portion of the first metal layer is insulated from the rest and electrically connected to the first conductive structure, a portion of the second metal layer is insulated from the rest and electrically connected to the second conductive structure, and the portion of the first metal layer is electrically connected to the portion of the second metal layer. For specific operations, please refer to the embodiments described below, but the present application is not limited thereto.

[0154] like Figure 6B As shown, the method also includes:

[0155] 6017, forming a piezoelectric layer on the device layer, and forming a first electrode layer on an upper side of the piezoelectric layer; and

[0156] 6018. Electrically connect the first electrode layer to the second conductive structure.

[0157] For example, the wafer where the device layer is located is thinned to expose the other end of the second conductive structure, a piezoelectric layer and a top electrode are formed above the device layer, and the top electrode is electrically connected to the second conductive structure after crossing the piezoelectric layer and / or the insulating layer.

[0158] like Figure 6B As shown, the method also includes:

[0159] 6019, forming pins on the lower side of the substrate layer; and

[0160] 6020, electrically connect the pin to the first conductive structure.

[0161] For example, the back side of the substrate layer may be thinned to expose the first conductive structure, and an insulating layer may be further deposited, and the insulating layer may be etched to expose the first conductive structure, and a metal pin structure may be formed, so that the metal pin is electrically connected to the first conductive structure.

[0162] It is worth noting that the above Figure 6B The embodiments of the present application are only schematically described, but the present application is not limited thereto. For example, the execution order of the various steps can be appropriately adjusted, and other steps can be added or some steps can be reduced. Those skilled in the art can make appropriate modifications based on the above content, and are not limited to the above attached. Figure 6B Records of.

[0163] In some embodiments, the forming of the device structure includes: forming a first conductive hole in the substrate layer that passes through the substrate layer in the thickness direction, the first conductive hole having a first conductive structure insulated from the substrate layer to form the first conductive hole; forming a second conductive hole in the device layer that passes through the device layer in the thickness direction, the second conductive hole having a second conductive structure insulated from the device layer to form the second conductive hole; electrically connecting one end of the first conductive structure to the pin, and the other end to one end of the second conductive structure, and the other end of the second conductive structure is electrically connected to the first electrode layer via a third conductive structure.

[0164] Figure 7 FIG. 1 is an example diagram of a device structure formed in an embodiment of the present application. Figure 7 As shown, firstly, a hole for leading out a signal is formed by etching on the silicon substrate layer 101, and the depth of the hole is generally above 50 um, for example above 100 um, but is not limited to the depth mentioned above.

[0165] The cross-sectional shape of the hole can be any shape such as circular, elliptical, polygonal or a combination thereof, and the number of holes is generally the same as the number of signal ports. For example, there can be three holes, a positive drive terminal, a negative drive terminal, and a ground terminal, or there can be two drive terminals and a ground terminal, or the number can be greater than the number of signal ports, for example: there can be multiple ground terminals, or multiple signal terminals.

[0166] In some embodiments, a first insulating layer is formed between the substrate layer and the device layer, and the first insulating layer is also formed between the first conductive structure in the hole and the substrate layer.

[0167] Figure 8 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Figure 8As shown, a uniform and dense silicon dioxide layer (first insulating layer 104) is formed on the substrate layer 101 by thermal oxidation (eg dry thermal oxidation or wet thermal oxidation), and its thickness is generally less than 2 um, for example, 500 nm or 1 um, but not limited thereto.

[0168] It is worth noting that Figure 8 The silicon dioxide layers illustrated on the left and right sides include the silicon dioxide layers formed on the outer edge of the entire wafer, rather than the silicon dioxide layers formed on the edge of a single chip. There will be multiple chips distributed continuously on the entire wafer.

[0169] Fig. 9 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig. 9 As shown, a doped polysilicon layer (first conductive structure 105) is grown on one side of the hole etched on the substrate layer 101, so that the polysilicon completely fills the hole. The dopant of polysilicon can be phosphorus P, arsenic As, boron B and other elements, and the doping type can be N-type or P-type, and the doping concentration is generally greater than 10 18 cm -3 , for example, greater than 10 19 cm -3 , so that its resistivity is lower than 0.01Ω·cm.

[0170] Fig.10 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.10 As shown, the polysilicon layer on the surface of the substrate layer 101 can be removed by dry etching and / or chemical mechanical polishing (CMP) or the like. Optionally, the silicon dioxide layer on the surface is removed so that the polysilicon layer is left only in the hole, and the surface of the polysilicon layer is flush or substantially flush with the silicon dioxide layer at the edge. For example, the surface of the polysilicon in the hole may be slightly convex or concave, but its edge is flush with the silicon dioxide layer.

[0171] In some embodiments, a first metal layer is formed between the device layer and the substrate layer.

[0172] Fig.11 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.11 As shown, a metal layer (first metal layer 106) can be deposited on the surface of the substrate layer 101 and patterned to pattern the metal layer connected to the hole into a discrete pattern. In this step, the metal layer at the lower cavity position may be etched away first or not.

[0173] The metal layer can be gold, aluminum, germanium, tin, copper and other metals, which are used for subsequent metal-silicon bonding or metal-metal bonding. The metal layer can also be a composite layer of multiple metal materials, and can also include at least one adhesion layer or barrier layer material, such as Ti, TiW, Cr and other materials.

[0174] Fig.12 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.12 As shown, a cavity (first cavity 102) can be etched on the surface of the substrate layer 101, for example, the metal layer, the oxide layer and the silicon substrate material at the position of the first cavity 102 are etched away in sequence. If the metal layer above the lower cavity is etched in the previous step, only the oxide layer and the silicon substrate material at the corresponding position need to be etched away in this step.

[0175] When the resonator works in an out-of-plane vibration mode, i.e., a large vibration amplitude is generated in the thickness direction, a cavity needs to be formed in the substrate layer 101, and its depth can be set according to the vibration amplitude of the resonator, for example, greater than 10um, or greater than 25um, or greater than 50um. Fig.12 As shown, the first cavity 102 may be located in the substrate layer 101 .

[0176] Fig.13 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.13 As shown, a cavity (first cavity 102) may be etched on the surface of the substrate layer 101, for example, the metal layer and the oxide layer at the position of the first cavity 102 are etched away in sequence.

[0177] When the resonator operates in the in-plane vibration mode, that is, the vibration mainly occurs in the horizontal direction, and no large vibration amplitude is generated in the thickness direction, at this time, the cavity can be formed only by etching the metal layer and the oxide layer. Fig.13 As shown, the first cavity 102 may be located on the upper side of the substrate layer 101 .

[0178] Fig.14 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.14 As shown, the silicon wafer (device layer 201) is processed. The silicon wafer is preferably a highly doped silicon material, so that the resonator has better frequency and temperature stability. For example, the dopant is phosphorus (P) or arsenic (As), the doping type is N-type, or the dopant is boron (B), the doping type is P-type, and the doping concentration is 10 19 cm -3 Above, further doping concentration is 10 20 cm -3 Above. Fig.14As shown, a second conductive hole 211 is etched on the wafer, and the position of the second conductive hole 211 corresponds to the position of the first conductive hole 103 on the substrate layer 101 wafer.

[0179] Fig.15 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.15 As shown, a silicon dioxide layer (second insulating layer 212) can be deposited on the wafer by thermal oxidation method, and the thickness of the silicon dioxide layer is generally less than 2 um, for example, 500 nm or 1 um, but not limited thereto.

[0180] Fig.16 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.16 As shown, doped polysilicon (second conductive structure 213) can be deposited on one side of the wafer etched hole so that the polysilicon completely fills the hole. The dopant of the polysilicon can be phosphorus P, arsenic As, boron B and other elements. The doping type can be N-type or P-type, and the doping concentration is generally greater than 10 18 cm -3 , for example, greater than 10 19 cm -3 , so that its resistivity is lower than 0.01Ω·cm.

[0181] Fig.17 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.17 As shown, the polysilicon layer on the surface of the wafer can be removed by dry etching and / or chemical mechanical polishing (CMP) and other methods. Optionally, a portion of the silicon dioxide layer on the surface can be removed so that the polysilicon layer is left only in the hole, and the surface of the polysilicon layer is flush or substantially flush with the silicon dioxide layer at the edge. For example, the surface of the polysilicon in the hole may be slightly convex or concave, but its edge is flush with the silicon dioxide layer.

[0182] Fig.18 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.18 As shown, on one side of the wafer etching hole, the silicon dioxide layer is partially etched open to expose the substrate (device layer 201), and a metal layer (second metal layer 205) is formed on its surface, and then the second metal layer 205 is patterned into a shape corresponding to the first metal layer 106 for bonding. At this time, the substrate (device layer 201) and the grounding conductive hole are electrically connected to each other. If the substrate (device layer 201) and the grounding conductive hole do not need to be electrically connected to each other, the silicon dioxide layer does not need to be partially etched open.

[0183] The second conductive hole 211 and the first conductive hole 103 may have cross-sections of the same size and shape, or may have cross-sections of different sizes and shapes, and their central axes may overlap, or may not overlap, but the projection areas of the holes in the thickness direction overlap, or, the projection areas of the holes in the thickness direction may not overlap, but the metal layers covering the respective holes overlap and do not overlap with the metal layers covering other holes.

[0184] The patterns of the first metal layer 106 and the second metal layer 205 can be exactly the same, or one side can be slightly smaller than the other side, so that the corresponding layers can still be connected when there is a bonding alignment error, or there are special routing positions to ensure that the metal layers with corresponding electrical properties correspond to each other.

[0185] Fig.19 is another exemplary diagram of a device structure formed according to an embodiment of the present application, showing a partial situation of a metal layer observed from above; Fig. 20 FIG. 1 is another exemplary diagram of a device structure formed in an embodiment of the present application, showing a partial situation of observing a metal layer from above. Fig.19 and Fig. 20 As shown, except for the metal layer connected to the signal terminal, the rest of the metal layer is connected to the ground hole, and the metal layer can also be patterned into any shape. For example, in each chip unit, the metal layer of the grounding part is at least connected to form a ring around the cavity.

[0186] Fig.21 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.21 As shown, the silicon wafer (device layer 201) can be bonded to the prepared wafer (substrate layer 101) by metal-metal bonding, such as gold-gold bonding, aluminum-germanium bonding, gold-tin-copper bonding, gold-copper bonding, etc.

[0187] Fig. 22 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig. 22 As shown, the silicon dioxide on the back of the silicon wafer (device layer 201) can be removed by one or more of wet etching, dry etching, grinding, chemical mechanical polishing and the like, and then thinned to the required device layer thickness, and the second conductive hole 211 is exposed.

[0188] Optionally, after the silicon wafer is thinned to the target device layer thickness, phosphorus diffusion can be driven by heat, for example, by introducing POCl3 gas in a nitrogen environment at 1050°C, or by growing a layer of phosphate glass (PSG) material, i.e., a phosphorus-doped silicon oxide layer, on the surface, and then heating to diffuse the P in the device layer and then removing the surface silicon oxide layer, thereby further increasing the phosphorus doping concentration in the device layer, or obtaining a device layer with a doping concentration gradient varying along the thickness direction.

[0189] Fig.23 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.23 As shown, the piezoelectric layer 202 and the top electrode (first electrode layer 203) can be formed in sequence, and the top electrode is patterned. Then, the piezoelectric layer above the second conductive hole 211 is etched to open, exposing the second conductive hole 211 below, but not exposing the device layer 201.

[0190] The piezoelectric material may be: aluminum nitride, doped aluminum nitride, zinc oxide, PZT, lithium niobate, lithium tantalate, etc. It may be a single crystal piezoelectric material or a polycrystalline piezoelectric material. The doping element of doped aluminum nitride may be a rare earth element, such as scandium Sc, yttrium Y, etc.; the doping material may also be a II / XII group element, such as Ca, Mg, Sr, Zn, etc., or a IV / V group element, such as Ti, Zr, Hf, etc. The electrode layer material may be: molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr), etc. and their alloys or composite stacks.

[0191] In addition, the electrode layer material can also be: doped polysilicon, the doping elements can be boron (B), phosphorus (P), arsenic (As), etc., and the doping concentration is generally greater than 10 19 cm -3 As mentioned above, the higher the doping concentration, the lower the sheet resistance of the electrode made of polysilicon will be, and the lower the electrical loss will be.

[0192] Fig.24 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.24 As shown, the corresponding top electrode is connected to the second conductive via 211 through the metal layer (third conductive structure 208), thereby completing the electrical interconnection from the top electrode to the bottom conductive via.

[0193] Fig.25 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.25 As shown, the piezoelectric layer 202, the device layer 201, and the silicon dioxide layer (the second insulating layer 212) may be sequentially etched to form a groove structure, thereby defining the boundary of the suspended shape of the resonator.

[0194] At this point, the device side wafer is ready. The obtained piezoelectric driven silicon-based MEMS resonator can have multiple planar structures, and the corresponding electrode arrangement structures are also different. Its vibration modes can also have multiple modes, such as: in-plane flexural vibration mode (in-plane flexural mode), out-of-plane flexural vibration mode (out-of-plane flexural mode), width extension mode (Width extensional mode, referred to as WE mode), length extension mode (Length extensional mode, referred to as LE mode), Lamé mode, etc., but not limited to the above vibration modes. The resonant frequency that can be achieved can generally cover the range from more than ten kHz to hundreds of MHz.

[0195] Optionally, there may be an insulating layer and a bottom electrode layer between the piezoelectric layer 202 and the device layer 201, wherein the bottom electrode layer is close to one side of the piezoelectric layer, and the insulating layer is close to one side of the device silicon layer. The insulating layer material may be silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, tantalum pentoxide, etc., and the selection range of the bottom electrode layer material is the same as that of the top electrode layer; there may be a passivation layer above the top electrode layer, such as dielectric materials such as aluminum nitride, silicon dioxide, and silicon nitride. Optionally, there may be a temperature compensation layer between any two adjacent layers and on the outermost side, such as silicon dioxide, doped silicon dioxide (e.g., fluorine doped), etc. When there are additional layers, the layers to be continuously etched are determined according to the actual stacking situation.

[0196] Fig.26 FIG. 1 is an example diagram of manufacturing a MEMS resonator according to an embodiment of the present application. Fig.26 As shown, another silicon wafer is used to make a silicon cap, and a cavity (second cavity 302) is formed above each chip. The second cavity 302 is generally larger in lateral dimension than the first cavity 102. Optionally, a getter layer 306 can be formed in the second cavity, and its material can be titanium (Ti) and titanium alloy, zirconium (Zr) and zirconium alloy, etc.

[0197] Fig. 27 FIG. 1 is an example diagram of manufacturing a MEMS resonator according to an embodiment of the present application. Fig. 27 As shown, optionally, there may be a silicon dioxide layer (insulating layer 307) formed by thermal oxidation on the surface of the silicon layer of the silicon cap.

[0198] Fig.28 FIG. 1 is an example diagram of manufacturing a MEMS resonator according to an embodiment of the present application. Fig.28 As shown, the thermal oxide layer on the back of the wafer (substrate layer 101) can be removed, and the wafer can be further thinned by a grinding method so that the first conductive via 103 is exposed on the wafer surface.

[0199] Fig.29FIG. 1 is an example diagram of manufacturing a MEMS resonator according to an embodiment of the present application. Fig.29 As shown, an insulating layer 107 can be formed on the back of the wafer (substrate layer 101), and a window can be etched below the first conductive hole 103 to expose the first conductive hole 103. The insulating layer here can be a dielectric material, such as silicon dioxide, doped silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, tantalum pentoxide, etc., or an organic material, such as epoxy resin, polyimide, etc., but not limited to the listed materials.

[0200] like Figure 2 As shown, pins 108 can be finally formed on the lower side of the substrate layer 101, and the pins 108 are electrically connected to the first conductive vias 103 through the openings of the insulating layer 107. Generally speaking, the material of the pins 108 is gold, copper, aluminum, and their alloys or a stacked combination thereof. Afterwards, the entire wafer is diced to form a number of single chips. If the chips are subsequently assembled by flip-chip, a ball implantation process step can also be performed on the pins 108 before dicing.

[0201] In some embodiments, the device structure has at least two first pins for driving ends, and the first pins are electrically connected to the first electrode layer via the first conductive via and the second conductive via, respectively. The device structure also has a second pin for grounding ends, and the second pin is electrically connected to the device layer via a third conductive via that penetrates the substrate layer.

[0202] The above examples illustrate Figure 2 The fabrication process of the MEMS resonator is shown in Figures 3 to 5 The manufacturing process of the MEMS resonator shown is similar. Figures 3 to 5 Part of the manufacturing process of the MEMS resonator shown is the same as that of the previous embodiment and is not described in detail. Only the differences are described below.

[0203] In some embodiments, the device structure has at least two first pins for driving ends, and the first pins are electrically connected to the first electrode layer via the first conductive via and the second conductive via, respectively. The device structure also has a second pin for grounding ends, and the second pin is electrically connected to the device layer via a third conductive via penetrating the substrate layer and a fourth conductive via penetrating the device layer.

[0204] For example, Figure 3 As shown, the device layer 201 is connected to the grounded first conductive via 103, and can also be realized through a second conductive via 211 and a conductive layer (third conductive structure 208). Figure 3As shown, a conductive hole corresponding to the grounding conductive hole is formed on the substrate silicon (device layer 201), and then the conductive hole and the device layer are electrically connected to each other through the conductive layer. At this time, the piezoelectric layer window above the grounding conductive hole can also be enlarged to expose the conductive hole and the device layer 201 around it at the same time, and then the window area is covered by a metal layer, and the electrical connection between the conductive hole and the device layer 201 can also be achieved.

[0205] In some embodiments, forming the device structure further includes: forming a second electrode layer between the device layer and the piezoelectric layer.

[0206] Fig.30 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.30 As shown, when there is a bottom electrode (second electrode layer 210), as Fig.30 As shown, a bottom electrode (second electrode layer 210), a piezoelectric layer 202 and a top electrode (first electrode layer 203) are formed in sequence, and the top electrode is patterned.

[0207] Fig.31 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.31 As shown, the piezoelectric layer and the bottom electrode above the second conductive hole 211 can be etched to expose the second conductive hole 211 below, as well as the silicon dioxide layer (second insulating layer 212) on the sidewall of the conductive hole and the device layer 201 portion surrounding the conductive hole.

[0208] Fig.32 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.32 As shown, an insulating layer (third insulating layer 207) can be first deposited on the surface of the above-mentioned substrate, and then the third insulating layer 207 above the electrode pin of the top electrode layer and the third insulating layer 207 above the second conductive hole 211 can be removed, and the corresponding top electrodes can be connected through the metal layer (third conductive structure 208), thereby completing the electrical interconnection from the top electrode to the first conductive hole 103.

[0209] Then, the trench structure is etched, the silicon cap is made and finally the Figure 4 Optionally, there may be an insulating layer between the bottom electrode layer and the piezoelectric layer, and the insulating layer material may be silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, tantalum pentoxide, etc. Optionally, there may be a passivation layer above the top electrode layer, such as dielectric materials such as aluminum nitride, silicon dioxide, silicon nitride, etc. Optionally, there may be a temperature compensation layer between any two adjacent layers and on the outermost side, such as silicon dioxide, doped silicon dioxide (for example, fluorine doped), etc.

[0210] for Figure 5The structure shown can be electrically connected to the grounded first conductive hole 103 through a second conductive hole 211 on the substrate silicon (device layer 201). Further, the conductive hole and the device layer 201 are electrically connected to each other through a bottom electrode. At this time, the step of etching the silicon dioxide layer (second insulating layer 212) to open a window can be omitted.

[0211] The above embodiments are merely exemplary of the embodiments of the present application, but the present application is not limited thereto, and appropriate modifications may be made based on the above embodiments. For example, the above embodiments may be used alone, or one or more of the above embodiments may be combined.

[0212] Some variations of the embodiments of the present application are described below.

[0213] Fig.33 is another exemplary diagram of forming a device structure according to an embodiment of the present application, Fig.34 is another example diagram of forming a device structure according to an embodiment of the present application; Fig.10 The situation of modification.

[0214] like Fig.33 As shown, for example, the silicon dioxide layer on the surface can be completely removed by CMP. Fig.34 As shown, an insulating layer 104b (generally silicon dioxide) can be further grown on the surface of the substrate layer 101, and a portion of the surface of the first conductive via 103 is exposed by etching. When a metal bonding layer is subsequently deposited, the metal bonding layer is electrically connected to the exposed first conductive via 103.

[0215] In some embodiments, the first conductive structure may also be a part of the substrate layer, and the second conductive structure may also be a part of the device layer. Fig.35 is another example diagram of a MEMS resonator according to an embodiment of the present application; Figure 3 The situation of modification.

[0216] The following description will be made by taking the formation of the first conductive structure as an example, and the second conductive structure is similar.

[0217] Fig.36 is another exemplary diagram of forming a device structure according to an embodiment of the present application, Fig.37 yes Fig.36 A top view of Fig.38 is another exemplary diagram of forming a device structure according to an embodiment of the present application, Fig.39 is another exemplary diagram of forming a device structure according to an embodiment of the present application, Fig.40 is another example diagram of forming a device structure according to an embodiment of the present application; Figures 7 to 10 The situation of modification.

[0218] In some embodiments, the substrate layer 101 may be a low-resistance single-crystal silicon substrate, wherein the single-crystal silicon resistivity is lower than 0.05Ω·cm. Fig.36 and Fig.37 As shown, an isolation ring structure is etched on the substrate layer 101, so that a part of the first conductive via 103 is laterally isolated from the rest of the substrate. At this time, the material of the first conductive via 103 is the same as that of the substrate layer 101, both of which are single crystal silicon.

[0219] like Fig.38 As shown, a dielectric layer (insulating layer 107) can be further grown to fill the isolation ring structure. The dielectric layer can be a silicon dioxide layer grown by thermal oxidation or LPCVD-TEOS or other methods, or the dielectric layer can be a stack of two dielectric materials, for example, a silicon dioxide layer is first grown on the surface of the substrate, at which time the isolation ring structure is not completely filled, and then polysilicon is grown by LPCVD or other methods to completely fill the isolation ring structure.

[0220] like Fig.39 As shown, the dielectric layer on the surface of the substrate layer 101 can be removed by CMP or dry etching to expose the surface of the substrate layer 101 again. Fig.40 As shown, an insulating layer (generally silicon dioxide) may be grown on the surface of the substrate layer 101 and etched to expose a portion of the surface of the first conductive hole 103 .

[0221] The following Fig.17 A variation of will be described below.

[0222] Fig.41 is another example diagram of forming a device structure according to an embodiment of the present application, showing Fig.17 For example, Fig.41 As shown, during CMP, the silicon dioxide on the surface can be polished away to expose silicon and the second conductive via 211 .

[0223] Fig.42 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.42 As shown, when the device layer 201 is metal-bonded to the substrate layer 101, the graphic edges of the two metal layers (i.e., as shown in 205 and 106) located between the first conductive hole 103 and the second conductive hole 211, or the edge of the second metal layer 205 close to the device layer 201 side, are smaller than the edge of the insulating layer around the second conductive hole 211, and are further smaller than the edge of the second conductive hole 211.

[0224] The embodiment of the present application also provides an electrical product, which has the MEMS resonator as described above. The electrical product includes, for example, a MEMS oscillator, or a communication device using the MEMS resonator, etc., but the present application is not limited thereto.

[0225] It is worth noting that the above is only an exemplary description of the embodiment of the present application, but the embodiment of the present application is not limited thereto, and appropriate modifications can be made on the basis of the above various implementations. In addition, the above is only an exemplary description of each component, but the embodiment of the present application is not limited thereto, and the specific content of each component can also refer to the relevant technology; in addition, components not shown in the figure can be added, or one or more components in the figure can be reduced.

[0226] The embodiments of the present application are described above in conjunction with specific implementation methods, but it should be clear to those skilled in the art that these descriptions are exemplary and are not intended to limit the scope of protection of the embodiments of the present application. Those skilled in the art can make various modifications and variations to the embodiments of the present application based on the spirit and principles of the embodiments of the present application, and these modifications and variations are also within the scope of the embodiments of the present application.

[0227] The preferred embodiments of the present application are described above with reference to the accompanying drawings. Many features and advantages of these embodiments are clear from this detailed description, and therefore the appended claims are intended to cover all such features and advantages of these embodiments that fall within their true spirit and scope. In addition, since many modifications and changes are easily conceivable to those skilled in the art, it is not intended to limit the embodiments of the present application to the precise structures and operations illustrated and described, but all suitable modifications and equivalents that fall within its scope may be covered.

Claims

1. A MEMS resonator, characterized in that: The MEMS resonator comprises: A device structure, comprising a substrate layer, a first cavity located inside the substrate layer or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, and the pin is electrically connected to the first electrode layer via a first conductive hole penetrating the substrate layer and a second conductive hole penetrating the device layer.

2. The MEMS resonator according to claim 1, characterized in that: The MEMS resonator further comprises: A cap structure includes a second cavity, wherein the cap structure is bonded to the device structure on an upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in a thickness direction.

3. The MEMS resonator according to claim 1, characterized in that: The device layer is a doped silicon layer, and the doping concentration of at least part of the doped silicon layer is greater than 10 19 cm -3 .

4. The MEMS resonator according to claim 3, characterized in that: The doping concentration of at least part of the doped silicon layer is greater than 10 20 cm -3 .

5. The MEMS resonator according to claim 1, characterized in that: The substrate layer has the first conductive hole penetrating the substrate layer in the thickness direction, and the first conductive hole has a first conductive structure insulated from the substrate layer; The device layer has a second conductive hole that penetrates the device layer in a thickness direction, and the second conductive hole has a second conductive structure that is insulated from the device layer; One end of the first conductive structure is electrically connected to the pin, and the other end of the first conductive structure is electrically connected to one end of the second conductive structure. The other end of the second conductive structure is electrically connected to the first electrode layer via a third conductive structure.

6. The MEMS resonator according to claim 5, characterized in that: The first conductive structure includes polycrystalline silicon or single crystal silicon, and the resistivity of the polycrystalline silicon or single crystal silicon is lower than 0.05Ω·cm.

7. The MEMS resonator according to claim 5, characterized in that: The second conductive structure includes polycrystalline silicon or single crystal silicon, and the resistivity of the polycrystalline silicon or single crystal silicon is lower than 0.05Ω·cm.

8. The MEMS resonator according to claim 5, characterized in that: There is a first insulating layer between the substrate layer and the device layer, and there is also the first insulating layer between the first conductive structure in the first conductive hole and the substrate layer.

9. The MEMS resonator according to claim 5, characterized in that: A second insulating layer is provided between the second conductive structure and the device layer in the second conductive hole, and the second insulating layer is at least partially located on a surface of the device layer facing the substrate layer.

10. The MEMS resonator according to claim 5, characterized in that: There are also a first metal layer and a second metal layer between the device layer and the substrate layer, a portion of the first metal layer is insulated from the rest and electrically connected to the first conductive structure, a portion of the second metal layer is insulated from the rest and electrically connected to the second conductive structure, and the portion of the first metal layer is electrically connected to the portion of the second metal layer.

11. The MEMS resonator according to claim 2, characterized in that: A groove penetrating the device layer and the piezoelectric layer is provided between the first cavity and the second cavity.

12. The MEMS resonator according to claim 5, characterized in that: A second electrode layer is provided between the device layer and the piezoelectric layer.

13. The MEMS resonator according to claim 12, characterized in that: A third insulating layer is provided between the second electrode layer and the third conductive structure.

14. The MEMS resonator according to claim 1 or 12, characterized in that: The device structure has at least one first pin for a driving end, and the first pin is electrically connected to the first electrode layer via the first conductive via and the second conductive via respectively.

15. The MEMS resonator according to claim 14, characterized in that: The device structure further comprises a second pin having an electrical polarity different from that of the first pin, The second pin is electrically connected to the device layer via a third conductive via penetrating the substrate layer, or the second pin is electrically connected to the second electrode layer or the device layer via a third conductive via penetrating the substrate layer and a fourth conductive via penetrating the device layer.

16. A method for manufacturing a MEMS resonator, characterized in that: The manufacturing method comprises: A device structure is formed, the device structure comprising a substrate layer, a first cavity located inside the substrate layer or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, the pin being electrically connected to the first electrode layer via a first conductive hole penetrating the substrate layer and a second conductive hole penetrating the device layer.

17. The method according to claim 16, characterized in that The manufacturing method further comprises: forming a cap structure, the cap structure comprising a second cavity; The cap structure is bonded to the device structure on the upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in the thickness direction.

18. The method according to claim 16, characterized in that The forming of the device structure comprises: forming a first conductive structure in the substrate layer; forming a first metal layer on the substrate layer; and The first cavity is formed inside or on the upper side of the substrate layer.

19. The method according to claim 18, characterized in that The forming of the device structure further comprises: forming a second conductive structure in the silicon wafer; forming a second metal layer on the lower side of the silicon wafer; and The first metal layer and the second metal layer are bonded to form the device layer.

20. The method according to claim 19, characterized in that A portion of the first metal layer is insulated from the rest and electrically connected to the first conductive structure, a portion of the second metal layer is insulated from the rest and electrically connected to the second conductive structure, and the portion of the first metal layer is electrically connected to the portion of the second metal layer.

21. The method according to claim 20, characterized in that The forming of the device structure further comprises: forming the piezoelectric layer on the device layer; forming the first electrode layer on the upper side of the piezoelectric layer; and The first electrode layer is electrically connected to the second conductive structure.

22. The method according to claim 21, characterized in that The forming of the device structure further comprises: forming leads on the underside of the substrate layer; and The pin is electrically connected to the first conductive structure.

23. An electrical product, characterized in that: The electrical product comprises the MEMS resonator according to any one of claims 1 to 15.

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