Memory and manufacturing method thereof
By designing a memory structure including a regular arrangement of first and second gates, source, drains and channels, forming vertically arranged transistors, the size and density of the existing FeRAM memory is solved. It realizes memory integration and process simplification.
Patent Information
- Application Number
- CN202311084430.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-25
- Publication Date
- 2025-02-25
AI Technical Summary
Existing FeRAM memory has shortcomings in size and density, making it difficult to meet the growing application needs.
By designing a memory structure including a plurality of regular arrangements of first and second gates, source, drain and channels, wherein the first gate and the second gate both surround the channel and form a vertical arrangement , thereby reducing the transistor size and improving memory integration.
The transistor size reduction and memory integration are achieved, the source and drain production difficulty is reduced, and the process is simplified.
Smart Images
Figure CN119521678A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a memory and a manufacturing method thereof. Background Art
[0002] Compared with traditional memory, FeRAM (Ferroelectric RAM) has the characteristics of no data loss after power failure, non-volatility, higher writing speed, overwriting, long life, repeated reading and writing, the number of rereading times can reach billions of times, strong durability, long service life, low standby current, no need for backup battery, no need for charge pump circuit, high reliability, compatibility with CMOS process, wide operating range, strong reliability, etc., and has a very wide application space.
[0003] However, with the development of technology, the requirements for size and density of memory are getting higher and higher, and it is becoming more and more important to design FeRAM with higher density structure. Summary of the invention
[0004] The object of the present invention is to provide a memory and a manufacturing method thereof, which can reduce the size of transistors in the memory and improve the integration of the memory.
[0005] In order to solve the above technical problem, according to a first aspect of the present invention, a memory is provided, comprising:
[0006] A plurality of first grid electrodes are regularly arranged along the second direction and extend along the first direction;
[0007] a plurality of second grid electrodes, regularly arranged along the first direction and extending along the second direction, wherein the first direction intersects with the second direction;
[0008] a source electrode, located at a side of the first gate away from the second gate;
[0009] a drain electrode, located at a side of the second gate away from the first gate;
[0010] A channel is located between the source and the drain, and the first gate and the second gate both surround a portion of the channel, and the first gate and the second gate are used to control different regions of the same channel;
[0011] When the first gate is a word line, the second gate is a bit line; when the first gate is a bit line, the second gate is a word line.
[0012] Optionally, the first direction is perpendicular to the second direction.
[0013] Optionally, the source extends along the first direction and the second direction, the drain extends along the first direction and the second direction, and a plurality of the first gates and a plurality of the second gates share the same source and the same drain.
[0014] Optionally, a first insulating layer is further included, wherein the first insulating layer is located between the source and the drain and is used to isolate the source, the first gate, the second gate and the drain.
[0015] Optionally, a gate oxide layer is further included, which is located on the sidewalls of the channel surrounded by the first gate and the second gate.
[0016] Optionally, a gate oxide layer is further included, which is located on the sidewalls of the channel surrounded by the first gate, the second gate and the first insulating layer between the first gate and the second gate.
[0017] Optionally, the channel is cylindrical.
[0018] Optionally, a second insulating layer is further included, the second insulating layer is located on a side of the drain away from the second gate, a through hole corresponding to the position of the channel is formed in the second insulating layer, and the through hole is filled with metal material to form a metal plug.
[0019] Optionally, a capacitor electrically connected to the metal plug, a metal layer electrically connected to the capacitor, and a metal pad electrically connected to the metal layer are further formed in the second insulating layer, and the second insulating layer exposes the upper surface of the metal pad.
[0020] To solve the above technical problem, according to a second aspect of the present invention, a method for manufacturing a memory is provided, which is used to manufacture the memory as described above. The method for manufacturing the memory comprises the following steps:
[0021] providing a substrate;
[0022] A source, a plurality of first gates, a plurality of second gates, a channel and a drain are formed on the substrate, wherein the plurality of first gates are arranged along a second direction and extend along a first direction, the plurality of second gates are arranged along the first direction and extend along the second direction, and the first direction intersects with the second direction; the first gate, the second gate and the channel are located between the source and the drain, and the first gate and the second gate both surround a portion of the channel.
[0023] To summarize, in the memory and the manufacturing method thereof provided by the present invention, a plurality of first gates are regularly arranged along the second direction and extend along the first direction, and a plurality of second gates are regularly arranged along the first direction and extend along the second direction, wherein the first direction intersects with the second direction; a source is formed on the side of the first gate away from the second gate, a drain is formed on the side of the second gate away from the first gate, a channel is formed between the gate and the drain, and the first gate and the second gate both surround part of the channel, thereby forming a vertically arranged transistor, thereby reducing the size of the transistor and improving the integration of the memory device.
[0024] Furthermore, the source extends along the first direction and the second direction, the drain extends along the first direction and the second direction, and multiple first gates and multiple second gates share the same source and the same drain, that is, the source and the drain are flat-plate-shaped, thereby reducing the difficulty of manufacturing the source and the drain and simplifying the process. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0026] Figure 1 is a cross-sectional view of a memory.
[0027] Figure 2 It is a partial structural diagram of a memory provided by an embodiment of the present invention.
[0028] Figure 3 is a cross-sectional view of a memory provided by an embodiment of the present invention.
[0029] In the attached figure:
[0030] Figure 1 In the figure, 10 is a substrate; 11 is a gate; 12 is a source; 13 is a drain; 14 is a sidewall; 15 is an insulating layer; 16 is a metal plug; 17 is a metal layer; 18 is a capacitor; 19 is a metal pad;
[0031] Figure 2 and Figure 3 In the figure, 100 is a substrate, 110 is a source, 120 is a first insulating layer, 130 is a first gate, 140 is a second gate, 150 is a channel, 160 is a gate oxide layer, 170 is a drain, 180 is a second insulating layer, 190 is a metal plug, 200 is a capacitor, 210 is a metal layer, and 220 is a metal pad. DETAILED DESCRIPTION
[0032] Figure 1 is a cross-sectional view of a memory. Figure 1 As shown, the memory includes: a substrate 10, a gate 11 located on the substrate 10, a source 12 and a drain 13 located in the substrate 10 on both sides of the gate 11, a gate oxide layer (not shown) is formed between the gate 11 and the substrate 10, and sidewalls 14 are formed on both sides of the gate 11.
[0033] An insulating layer 15 is formed on the substrate 10, and the insulating layer 15 covers the gate 11 and the substrate 10. A metal plug 16, a metal layer 17, a capacitor 18 and a metal pad 19 are formed in the insulating layer 15, wherein the metal plug 16 is electrically connected to the gate 11, the source 12 or the drain 13, respectively, the metal layer 17 is electrically connected to the metal plug 16, a capacitor 18 (not limited to the drain 13) is formed between the metal layer 17 electrically connected to the drain 13, and the metal pad 19 is electrically connected to the metal layer 17.
[0034] Figure 1 In the embodiment, the source 12 and the drain 13 are respectively located on the left and right sides of the gate 11, forming a horizontally placed transistor. Taking the 28nm process as an example, the size of the horizontally placed transistor is about 110nm. The inventor has found through research that if the transistor is set to be placed vertically, the size of the transistor can be reduced, thereby improving the integration of the memory.
[0035] After further research by the inventor, the present invention provides a memory, comprising: a plurality of first gates, regularly arranged along a second direction and extending along the first direction; a plurality of second gates, regularly arranged along the first direction and extending along the second direction, wherein the first direction intersects with the second direction; a source, located on a side of the first gate away from the second gate; a drain, located on a side of the second gate away from the first gate; a channel, located between the source and the drain, and passing through the first gate and the second gate; wherein the first gate is a word line or a bit line, and the second gate is a bit line or a word line.
[0036] The present invention also provides a method for manufacturing a memory, comprising the following steps: providing a substrate; forming a source, multiple first gates, multiple second gates, a channel and a drain on the substrate, wherein the multiple first gates are arranged along the second direction and extend along the first direction, and the multiple second gates are arranged along the first direction and extend along the second direction, and the first direction intersects with the second direction; the first gate, the second gate and the channel are located between the source and the drain, and the channel runs through the first gate and the second gate.
[0037] In the memory and the manufacturing method thereof provided by the present invention, a plurality of first gates regularly arranged along the second direction and extending along the first direction are provided, a plurality of second gates regularly arranged along the first direction and extending along the second direction are provided, a source is formed on a side of the first gate away from the second gate, a drain is formed on a side of the second gate away from the first gate, a channel is provided between the gate and the drain, the first gate and the second gate both surround part of the channel, thereby forming a vertically arranged transistor, thereby reducing the size of the transistor and improving the integration of the memory device.
[0038] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0039] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.
[0040] Figure 2 is a partial structural diagram of a memory provided by an embodiment of the present invention, Figure 3 is a cross-sectional view of a memory provided by an embodiment of the present invention. Figure 3 yes Figure 2 Cross-section view on the xz plane. Please refer to Figure 2 and Figure 3 As shown, the memory provided in this embodiment includes:
[0041] A plurality of first gate electrodes 130 are regularly arranged along the second direction y and extend along the first direction x;
[0042] A plurality of second gate electrodes 140 are regularly arranged along the first direction x and extend along the second direction y;
[0043] The source electrode 110 is located at a side of the first gate electrode 130 away from the second gate electrode 140;
[0044] a drain electrode 170 , located at a side of the second gate electrode 140 away from the first gate electrode 130 ;
[0045] A channel 150 is located between the source 110 and the drain 170, and the first gate 130 and the second gate 140 both surround the channel, and the first gate 130 and the second gate 140 are used to control different regions of the same channel;
[0046] When the first gate 130 is a word line, the second gate 140 is a bit line; when the first gate 130 is a bit line, the second gate 140 is a word line.
[0047] In this embodiment, in the third direction z (ie, the vertical direction), the source 110 and the drain 170 are located on both sides of the first gate 130 and the second gate 140 , that is, the transistor thus constructed is arranged along the vertical direction. Figure 1 The size of the transistors arranged horizontally is 110 nm. Figure 2 and Figure 3 The size of the transistors arranged in the vertical direction shown can be reduced to 40 nm, or even smaller. Compared with the prior art, the size of the transistors of the memory provided by the present application is greatly reduced, thereby improving the integration of the memory device.
[0048] Please continue to refer to Figure 2 and Figure 3 As shown, in this embodiment, a plurality of first grid electrodes 130 are regularly arranged in the second direction y, for example, a plurality of first grid electrodes 130 are parallel to each other in the second direction y, and extend in the first direction x. A plurality of second grid electrodes 140 are regularly arranged in the first direction x, for example, a plurality of second grid electrodes 140 are parallel to each other in the first direction x, and extend in the second direction y.
[0049] In this embodiment, the first direction x is perpendicular to the second direction y, and the third direction z is perpendicular to the first direction x and the second direction y. The source 110 extends along the first direction x and the second direction y, that is, extends in a plane formed by the first direction x and the second direction y. The drain 170 is similar to the source 110, and the drain 170 extends along the first direction x and the second direction y, that is, extends in a plane formed by the first direction x and the second direction y. In other words, the source 110 is in the form of a flat plate and covers the substrate 100, and the drain 170 is in the form of a flat plate and covers the second gate 140. Multiple first gates 130 and multiple second gates 140 share the same source 110 and the same drain 170, that is, the source 110 is a common source, and the drain 170 is a common drain.
[0050] Compared with the prior art, the areas of the source 110 and the drain 170 are increased, thereby reducing the difficulty of manufacturing the source and the drain and simplifying the process.
[0051] Of course, in this embodiment, the source 110 is formed on the substrate 100 .
[0052] The memory further includes a first insulating layer 120 , which is located between the source 110 and the drain 170 and is used to isolate the source 110 , the first gate 130 , the second gate 140 and the drain 170 .
[0053] Please refer to Figure 2 As shown, the channel 150 is columnar, preferably cylindrical. The channel 150 is arranged at the position where the first gate 130 and the second gate 140 intersect (that is, the projections on the source 110 intersect), and the channel 150 runs through the second gate 140 and the first gate 130 thereunder.
[0054] Please refer to Figure 2 and Figure 3As shown, the memory further includes a gate oxide layer 160. In this embodiment, the gate oxide layer 160 is located on the outer sidewall of the channel 150 surrounded by the first gate 130, the second gate 140, and the first insulating layer 120 between the first gate 130 and the second gate 140. In another embodiment of the present invention, the gate oxide layer 160 may be located only on the outer sidewall of the channel 150 surrounded by the first gate 130 and the second gate 140. When the gate oxide layer 160 is also disposed on the sidewall of the channel 150 surrounded by the first insulating layer 120 between the first gate 130 and the second gate 140, a strong voltage needs to be passed between the source 110 and the drain 170 so that the channel 150 can be turned on. When the gate oxide layer 160 is disposed only on the sidewall of the channel 150 surrounded by the first gate 130 and the second gate 140, the voltage requirement does not need to be too high, and the conduction of the channel 150 can be controlled by the first gate 130 or the second gate 140. The present invention can select the position of the gate oxide layer 160 according to actual needs.
[0055] In this embodiment, the transistor is turned on only when the first gate 130 and the second gate 140 are turned on at the same time. The memory can be turned on by using the first gate 130 as a word line and the second gate 140 as a bit line, or by using the first gate 130 as a bit line and the second gate 140 as a word line, and the purpose of controlling the memory can be achieved by row selection or column selection (i.e., using the two gates as word lines or bit lines).
[0056] Please refer to Figure 3 As shown, the memory further includes a second insulating layer 180, which is located on the drain 170, that is, located on the side of the drain 170 away from the second gate 140. A through hole corresponding to the position of the channel 150 is formed in the second insulating layer 180, that is, the projection of the through hole on the substrate 100 coincides with or partially coincides with the projection of the groove 150 on the substrate 100. The through hole is filled with a metal material to form a metal plug 190.
[0057] The second insulating layer 180 also includes a capacitor 200 electrically connected to the metal plug 190. The capacitor 200 may include a first electrode, a dielectric layer and a second electrode. The dielectric layer may be a ferroelectric layer, a magnetic layer or other material layer known to those skilled in the art.
[0058] A metal layer 210 electrically connected to the capacitor 200 is formed in the second insulating layer 180, and the metal layer 210 may include multiple metal layers. A metal pad 220 electrically connected to the metal layer 210 is formed in the second insulating layer 180, and the second insulating layer 180 exposes the upper surface of the metal pad 220, that is, the upper surface of the second insulating layer 180 is flush with the upper surface of the metal pad 220.
[0059] In the memory provided by the present invention, a plurality of first gates 130 are regularly arranged along a second direction y and extend along a first direction x, and a plurality of second gates 140 are regularly arranged along the first direction x and extend along the second direction y, wherein the first direction x intersects with the second direction y; a source 110 is formed on a side of the first gate 130 away from the second gate 140, a drain 170 is formed on a side of the second gate 140 away from the first gate 130, a channel 150 is formed between the source 110 and the drain 170, and the channel 150 runs through the first gate 130 and the second gate 140, thereby forming a vertically arranged transistor, thereby reducing the size of the transistor and improving the integration of the memory device.
[0060] Furthermore, the source 110 extends along the first direction x and the second direction y, the drain 170 extends along the first direction x and the second direction y, and a plurality of the first gates 130 and a plurality of the second gates 140 share the same source 110 and the same drain 170, that is, the source and the drain are flat-plate-shaped, thereby reducing the difficulty of manufacturing the source and the drain and simplifying the process.
[0061] Accordingly, the present invention also provides a method for manufacturing a memory, which is used to manufacture the memory as described above. The method for manufacturing the memory comprises:
[0062] Step S1: providing a substrate;
[0063] Step S2: forming a source, a plurality of first gates, a plurality of second gates, a channel and a drain on the substrate, wherein the plurality of first gates are arranged along the second direction and extend along the first direction, the plurality of second gates are arranged along the first direction and extend along the second direction, and the first direction intersects with the second direction; the first gate, the second gate and the channel are located between the source and the drain, and the first gate and the second gate both surround part of the channel.
[0064] In step S1, refer to Figure 2 and Figure 3As shown, a substrate 100 is provided. The material of the substrate 100 may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, etc., or may be silicon on insulator, germanium on insulator; or may be other materials, such as III-V compounds such as gallium arsenide. The present invention is not limited to this.
[0065] In step S2, please refer to Figure 2 and Figure 3 As shown, a source 110, a plurality of first gates 130, a plurality of second gates 140, a channel 150 and a drain 170 are formed on the substrate 100, wherein the plurality of first gates 130 are arranged along the second direction y and extend along the first direction x, the plurality of second gates 140 are arranged along the first direction x and extend along the second direction y, and the first direction x intersects with the second direction y; the first gate 130, the second gate 140 and the channel 150 are located between the source 110 and the drain 170, and the first gate 130 and the second gate 140 both surround a portion of the channel 150.
[0066] Exemplarily, the source electrode 110 is first formed on the substrate 100, and then a first insulating layer 120 of partial thickness is formed on the source electrode 110, and then a first gate material layer is formed on the first insulating layer 120, and then the first gate material layer is etched to form a plurality of first gates 130 (for example, a photoresist layer can be formed on the first gate material layer, and the photoresist layer is exposed and developed to form a patterned photoresist layer, and the first gate material layer is etched using the patterned photoresist layer as a mask until the first insulating layer 120 is exposed). Then, a first insulating layer 120 of partial thickness is formed on the first gate 130, and the first insulating layer 120 covers the first gate 130 and fills the gap between adjacent first gates 130 to connect with the first insulating layer 120 formed previously. Then, a second gate material layer is formed on the first insulating layer 120, and the second gate material layer is etched to form multiple second gates 140. Then, a partial thickness of the first insulating layer 120 is formed to cover the second gates 140 and fill the gaps between adjacent second gates 140 and connect to the first insulating layer 120 formed previously.
[0067] Next, the first insulating layer 120 , the second gate 140 , and the first gate 130 may be etched to form a groove exposing the source 110 , a gate oxide layer 160 may be formed on the sidewall of the groove, and a channel 150 may be formed in the groove. Thereafter, the drain 170 may be formed on the first insulating layer 120 .
[0068] After forming the drain electrode 170 , the method further includes: forming a second insulating layer 180 on the drain electrode 170 , and forming a metal plug corresponding to the position of the channel 150 in the second insulating layer 180 .
[0069] 190, and then forming a capacitor 200 electrically connected to the metal plug 190, a metal layer 210 electrically connected to the capacitor 200, and a metal pad 220 electrically connected to the metal layer 210 in the second insulating layer 180. The second insulating layer 180 exposes the upper surface of the metal pad 220. Specifically, the second insulating layer 180 with a partial thickness may be formed, the metal plug 190 is formed in the second insulating layer 180, and then the second insulating layer 180 with a partial thickness is formed, and the capacitor 200 electrically connected to the metal plug 190 is formed in the second insulating layer 180, and then the metal layer 210 and the metal pad 220 are formed in sequence.
[0070] It should be noted that the present invention only provides one manufacturing method for forming the above-mentioned memory, and other manufacturing methods can also be used to manufacture the above-mentioned memory, and the present invention is not limited to this.
[0071] To summarize, in the memory and the manufacturing method thereof provided by the present invention, a plurality of first gates are regularly arranged along the second direction and extend along the first direction, and a plurality of second gates are regularly arranged along the first direction and extend along the second direction, wherein the first direction intersects with the second direction; a source is formed on the side of the first gate away from the second gate, a drain is formed on the side of the second gate away from the first gate, a channel is formed between the gate and the drain, and the first gate and the second gate both surround part of the channel, thereby forming a vertically arranged transistor, thereby reducing the size of the transistor and improving the integration of the memory device.
[0072] Furthermore, the source extends along the first direction and the second direction, the drain extends along the first direction and the second direction, and multiple first gates and multiple second gates share the same source and the same drain, that is, the source and the drain are flat-plate-shaped, thereby reducing the difficulty of manufacturing the source and the drain and simplifying the process.
[0073] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A memory, characterized in that: include: A plurality of first grid electrodes are regularly arranged along the second direction and extend along the first direction; a plurality of second grid electrodes, regularly arranged along the first direction and extending along the second direction, wherein the first direction intersects with the second direction; a source electrode, located at a side of the first gate away from the second gate; a drain electrode, located at a side of the second gate away from the first gate; A channel is located between the source and the drain, and the first gate and the second gate both surround a portion of the channel, and the first gate and the second gate are used to control different regions of the same channel; When the first gate is a word line, the second gate is a bit line; when the first gate is a bit line, the second gate is a word line.
2. The memory according to claim 1, characterized in that: The first direction is perpendicular to the second direction.
3. The memory according to claim 1, characterized in that: The source electrode extends along the first direction and the second direction, the drain electrode extends along the first direction and the second direction, and a plurality of the first gate electrodes and a plurality of the second gate electrodes share the same source electrode and the same drain electrode.
4. The memory according to any one of claims 1 to 3, characterized in that: The invention also includes a first insulating layer, which is located between the source and the drain and is used to isolate the source, the first gate, the second gate and the drain.
5. The memory according to claim 4, characterized in that: It also includes a gate oxide layer located on the sidewall of the channel surrounded by the first gate and the second gate.
6. The memory according to claim 4, characterized in that: It also includes a gate oxide layer, which is located on the first gate, the second gate and the sidewall of the channel surrounded by the first insulating layer between the first gate and the second gate.
7. The memory according to any one of claims 1 to 3, characterized in that: The channel is cylindrical.
8. The memory according to any one of claims 1 to 3, characterized in that: It also includes a second insulating layer, which is located on a side of the drain away from the second gate. A through hole corresponding to the position of the channel is formed in the second insulating layer, and the through hole is filled with metal material to form a metal plug.
9. A memory according to claim 8, characterized in that: A capacitor electrically connected to the metal plug, a metal layer electrically connected to the capacitor, and a metal pad electrically connected to the metal layer are also formed in the second insulating layer, and the second insulating layer exposes the upper surface of the metal pad.
10. A method for manufacturing a memory, characterized in that: Used to manufacture a memory as claimed in any one of claims 1 to 9, the manufacturing method comprising: providing a substrate; A source, a plurality of first gates, a plurality of second gates, a channel and a drain are formed on the substrate, wherein the plurality of first gates are arranged along a second direction and extend along a first direction, the plurality of second gates are arranged along the first direction and extend along the second direction, and the first direction intersects with the second direction; the first gate, the second gate and the channel are located between the source and the drain, and the first gate and the second gate both surround a portion of the channel.