Display device

Abstract

The invention relates to a display device. According to one or more embodiments of the present disclosure, a display device includes a driving circuit, a display panel over the driving circuit in a first direction, and a heat dissipation layer between the driving circuit and the display panel and including chambers and a piezoelectric element in at least one of the chambers, the piezoelectric element is configured to deform in a first direction or in a direction opposite the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0106692 filed in the Korean Intellectual Property Office on August 16, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device and a semiconductor device. Background Art

[0004] A head mounted display (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet to form a focus at a close distance in front of the user's eyes. The head mounted display can realize virtual reality (VR) or augmented reality (AR).

[0005] The head-mounted display magnifies the image displayed on the small display device by using a plurality of lenses and displays the magnified image. Therefore, the display device suitable for the head-mounted display can appropriately provide a high-resolution image, for example, an image with a resolution of 3000PPI (pixels per inch) or more. For this reason, an organic light-emitting diode on silicon (OLEDoS), which is a high-resolution small organic light-emitting display device, is used as a display device applied to the head-mounted display. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is located on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is positioned. Summary of the invention

[0006] Aspects of the present disclosure provide a display device capable of reducing the size of a heat dissipation layer and noise generated during a heat dissipation operation.

[0007] According to one or more embodiments of the present disclosure, a display device includes a driving circuit, a display panel above the driving circuit along a first direction, and a heat dissipation layer, the heat dissipation layer being between the driving circuit and the display panel and including a chamber and a piezoelectric element in at least one of the chambers, the piezoelectric element being configured to deform along the first direction or in a direction opposite to the first direction.

[0008] The heat dissipation layer may further include a lower plate adjacent to the driving circuit, an upper plate adjacent to the display panel, and an intermediate plate between the lower plate and the upper plate and defining a through hole.

[0009] The chamber may include a first chamber between the lower plate and the middle plate and a second chamber between the middle plate and the upper plate.

[0010] The lower plate may define a through hole penetrating the lower plate, wherein the heat dissipation layer further includes a first side plate connecting one edge of the lower plate to one edge of the middle plate, a second side plate connecting another edge of the lower plate to another edge of the middle plate, a third side plate connecting one edge of the middle plate to one edge of the upper plate, and an opening between another edge of the middle plate and another edge of the upper plate.

[0011] The piezoelectric element may overlap the through hole of the intermediate plate.

[0012] The heat dissipation layer may further include a support member in at least one of the chambers to support the piezoelectric element.

[0013] The support may define a through hole penetrating the support in a second direction substantially perpendicular to the first direction.

[0014] The display device may further include a heat conductive layer between the display panel and the heat dissipation layer.

[0015] The display device may further include a metal layer between the heat conductive layer and the heat dissipation layer.

[0016] The display device may further include a circuit board between the driving circuit and the heat dissipation layer.

[0017] The heat dissipation layer may further include a first protrusion defined by the lower plate in the first chamber and a second protrusion defined by the upper plate in the second chamber.

[0018] The heat dissipation layer may further include a first valve overlapping the through hole of the lower plate in the first chamber and a second valve overlapping the through hole of the middle plate in the second chamber.

[0019] The second valve may overlap the piezoelectric element.

[0020] The lower plate may include a plurality of sub-lower plates including different corresponding materials, wherein the upper plate includes a plurality of sub-upper plates including different corresponding materials.

[0021] One of the sub-lower panels overlapping with the driving circuit may include a metal material, wherein one or more of the remaining sub-lower panels include a plastic material, wherein one of the sub-upper panels overlapping with the display panel includes a metal material, and wherein one or more of the remaining sub-upper panels include a plastic material.

[0022] The heat dissipation layer may also include a first side plate connecting another edge of the lower plate to another edge of the middle plate and a second side plate connecting one edge of the middle plate to one edge of the upper plate, wherein the heat dissipation layer defines a first opening between one edge of the lower plate and one edge of the middle plate and a second opening between another edge of the middle plate and another edge of the upper plate.

[0023] The heat dissipation layer may also include a first side plate connecting one edge of the lower plate to one edge of the middle plate, a second side plate connecting another edge of the lower plate to another edge of the middle plate and defining a through hole, a third side plate connecting one edge of the middle plate to one edge of the upper plate, and a fourth side plate connecting another edge of the middle plate to another edge of the upper plate and defining a through hole.

[0024] The middle plate may include a first middle plate located between the lower plate and the upper plate and defining the through hole, and a second middle plate located between the first middle plate and the upper plate and defining the through hole.

[0025] The chamber may include a first chamber between the lower plate and the first middle plate, a second chamber between the first middle plate and the second middle plate, and a third chamber between the second middle plate and the upper plate.

[0026] The heat dissipation layer may also include a first side plate connecting one edge of the lower plate to one edge of the first middle plate, a second side plate connecting another edge of the first middle plate to another edge of the second middle plate, and a third side plate connecting one edge of the second middle plate to one edge of the upper plate, and wherein the heat dissipation layer defines a first opening between another edge of the lower plate and another edge of the first middle plate, a second opening between one edge of the first middle plate and one edge of the second middle plate, and a third opening between another edge of the second middle plate and another edge of the upper plate.

[0027] The piezoelectric element may be connected to an external power source.

[0028] The piezoelectric element may be connected to a drive circuit.

[0029] According to the display device of the present disclosure, it is possible to reduce both the size of the heat dissipation layer and the noise generated during the heat dissipation operation.

[0030] Aspects of the present disclosure are not limited to the above-described aspects, and other aspects not described herein will become apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments;

[0033] Figure 2 It is shown Figure 1 A layout diagram of an example of a display panel shown in ;

[0034] Figure 3is a block diagram showing a display device according to one or more embodiments;

[0035] Figure 4 is an equivalent circuit diagram of a first pixel according to one or more embodiments;

[0036] Figure 5 is a layout diagram showing pixels of a display area according to one or more embodiments;

[0037] Figure 6 is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA';

[0038] Figure 7 is a perspective view showing a head mounted display device according to one or more embodiments;

[0039] Figure 8 It is shown Figure 7 An exploded perspective view of an example of a head mounted display device;

[0040] Fig. 9 is a perspective view showing a head mounted display device according to one or more embodiments;

[0041] Fig.10 is a cross-sectional view of a display device according to one or more embodiments;

[0042] Fig.11 yes Fig.10 A plan view of a piezoelectric element, a support member, and a through hole of a portion A;

[0043] Fig.12 yes Fig.10 an enlarged cross-sectional view of a portion A of the

[0044] Fig.13 Yes Fig.12 A timing diagram of AC power supplied to the piezoelectric element;

[0045] Fig.14 and Fig.15 It is used to explain Fig.12 A diagram of the operation of a piezoelectric element;

[0046] Fig.16 and Fig.17 Is used to describe Fig.10 a diagram showing the operation of the device;

[0047] Fig.18 is a cross-sectional view of a display device according to one or more embodiments;

[0048] Fig.19 is a cross-sectional view of a display device according to one or more embodiments;

[0049] Fig. 20 is a cross-sectional view of a display device according to one or more embodiments;

[0050] Fig.21 is a cross-sectional view of a display device according to one or more embodiments;

[0051] Fig. 22 is a cross-sectional view of a display device according to one or more embodiments;

[0052] Fig.23 is a cross-sectional view of a display device according to one or more embodiments;

[0053] Fig.24 yes Fig.23 an exploded plan view of a first valve;

[0054] Fig.25 and Fig.26 It is used to explain Fig.23 a diagram showing the operation of the device;

[0055] Fig. 27 is a cross-sectional view of a display device according to one or more embodiments;

[0056] Fig.28 is a cross-sectional view of a display device according to one or more embodiments;

[0057] Fig.29 and Fig.30 It is used to explain Fig.28 a diagram showing the operation of the device;

[0058] Fig.31 is a cross-sectional view of a display device according to one or more embodiments; and

[0059] Fig.32 is a cross-sectional view of a display device according to one or more embodiments. DETAILED DESCRIPTION

[0060] By referring to the detailed description and drawings of the embodiments, various aspects of some embodiments of the present disclosure and methods for realizing these aspects can be more easily understood. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for fully understanding various aspects of the present disclosure for those of ordinary skill in the art can be omitted. Unless otherwise stated, the same reference numerals, characters or combinations thereof represent the same elements throughout the drawings and written descriptions, and therefore their repeated descriptions can be omitted.

[0061] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments described herein. The use of "can", "may" or "may not" when describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interlocks and drives are possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0062] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0063] Various embodiments are described herein with reference to schematic cross-sectional illustrations as embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations caused by, for example, manufacturing techniques and / or tolerances are expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but include deviations in shapes caused by, for example, manufacturing.

[0064] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0065] Spatial relative terms, such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc., can be used in this article for the convenience of explanation, to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It should be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to also cover the different orientations of the device in use or in operation. For example, if the device in the figure is turned over, the element described as "below", "below" or "below" other elements or features will be subsequently oriented to "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the orientations of above and below. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged at the upper side or lower side of the second part, without being limited to its upper side based on the direction of gravity.

[0066] In addition, the phrase "in a plan view" means when observing the object portion from above, and the phrase "in a schematic cross-sectional view" means when observing the schematic cross-section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object may be located above or below the second object or on the side of the second object, and vice versa. Additionally, the term "overlap" may include stacking, facing or facing, extending on ..., covering or partially covering, or any other suitable term that will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include the meaning of any other suitable corresponding words such as "separated from ... "or "set aside ... "or "offset from ... "and any other suitable corresponding words that will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although still facing each other, the first object and the second object may be understood to be indirectly opposite to each other.

[0067] It should be understood that when an element, layer, region, or component is referred to as being "formed on," "located on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component can be directly formed on, located on, connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, located on, connected to, or indirectly coupled to another element, layer, region, or component such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may collectively mean direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or electrically coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, and / or the like. When describing embodiments, unless explicitly described as being directly connected, the statement of connection indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or is located on another component without intermediate components.

[0068] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the situation that the part is "directly" located "below" another part, but also includes the situation that there is another part between the part and the other part. At the same time, other expressions such as "between...", "directly between...", or "adjacent to" and "directly adjacent to" that describe the relationship between parts can be interpreted similarly. It should be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0069] For the purposes of this disclosure, expressions such as "at least one of..." or "any of..." or "one or more of...", when following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X; only Y; only Z; any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ; or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list.

[0070] It should be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or parts, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, area, region, layer, part or part from another element, member, component, area, region, layer, part or part. Therefore, the first element, component, area, layer or part described below can be referred to as the second element, component, area, layer or part, without departing from the spirit and scope of the present disclosure. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish different categories or sets of elements. For the sake of brevity, the terms "first", "second", etc. can respectively represent "first category (or first set)", "second category (or second set)", etc.

[0071] In the example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted as a broader meaning. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first, second, and / or third directions.

[0072] The terms used herein are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It should also be understood that the terms "comprise", "comprising", "have", "having", "include" and "including" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0073] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation rather than as terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the errors associated with the measurement and the measurement of a specific amount (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated values ​​and mean within an acceptable deviation range for a specific value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure".

[0074] In some embodiments, well-known structures and devices are described in the accompanying drawings in relation to one or more functional blocks (e.g., block diagrams), units and / or modules to avoid making various embodiments unnecessary obscurity. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and optionally, blocks, units and / or modules implemented by microprocessors or other similar hardware can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform functions different from those of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules can be physically separated into two or more separate blocks, units and / or modules that interact with each other without departing from the scope of this disclosure. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0075] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0076] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 It is shown Figure 1 Layout diagram of an example of a display panel shown in . Figure 3 is a block diagram illustrating a display device according to one or more embodiments.

[0077] Reference Figure 1 and Figure 2, the display device 10 according to one or more embodiments is a device for displaying a moving image or a still image. The display device 10 according to one or more embodiments may be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), or the like. For example, the display device 10 may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 may be applied to a smart watch, a watch phone, a head mounted display (HMD) for realizing virtual reality and augmented reality, and the like.

[0078] The display device 10 according to one or more embodiments includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , and a driving circuit 450 .

[0079] The display panel 100 may have a planar shape similar to a quadrilateral shape. For example, the display panel 100 may have a planar shape similar to a quadrilateral shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, a corner where a short side in the first direction DR1 intersects a long side in the second direction DR2 may be a right angle or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the present specification is not limited thereto.

[0080] like Figure 2 As shown in FIG. 1 , the display panel 100 includes a display area DAA for displaying an image and a non-display area NDA where no image is displayed.

[0081] like Figure 3 As shown in the figure, the display area DAA includes a plurality of pixels PX, a plurality of scan lines SL (including a plurality of write scan lines GWL, a plurality of control scan lines GCL and a plurality of bias scan lines EBL), a plurality of emission control lines EL (including a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2) and a plurality of data lines DL.

[0082] Each of the plurality of pixels PX includes a light emitting element that emits light. The plurality of pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 while being arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 while being arranged in the first direction DR1.

[0083] like Figure 5 and Figure 6 As shown in FIG, each of the plurality of unit pixels UPX includes a plurality of pixels PX1, PX2, and PX3. Figure 4 As shown in FIG. 1 , the plurality of pixels PX1, PX2, and PX3 may include a plurality of pixel transistors that may be formed by a semiconductor process, and may be located (for example, as used herein, “located on” may mean “located above”) on a semiconductor substrate SSUB (see FIG. 1 ). Figure 6 ). For example, a plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0084] Each of the plurality of pixels PX1, PX2, and PX3 may be connected to one of the plurality of write scan lines GWL, one of the plurality of control scan lines GCL, one of the plurality of bias scan lines EBL, one of the plurality of first emission control lines EL1, one of the plurality of second emission control lines EL2, and one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 may receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and may emit light from the light emitting element according to the data voltage.

[0085] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0086] The scan driving area SDA may be an area in which the scan driver 610 and the emission driver 620 are located. Figure 2 6 shows that the scan driver 610 is located on the left side of the display area DAA and the emission driver 620 is located on the right side of the display area DAA, but the present specification is not limited thereto. For example, the scan driver 610 and the emission driver 620 may each be located on both the left and right sides of the display area DAA.

[0087] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see Figure 6 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed by CMOS.

[0088] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit (or timing controller) 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and may sequentially output them to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and may sequentially output them to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and may sequentially output them to the bias scan line EBL.

[0089] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate first emission control signals according to the emission timing control signal ECS, and may sequentially output them to the first emission control line EL1. The second emission control driver 622 may generate second emission control signals according to the emission timing control signal ECS, and may sequentially output them to the second emission control line EL2.

[0090] The data driving area DDA may be an area in which the data driver 700 is located. The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see Figure 6 For example, the plurality of data transistors may be formed of CMOS.

[0091] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0092] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. In one or more embodiments, each of the plurality of pads PD may be exposed without being covered by the cover layer CVL (see Figure 6) and polarizer cover.

[0093] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be located on one surface of the display panel 100, for example, on the rear surface thereof. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a graphite layer having relatively high thermal conductivity or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al).

[0094] The circuit board 300 may be electrically connected to the plurality of pads PD in the pad area PDA of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board having a flexible material, or a flexible film. Figure 1 100, but the circuit board 300 may be curved or bendable. In this case, one end of the circuit board 300 may be located on the rear surface of the display panel 100. The one end of the circuit board 300 may be an end opposite to the other end of the plurality of pads PD of the circuit board 300 connected to the pad area PDA of the display panel 100 by using a conductive adhesive member.

[0095] The driving circuit 450 may include a timing control circuit 400 and a power supply circuit (or power supply unit) 500 .

[0096] The timing control circuit 400 may receive digital video data DATA and a timing signal input from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610, and may output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0097] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and may supply them to the display panel 100. Figure 4 A description of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT is provided.

[0098] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and may be attached to one side of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0099] The driving circuit 450 may include all of the scan driver 610, the emission driver 620, the data driver 700, the timing control circuit 400, and the power supply circuit 500, or may selectively include only some of them. At this time, the power supply circuit 500 may include a gamma driver, which may provide a value that determines the correlation between the brightness (gray scale) of the data signal input to the display device 10 and the brightness of the image displayed on the screen. On the other hand, the gamma driver may be provided separately from the power supply circuit 500, and in this case, in addition to the above-mentioned scan driver 610, the emission driver 620, the data driver 700, the timing control circuit 400, and the power supply circuit 500, the driving circuit 450 may also include a gamma driver.

[0100] In addition, similar to the scan driver 610, the emission driver 620, and the data driver 700, the driving circuit 450 may be located in a circuit area of ​​the non-display area NDA of the display panel 100. For example, the driving circuit 450 may be located on a silicon substrate, a glass substrate, a polyimide substrate, and the like. In this case, the circuit area may be located between the data driving area DDA and the pad area PDA.

[0101] Figure 4 is an equivalent circuit diagram of a first pixel according to one or more embodiments.

[0102] Reference Figure 4 , the first pixel PX1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first pixel PX1 may be connected to a first driving voltage VSS (see Figure 3 ) and a first driving voltage line VSL to which a second driving voltage VDD corresponding to a high potential voltage is applied (see Figure 3 ) and a second driving voltage line VDL to which a third driving voltage VINT corresponding to the initialization voltage is applied (see Figure 3). That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0103] The first pixel PX1 includes a plurality of transistors T1 , T2 , T3 , T4 , T5 , and T6 , a light emitting element ED, a first capacitor C1 , and a second capacitor C2 .

[0104] The light emitting element ED emits light according to the driving current flowing through the channel of the first transistor T1. The light emission amount of the light emitting element ED may be proportional to the driving current. The light emitting element ED may be located between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element ED may be connected to the drain electrode of the fourth transistor T4, and the second electrode thereof may be connected to the first driving voltage line VSL. The first electrode of the light emitting element ED may be an anode electrode, and the second electrode of the light emitting element ED may be a cathode electrode. The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer located between the first electrode and the second electrode, but the present specification is not limited thereto. For example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode, in which case the light emitting element ED may be a micro light emitting diode.

[0105] The first transistor T1 may be a driving transistor that controls a source-drain current (hereinafter referred to as a "driving current") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0106] The second transistor T2 may be located between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Accordingly, a data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0107] The third transistor T3 may be located between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. For this reason, since the gate electrode of the first transistor T1 is connected to the drain electrode, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0108] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, the driving current of the first transistor T1 may be supplied to the light emitting element ED. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0109] The fifth transistor T5 may be located between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element ED. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0110] The sixth transistor T6 may be located between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0111] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0112] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0113] The first node N1 is a junction point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element ED.

[0114] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a P-type MOSFET, but the present specification is not limited thereto. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be P-type MOSFETs, and the remaining transistors may be N-type MOSFETs.

[0115] Although in Figure 4 FIG. 4 shows that the first pixel PX1 includes six transistors T1, T2, T3, T4, T5 and T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 4 For example, the number of transistors and the number of capacitors of the first pixel PX1 are not limited to Figure 4 The example shown in .

[0116] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 may be combined with Figure 4 The equivalent circuit diagram of the first pixel PX1 described above is substantially the same. Therefore, in this specification, descriptions of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 will be omitted.

[0117] Figure 5 is a diagram showing a layout of pixels of a display area according to one or more embodiments.

[0118] Reference Figure 5, each of the plurality of pixels PX includes a first emission area EA1 as an emission area of ​​a first pixel PX1, a second emission area EA2 as an emission area of ​​a second pixel PX2, and a third emission area EA3 as an emission area of ​​a third pixel PX3.

[0119] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape such as a rectangle, a square, or a rhombus in a plan view. For example, the first emission area EA1 may have a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2 in a plan view. In addition, each of the second emission area EA2 and the third emission area EA3 may have a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2 in a plan view.

[0120] The length of the first emission area EA1 in the first direction DR1 may be smaller than that of the second emission area EA2 and smaller than that of the third emission area EA3 in the first direction DR1. The length of the second emission area EA2 in the first direction DR1 may be substantially the same as that of the third emission area EA3 in the first direction DR1.

[0121] The length of the first emission region EA1 in the second direction DR2 may be greater than the sum of the lengths of the second emission region EA2 and the third emission region EA3 in the second direction DR2. The length of the second emission region EA2 in the second direction DR2 may be greater than the length of the third emission region EA3 in the second direction DR2.

[0122] Although in Figure 5 , each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 is shown to have a rectangular shape in a plan view, but the present specification is not limited thereto. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape, a circular shape, or an elliptical shape in addition to a quadrilateral shape in a plan view.

[0123] In each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be different.

[0124] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the first color light may be light of a blue wavelength band, the second color light may be light of a green wavelength band, and the third color light may be light of a red wavelength band. For example, the blue wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 370 nm to about 460 nm, the green wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 600 nm to about 750 nm.

[0125] exist Figure 5 , each of the plurality of unit pixels UPX includes three emission areas EA1, EA2, and EA3, but the present specification is not limited thereto. For example, each of the plurality of unit pixels UPX may include four emission areas.

[0126] In addition, the layout of the emission regions of the plurality of pixels PX is not limited to Figure 5 For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the plurality of emission regions are arranged in the first direction DR1, in which the plurality of emission regions are arranged in a diamond shape, or in which the plurality of emission regions are arranged in a stripe structure in which the plurality of emission regions are arranged in the first direction DR2. Structure (for example, RGBG matrix structure or RGBG structure, is a registered trademark of Samsung Display Co., Ltd. of South Korea), or a hexagonal structure in which a plurality of emission regions having a hexagonal shape in a plan view are arranged.

[0127] Figure 6 is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA'.

[0128] Reference Figure 6 The display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EMTL, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate.

[0129] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors TRS, a plurality of semiconductor insulating layers covering the plurality of pixel transistors TRS, and a plurality of contact terminals CTE respectively electrically connected to the plurality of pixel transistors TRS. Figure 4 Any one of the described first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5 and sixth transistor T6.

[0130] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be located below the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0131] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor TRS, a drain region DA corresponding to a drain electrode of the pixel transistor TRS, and a channel region CH between the source region SA and the drain region DA.

[0132] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor TRS may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be located on one side of the gate electrode GE, and the drain region DA may be located on the other side of the gate electrode GE.

[0133] Each of the plurality of well regions WA further includes a first low-concentration impurity region between the channel region CH and the source region SA and a second low-concentration impurity region between the channel region CH and the drain region DA. The first low-concentration impurity region may be a region having an impurity concentration lower than that of the source region SA. The second low-concentration impurity region may be a region having an impurity concentration lower than that of the drain region DA. Due to the presence of the first low-concentration impurity region and the second low-concentration impurity region, the distance between the source region SA and the drain region DA may be increased. Therefore, the length of the channel region CH of each of the pixel transistors TRS may be increased, thereby reducing or preventing the possibility of punch-through and hot carrier phenomena that may be caused by a short channel.

[0134] The first semiconductor insulating layer SINS1 may be located on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but the present specification is not limited thereto.

[0135] The second semiconductor insulating layer SINS2 may be located on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present specification is not limited thereto.

[0136] A plurality of contact terminals CTE may be located on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source area SA, and the drain area DA of each of the pixel transistors TRS through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them.

[0137] The third semiconductor insulating layer SINS3 may be located on a side surface of each of the plurality of contact terminals CTE. A top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present specification is not limited thereto.

[0138] The semiconductor substrate SSUB may be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin film transistor may be located on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0139] The light emitting element backplane EBP includes a first metal layer ML1, a second metal layer ML2, a third metal layer ML3, a fourth metal layer ML4, a fifth metal layer ML5, a sixth metal layer ML6, a seventh metal layer ML7 and an eighth metal layer ML8, reflective electrodes RL1, RL2, RL3 and RL4, a plurality of vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8, VA9 and VA10 and a step layer STPL. In addition, the light emitting element backplane EBP includes a plurality of interlayer insulating layers INS1, INS2, INS3, INS4, INS5, INS6, INS7, INS8, INS9 and INS10 located between the semiconductor backplane SBP, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8, the reflective electrodes RL1, RL2, RL3 and RL4 and the light emitting element layer EMTL.

[0140] The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing Figure 4. That is, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 and the first capacitor C1 and the second capacitor C2 is realized by the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5 and the first electrode of the light emitting element ED is also realized by the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8.

[0141] The first interlayer insulating layer INS1 may be located on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first interlayer insulating layer INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. The first metal layer ML1 may be located on the first interlayer insulating layer INS1 and may be connected to the first vias VA1.

[0142] The second interlayer insulating layer INS2 may be located on the first interlayer insulating layer INS1 and the first metal layer ML1. Each of the second via holes VA2 may penetrate the second interlayer insulating layer INS2 and may be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be located on the second interlayer insulating layer INS2 and may be connected to the second via holes VA2.

[0143] The third interlayer insulating layer INS3 may be located on the second interlayer insulating layer INS2 and the second metal layer ML2. Each of the third via holes VA3 may penetrate the third interlayer insulating layer INS3 and may be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be located on the third interlayer insulating layer INS3 and may be connected to the third via holes VA3.

[0144] The fourth interlayer insulating layer INS4 may be located on the third interlayer insulating layer INS3 and the third metal layer ML3. Each of the fourth via holes VA4 may penetrate the fourth interlayer insulating layer INS4 and may be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be located on the fourth interlayer insulating layer INS4 and may be connected to the fourth via holes VA4.

[0145] The fifth interlayer insulating layer INS5 may be located on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. Each of the fifth via holes VA5 may penetrate the fifth interlayer insulating layer INS5 and may be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be located on the fifth interlayer insulating layer INS5 and may be connected to the fifth via holes VA5.

[0146] The sixth interlayer insulating layer INS6 may be located on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may penetrate the sixth interlayer insulating layer INS6 and may be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be located on the sixth interlayer insulating layer INS6 and may be connected to the sixth vias VA6.

[0147] The seventh interlayer insulating layer INS7 may be located on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. Each of the seventh via holes VA7 may penetrate the seventh interlayer insulating layer INS7 and may be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be located on the seventh interlayer insulating layer INS7 and may be connected to the seventh via hole VA7.

[0148] The eighth interlayer insulating layer INS8 may be located on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may penetrate the eighth interlayer insulating layer INS8 and may be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be located on the eighth interlayer insulating layer INS8 and may be connected to the eighth vias VA8.

[0149] The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be formed of substantially the same material. The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy containing any one of them. The first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be made of substantially the same material. The first interlayer insulating layer INS1, the second interlayer insulating layer INS2, the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, the fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, the seventh interlayer insulating layer INS7 and the eighth interlayer insulating layer INS8 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present specification is not limited thereto.

[0150] The thickness of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be respectively greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 may be about The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be about 1000 mm. And the thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6 may be about 1000 Å.

[0151] The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, the thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be approximately The thickness of each of the seventh via hole VA7 and the eighth via hole VA8 may be about

[0152] The ninth interlayer insulating layer INS9 may be located on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present specification is not limited thereto.

[0153] Each of the ninth via holes VA9 may penetrate the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth metal layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. The thickness of the ninth via hole VA9 may be about

[0154] Each of the first reflective electrodes RL1 may be located on the ninth interlayer insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy including any one of them.

[0155] Each of the second reflective electrodes RL2 may be located on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any of them. For example, the second reflective electrode RL2 may be made of titanium nitride (TiN).

[0156] The step layer STPL may be located on the second reflective electrode RL2 overlapping the first pixel PX1. The step layer STPL may not be located in each of the second pixel PX2 and the third pixel PX3. In order to properly reflect the light of the first color emitted from the first light emitting layer of the first pixel PX1, the thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first light emitting layer to the fourth reflective electrode RL4. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) is formed as a base inorganic layer, but the present specification is not limited thereto. The thickness of the step layer STPL may be about

[0157] In the first pixel PX1, the third reflective electrode RL3 may be located on the second reflective electrode RL2 and the step layer STPL. In the second pixel PX2 and the third pixel PX3, the third reflective electrode RL3 may be located on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them.

[0158] In one or more embodiments, at least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0159] The fourth reflective electrode RL4 may be located on the third reflective electrode RL3, respectively. The fourth reflective electrode RL4 may reflect light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to appropriately reflect light. The fourth reflective electrode RL4 may be formed of aluminum (Al); a stacked structure of aluminum and titanium (Ti / Al / Ti); a stacked structure of aluminum and ITO (ITO / Al / ITO); an APC alloy which is an alloy of silver (Ag), palladium (Pd), and copper (Cu); and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the present specification is not limited thereto. Each of the fourth reflective electrodes RL4 may have a thickness of approximately Thickness.

[0160] The tenth interlayer insulating layer INS10 may be located on the ninth interlayer insulating layer INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating layer INS10 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present specification is not limited thereto.

[0161] Each of the tenth via holes VA10 may penetrate the tenth interlayer insulating layer INS10 and may be connected to the exposed fourth reflective electrode RL4. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. Due to the presence of the step layer STPL, the thickness of the tenth via hole VA10 in the first pixel PX1 may be less than the thickness of the tenth via hole VA10 in each of the second pixel PX2 and the third pixel PX3. For example, the thickness of the tenth via hole VA10 in the first pixel PX1 may be about And the thickness of the tenth via hole VA10 in each of the second pixel PX2 and the third pixel PX3 may be about

[0162] The light emitting element layer EMTL may be located on the light emitting element back plate EBP. The light emitting element layer EMTL may include light emitting elements ED each having a first electrode AND, an intermediate layer IL, and a second electrode CAT (see Figure 4 ), a pixel defining layer PDL and a plurality of trenches TRC.

[0163] The first electrode AND of each of the light emitting elements ED may be located on the tenth interlayer insulating layer INS10 and may be connected to the tenth via VA10. The first electrode AND of each of the light emitting elements ED may be connected to the drain area DA or the source area SA of the pixel transistor TRS through the tenth via VA10, the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4, the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, the eighth via VA8, and the ninth via VA9, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements ED may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. For example, the first electrode AND of each of the light emitting elements ED may be titanium nitride (TiN).

[0164] The pixel defining layer PDL may be located on a portion of the first electrode AND of each of the light emitting elements ED. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the light emitting elements ED. The pixel defining layer PDL may be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0165] The first emission area EA1 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second emission area EA2 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third emission area EA3 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0166] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be located on the edge of the first electrode AND of each of the light emitting elements ED, the second pixel defining layer PDL2 may be located on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be located on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x ) is formed of a base inorganic layer, but the present specification is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of about Thickness.

[0167] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1 , the second pixel defining layer PDL2 , and the third pixel defining layer PDL3 . The tenth interlayer insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0168] At least one trench TRC may be located between adjacent pixels PX1, PX2, and PX3. Figure 6 It is shown that two trenches TRC are located between adjacent pixels PX1 , PX2 , and PX3 , but the present specification is not limited thereto.

[0169] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0170] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 that respectively emit different lights. For example, the intermediate layer IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0171] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0172] A first charge generation layer for supplying holes to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be located between the first intermediate layer IL1 and the second intermediate layer IL2. A second charge generation layer for supplying holes to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be located between the second intermediate layer IL2 and the third intermediate layer IL3.

[0173] The first intermediate layer IL1 may be located on the first electrode AND and the pixel defining layer PDL and may be located on the bottom surface of each groove TRC. Due to the groove TRC, the first intermediate layer IL1 may be separated between adjacent pixels PX1, PX2 and PX3. The second intermediate layer IL2 may be located on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be separated between adjacent pixels PX1, PX2 and PX3. The third intermediate layer IL3 may be located on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 may be separated between adjacent pixels PX1, PX2 and PX3. That is, each of the plurality of grooves TRC may be a structure for separating the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2 and PX3.

[0174] In order to stably separate the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of grooves TRC indicates the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining layer PDL indicates the length of the pixel defining layer PDL in the third direction DR3.

[0175] In order to cut off the first, second and third intermediate layers IL1, IL2 and IL3 of the light emitting element layer EMTL between adjacent pixels PX1, PX2 and PX3, another structure may exist instead of the trench TRC. For example, instead of the trench TRC, an inversely tapered partition wall may be located on the pixel defining layer PDL.

[0176] The number of the intermediate layers IL1, IL2, and IL3 emitting different lights is not limited to Figure 6 For example, the intermediate layer IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and for supplying holes to the other intermediate layer may be located between the two intermediate layers.

[0177] in addition, Figure 6 It is shown that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all located in each of the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the present specification is not limited thereto. For example, the first intermediate layer IL1 may be located in the first emission area EA1, but not in the second emission area EA2 and the third emission area EA3. In addition, the second intermediate layer IL2 may be located in the second emission area EA2, but not in the first emission area EA1 and the third emission area EA3. In addition, the third intermediate layer IL3 may be located in the third emission area EA3, but not in the first emission area EA1 and the second emission area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0178] The second electrode CAT may be located on the third intermediate layer IL3. The second electrode CAT may be positioned on the third intermediate layer IL3 located in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or may be formed of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency may be improved in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 due to a microcavity effect.

[0179] The encapsulation layer TFE may be located on the light emitting element layer EMTL. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE3 to reduce or prevent the possibility of oxygen or moisture penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer TFE may include at least one organic layer TFE2 to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0180] The first encapsulation inorganic layer TFE1 may be located on the second electrode CAT, the encapsulation organic layer TFE2 may be located on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be located on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be composed of silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layers are formed by alternately stacking one or more inorganic layers. The encapsulation organic layer TFE2 may be a monomer. Alternatively, the encapsulation organic layer TFE2 may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or the like.

[0181] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0182] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be located on the adhesive layer ADL.

[0183] The first color filter CF1 may overlap the first emission area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of a first color (e.g., light of a blue wavelength band). The blue wavelength band may be about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of a first color among the light emitted from the first emission area EA1.

[0184] The second color filter CF2 may overlap with the second emission area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of a second color (e.g., light of a green wavelength band). The green wavelength band may be about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit light of a second color among the light emitted from the second emission area EA2.

[0185] The third color filter CF3 may overlap with the third emission area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color (e.g., light of a red wavelength band). The red wavelength band may be about 600 nm to about 750 nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0186] The plurality of lenses LNS may be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a lens for increasing the amount of light directed to the display device 10 (see Figure 1 Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0187] The filling layer FIL may be located on the plurality of lenses LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index) so that light travels in the third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0188] The cover layer CVL may be located on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it may be used as a packaging substrate. When the cover layer CVL is a polymer resin, it may be directly applied to the filling layer FIL.

[0189] The polarizing plate may be located on one surface of the cover layer CVL. The polarizing plate may be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizing plate may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter wave plate), but the present specification is not limited thereto. However, when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may be omitted.

[0190] Figure 7 is a perspective view showing a head mounted display device according to one or more embodiments. Figure 8 It is shown Figure 7 An exploded perspective view of an example of a head-mounted display device.

[0191] Reference Figure 7 and Figure 8 According to one or more embodiments, a head-mounted display device 1000 includes a first display device 10_1, a second display device 10_2, a display device accommodating portion 1100, a accommodating portion cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0192] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 6 The display devices 10 described are substantially the same, and thus repeated descriptions corresponding to the first display device 10_1 and the second display device 10_2 will be omitted.

[0193] The first optical member 1510 may be located between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be located between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0194] The middle frame 1400 may be located between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0195] The control circuit board 1600 may be located between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see Figure 3 ), and the digital video data DATA may be transmitted to the first display device 10_1 and the second display device 10_2 through the connector.

[0196] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0197] The display device housing 1100 is used to house the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 covers one opening surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 at which the user's left eye is positioned and a second eyepiece 1220 at which the user's right eye is positioned. Figure 7 and Figure 8It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately positioned, but the present specification is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0198] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0199] The headband 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively kept on the left eye and the right eye of the user. When the housing cover 1200 is implemented to be lightweight and compact, the head mounted display device 1000 can provide a user-friendly display device. Fig. 9 The eyeglass frame shown in FIG. 8 is not a headband 800 .

[0200] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0201] Fig. 9 is a perspective view showing a head mounted display device according to one or more embodiments.

[0202] Reference Fig. 9 The head mounted display device 1000_1 according to one or more embodiments may be a glasses type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head mounted display device 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0203] The display device housing portion 1200_1 may include a display device 10_3, an optical member 1060, and an optical path conversion member 1070. An image displayed on the display device 10_3 may be magnified by the optical member 1060, and an optical path may be converted by the optical path conversion member 1070 to provide the image to the right eye of the user through the right eye lens 1020. As a result, the user may view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 1020 are combined through the right eye.

[0204] Fig. 9 The display device housing 1200_1 is shown to be located at the end on the right side of the support frame 1030, but the present specification is not limited thereto. For example, the display device housing 1200_1 may be located on the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device housing 1200_1 may be located on both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 10_3 through both the left and right eyes.

[0205] Fig.10 is a cross-sectional view of a display device according to one or more embodiments, and Fig.11 yes Fig.10 A plan view of the piezoelectric element, support member and through hole of part A.

[0206] like Fig.10 As shown in , the display device 10 according to one or more embodiments may include a driving circuit 450, a heat dissipation layer 200, a display panel 100, a polarizing plate 111, a circuit board 300, and a thermal conductive layer 123 (or a thermal interface material).

[0207] for Fig.10 For a description of the driving circuit 450, the display panel 100 and the circuit board 300, refer to Figure 1 The driving circuit 450, the display panel 100 and the circuit board 300 are described in detail. On the other hand, the polarizing plate 111 may be located on the display panel 100. For the description of the polarizing plate 111, refer to the above description of Figure 6 Description of related polarizing plates.

[0208] The heat dissipation layer 200 may discharge heat generated from a heat generating element (e.g., at least one of the driving circuit 450 and the display panel 100) to the outside to dissipate the heat of the display device 10. At least a portion of the heat dissipation layer 200 may include, for example, a plastic material or a metal material. In addition, at least a portion of the heat dissipation layer 200 may include both a plastic material and a metal material.

[0209] The heat dissipation layer 200 may include a lower plate 251, a middle plate 252, an upper plate 253, a first side plate 261, a second side plate 262, a third side plate 263, a support 280, a first chamber 211, a second chamber 212, and a piezoelectric element 600. Here, the above-mentioned chambers 211 and 212 or the spaces of the chambers 211 and 212 may be defined by the lower plate 251, the middle plate 252, the upper plate 253, the first side plate 261, the second side plate 262, and the third side plate 263.

[0210] The lower plate 251 , the middle plate 252 , the upper plate 253 , the first side plate 261 , the second side plate 262 , the third side plate 263 , and the support 280 may be integrally formed.

[0211] The lower plate 251 may be located on the driving circuit 450. For example, the lower plate 251 may be located on the driving circuit 450 in the third direction DR3 to overlap with the driving circuit 450. The lower plate 251 may have a rectangular shape extending in the second direction DR2. The lower plate 251 may have at least one through hole 291 penetrating in a direction perpendicular to the extending direction of the lower plate 251 (for example, the third direction DR3). The lower plate 251 may contact the circuit board 300.

[0212] The middle plate 252 may be located on the lower plate 251. For example, the middle plate 252 may be located on the lower plate 251 in the third direction DR3 to overlap with the lower plate 251. In this case, the middle plate 252 may be located between the lower plate 251 and the upper plate 253. The middle plate 252 may overlap with the lower plate 251 and the upper plate 253. The middle plate 252 may have a rectangular shape extending in the second direction DR2. The middle plate 252 may have at least one through hole 292 penetrating in a direction perpendicular to the extending direction of the middle plate 252 (e.g., the third direction DR3).

[0213] The upper plate 253 may be located on the middle plate 252. For example, the upper plate 253 may be located on the middle plate 252 in the third direction DR3 to overlap the middle plate 252. The upper plate 253 may have a rectangular shape extending in the second direction DR2. The upper plate 253 may contact the heat conductive layer 123.

[0214] The first side plate 261 may be located at one edge of the lower plate 251. The first side plate 261 may have a rectangular shape extending in the third direction DR3 from one edge of the lower plate 251. For example, the first side plate 261 may be located between one edge of the lower plate 251 and one edge of the middle plate 252. The first side plate 261 may be connected to one edge of the lower plate 251 and one edge of the middle plate 252.

[0215] The second side plate 262 may be located at the other edge of the lower plate 251. The second side plate 262 may have a rectangular shape extending from the other edge of the lower plate 251 in the third direction DR3. For example, the second side plate 262 may be located between the other edge of the lower plate 251 and the other edge of the middle plate 252. The second side plate 262 may be connected to the other edge of the lower plate 251 and the other edge of the middle plate 252. The second side plate 262 may face the above-mentioned first side plate 261, or may be opposite to the above-mentioned first side plate 261.

[0216] The third side plate 263 may be located at one edge of the middle plate 252. The third side plate 263 may have a rectangular shape extending in the third direction DR3 from one edge of the middle plate 252. For example, the third side plate 263 may be located between one edge of the middle plate 252 and one edge of the upper plate 253. The third side plate 263 may be connected to one edge of the middle plate 252 and one edge of the upper plate 253.

[0217] The heat dissipation layer 200 may have an opening 299 between the other edge of the middle plate 252 and the other edge of the upper plate 253. In other words, the opening 299 may be located between the other edge of the middle plate 252 and the other edge of the upper plate 253. The opening 299 may face the third side plate 263 or may be opposite to the third side plate 263.

[0218] The first chamber 211 may be located between the above-mentioned lower plate 251 and the middle plate 252. For example, the first chamber 211 may be a region surrounded and defined in a rectangular shape by the lower plate 251, the middle plate 252, the first side plate 261, and the second side plate 262. In addition, the first chamber 211 may be a structure including all of the above-mentioned lower plate 251, the middle plate 252, the first side plate 261, and the second side plate 262 and the space surrounded by them.

[0219] The second chamber 212 may be located between the above-mentioned middle plate 252 and the upper plate 253. For example, the second chamber 212 may be a region surrounded and defined in a U-shape by the middle plate 252, the upper plate 253, and the third side plate 263. In addition, the second chamber 212 may be a structure including all of the above-mentioned middle plate 252, the upper plate 253, and the third side plate 263 and the space surrounded by them. The second chamber 212 may have an opening 299 on one side thereof. The second chamber 212 may have an opening 299 between the other edge of the middle plate 252 and the other edge of the upper plate 253. In other words, the opening 299 may be located between the other edge of the middle plate 252 and the other edge of the upper plate 253.

[0220] The support member 280 may be located in at least one of the chambers. For example, the support member 280 may be located in the first chamber 211 between the lower plate 251 and the middle plate 252. When the support member 280 is located in the first chamber 211, the support member 280 may extend from the bottom surface of the middle plate 252 in a direction opposite to the third direction DR3 (hereinafter referred to as the third opposite direction). The support member 280 may have a through hole 297 penetrating in a direction perpendicular to the extension direction of the support member 280 (e.g., the first direction DR1 and / or the second direction DR2).

[0221] The piezoelectric element 600 may be located in at least one of the chambers. Fig.10 As shown in , the piezoelectric element 600 may be located in the first chamber 211. The piezoelectric element 600 may be located between the support 280 and the lower plate 251 in the first chamber 211. The piezoelectric element 600 may be supported by the support 280. For example, the piezoelectric element 600 may be located on the support 280. The edge of the piezoelectric element 600 may be located on the support 280. The piezoelectric element 600 may be attached to the support 280. In one or more embodiments, the piezoelectric element 600 may be fixed to the support 280 by the support 280 and by other fixing devices connected to the support 280.

[0222] The piezoelectric element 600 may be deformed according to a voltage from the outside. For example, depending on the direction of the current flowing through the piezoelectric element 600, the piezoelectric element 600 may be deformed to protrude in the third direction DR3 or in the third opposite direction. For example, depending on the direction of the current, the piezoelectric element 600 may be deformed to form a parabolic shape protruding in the third direction DR3, or to form a parabolic shape protruding in the third opposite direction. Here, the third direction DR3 or the third opposite direction is a direction in which the above-mentioned drive circuit 450, the heat dissipation layer 200 and the display panel 100 are stacked, and the piezoelectric element 600 may be deformed in the third direction DR3 or in the third opposite direction. At least one piezoelectric element 600 may be provided in at least one of the chambers. Fig.10 An example is shown in which two piezoelectric elements 600 are located in the first chamber 211 .

[0223] like Fig.10 and Fig.11 As shown in FIG. 2 , the piezoelectric element 600 may overlap with at least one through hole 292. For example, the piezoelectric element 600 may be positioned on the support member 280 to overlap with the through hole 292 of the intermediate plate 252. Here, in a plan view, as shown in FIG. Fig.11 As shown in , the through hole 292 of the middle plate 252 may be surrounded by the support member 280 .

[0224] like Fig.11 As shown in FIG. 1 , the piezoelectric element 600 , the support member 280 , and the through hole 292 of the middle plate 252 may have a circular shape.

[0225] In one or more implementations, by way of non-limiting example, the piezoelectric element 600 may be a piezoelectric pump or a piezoelectric micropump.

[0226] like Fig.11 As shown in FIG. 2 , the through hole 297 of the support member 280 may be formed along arcs of three sectors of the support member 280 having a circular shape. Fig.11 An example is shown in which the support member 280 has three through holes 297 separated from each other. Fig.11 As shown in , each through hole 297 may have a length (eg, arc length) corresponding to a central angle (eg, approximately 120 degrees) of each sector.

[0227] The heat conductive layer 123 may be located between the heat dissipation layer 200 and the display panel 100. For example, the heat conductive layer 123 may be located between the upper plate 253 of the heat dissipation layer 200 and the bottom surface of the display panel 100. The heat conductive layer 123 may improve the thermal conductivity between the display panel 100 and the heat dissipation layer 200. In one or more embodiments, the heat conductive layer 123 may include an adhesive material, in which case the display panel 100 and the heat dissipation layer 200 may be bonded to each other through the heat conductive layer 123.

[0228] Fig.12 yes Fig.10 An enlarged cross-sectional view of part A of Fig.13 Yes Fig.12 The timing diagram of AC power supplied to the piezoelectric element, and Fig.14 and Fig.15 It is used to explain Fig.12 Diagram of the operation of the piezoelectric element.

[0229] like Fig.12 As shown in , the piezoelectric element 600 may include a first conductive layer 601 , a second conductive layer 602 , and a piezoelectric layer 666 .

[0230] The first conductive layer 601 may be located on the support member 280. The first conductive layer 601 may be a conductive layer for applying a first voltage to the piezoelectric layer 666.

[0231] The second conductive layer 602 may be located on the first conductive layer 601. The second conductive layer 602 may be a conductive layer for applying a second voltage to the piezoelectric layer 666.

[0232] The first conductive layer 601 and the second conductive layer 602 may be applied with voltages of opposite polarities from the AC voltage source 33. For example, Fig.13As shown in FIG. 1 , the first voltage applied to the first conductive layer 601 may be an AC voltage having positive and negative polarities alternately over time. On the other hand, the second voltage applied to the second conductive layer 602 may be an AC voltage having a polarity opposite to that of the first voltage at the same timing. For example, the second voltage may be Fig.13 The first voltage is an AC voltage with a phase inversion of 180 degrees.

[0233] The piezoelectric layer 666 may be located between the first conductive layer 601 and the second conductive layer 602 .

[0234] like Fig.14 As shown in , when a first voltage of positive polarity (+) is applied to the first conductive layer 601 and a second voltage of negative polarity (-) is applied to the second conductive layer 602, a first current flowing in a third opposite direction may be generated in the piezoelectric layer 666. As a result, as Fig.14 As shown in , the piezoelectric element 600 may be deformed by the first current to have a parabolic shape that is convex in the third direction DR3.

[0235] On the other hand, Fig.15 As shown in FIG. 6 , when a first voltage of negative polarity (-) is applied to the first conductive layer 601 and a second voltage of positive polarity (+) is applied to the second conductive layer 602, a second current flowing in the third direction DR3 may be generated in the piezoelectric layer 666. As a result, as shown in FIG. Fig.15 As shown in , the piezoelectric element 600 may be deformed by the second current to have a parabolic shape that is convex in a third opposite direction.

[0236] Fig.16 and Fig.17 Is used to describe Fig.10 A diagram showing the operation of the device.

[0237] First, if Fig.16 As shown in , when the piezoelectric element 600 is deformed to have a parabolic shape that is convex in the third direction DR3, the pressure of the first chamber 211 becomes lower than the pressure outside the heat dissipation layer 200, so that the air outside the heat dissipation layer 200 can be sucked into the first chamber 211 through the through hole 291 of the lower plate 251. As a result, the pressure of the first chamber 211 can increase and can become higher than the pressure of the second chamber 212. Accordingly, the air of the first chamber 211 can be introduced into the second chamber 212 through the through hole 292 of the middle plate 252. As a result, the pressure of the second chamber 212 can increase and can become higher than the pressure outside the heat dissipation layer 200. Accordingly, the air introduced into the second chamber 212 can be discharged to the outside through the opening 299. For example, the external air introduced into the heat dissipation layer 200 can be discharged along the through hole 291 of the lower plate 251. Fig.16The direction indicated by the arrow shown in the figure sequentially passes through the through hole 291 of the lower plate 251, the first chamber 211, the through hole 292 of the middle plate 252, the second chamber 212 and the opening 299 to be discharged to the outside of the heat dissipation layer 200. In other words, the air outside the heat dissipation layer 200 can be introduced into the heat dissipation layer 200 through the through hole 291 of the lower plate 251, and then discharged to the outside through the opening 299 of the heat dissipation layer 200. Accordingly, the hot air in the first chamber 211 and the second chamber 212 can be discharged to the outside. Therefore, the heat of the driving circuit 450 and the display panel 100 can be easily released to the outside, so that the heat can be effectively dissipated from the display device 10.

[0238] On the other hand, Fig.17 As shown in , when the piezoelectric element 600 is deformed to have a parabolic shape that is convex in the third reverse direction, the pressure of the second chamber 212 becomes lower than the pressure outside the heat dissipation layer 200, so that the air outside the heat dissipation layer 200 can be introduced into the second chamber 212 through the opening 299. As a result, the pressure of the second chamber 212 can increase and can become higher than the pressure of the first chamber 211. Accordingly, the air of the second chamber 212 can be introduced into the first chamber 211 through the through hole 292 of the middle plate 252. As a result, the pressure of the first chamber 211 can increase and can become higher than the pressure outside the heat dissipation layer 200. Accordingly, the air sucked into the first chamber 211 can be discharged to the outside of the heat dissipation layer 200 through the through hole 291 of the lower plate 251. For example, the external air introduced into the heat dissipation layer 200 can be discharged along the through hole 291 of the lower plate 251. Fig.17 The direction indicated by the arrow shown in the figure sequentially passes through the opening 299 of the upper plate 253, the second chamber 212, the through hole 292 of the middle plate 252, the first chamber 211, and the through hole 291 of the first chamber 211 to be discharged to the outside of the heat dissipation layer 200. In other words, the air outside the heat dissipation layer 200 can be sucked into the heat dissipation layer 200 through the opening 299, and then can be discharged to the outside through the through hole 291 of the lower plate 251. Accordingly, the hot air in the first chamber 211 and the second chamber 212 can be discharged to the outside. Therefore, the heat of the driving circuit 450 and the display panel 100 can be easily released to the outside, so that the heat dissipation of the display device 10 can be effectively performed.

[0239] In one or more embodiments, Fig.16 and Fig.17 As shown in FIG. 5 , as the piezoelectric element 600 is deformed alternately in the third direction DR3 and the third opposite direction, air circulation occurs more actively in the heat dissipation layer 200 , so that heat dissipation of the display device 10 can be performed more effectively.

[0240] In one or more embodiments, the frequency of the piezoelectric element 600 (eg, the deformation period of the piezoelectric element 600 in the third direction DR3 and the third opposite direction) may be adjusted by adjusting the frequency of the AC voltage applied to the piezoelectric element 600 .

[0241] According to the display device 10 of one or more embodiments, since heat dissipation is performed by the piezoelectric element 600 of the heat dissipation layer 200, components of the heat dissipation layer 200 can be simplified and the size of the heat dissipation layer 200 can be reduced. As a result, the size of the display device 10 can also be reduced.

[0242] In addition, according to the display device 10 of one or more embodiments, since heat dissipation is performed by the piezoelectric element 600 , noise during heat dissipation of the display device 10 may be reduced.

[0243] Fig.18 is a cross-sectional view of a display device according to one or more embodiments.

[0244] Fig.18 The display device 10 shown in FIG. Fig.10 The display device 10 of FIG. 1 is different in that it further includes a metal layer 750. The following description will mainly focus on this difference.

[0245] like Fig.18 As shown in FIG. 1 , the display device 10 according to one or more embodiments may further include a metal layer 750 between the heat dissipation layer 200 and the thermal conductive layer 123 . For example, the metal layer 750 may be located between the upper plate 253 of the heat dissipation layer 200 and the thermal conductive layer 123 .

[0246] For example, the metal layer 750 may allow the heat of the display panel 100 to be better transferred to the heat dissipation layer 200 .

[0247] In one or more embodiments, a vapor cavity may be used instead of the metal layer 750. In other words, the vapor cavity may be located between the upper plate 253 of the heat dissipation layer 200 and the heat conductive layer 123 instead of the metal layer 750.

[0248] Fig.19 is a cross-sectional view of a display device according to one or more embodiments.

[0249] Fig.19 The display device 10 shown in FIG. Fig.10 The display device 10 of FIG. 1 is different in the structure of the heat dissipation layer 200. The following description will mainly focus on this difference.

[0250] like Fig.19 As shown in FIG. 2 , the heat dissipation layer 200 may have a first opening 299 - 1 and a second opening 299 - 2 .

[0251] The heat dissipation layer 200 (or the first chamber 211) may have a first opening 299-1 between one edge of the lower plate 251 and one edge of the middle plate 252. In other words, the first opening 299-1 may be located between one edge of the lower plate 251 and one edge of the middle plate 252.

[0252] The heat dissipation layer 200 (or the second chamber 212) may have a second opening 299-2 between the other edge of the middle plate 252 and the other edge of the upper plate 253. In other words, the second opening 299-2 may be located between the other edge of the middle plate 252 and the other edge of the upper plate 253. Here, the second opening 299-2 is located between the other edge of the middle plate 252 and the other edge of the upper plate 253. Fig.10 The same as the above-mentioned opening 299.

[0253] Fig. 20 is a cross-sectional view of a display device according to one or more embodiments.

[0254] Fig. 20 The display device 10 shown in FIG. Fig.10 The display device 10 of FIG. 1 is different in the structure of the heat dissipation layer 200. The following description will mainly focus on this difference.

[0255] like Fig. 20 As shown in , the second side plate 262 of the heat dissipation layer 200 may have a through hole 293 penetrating the second side plate 262 in a direction (eg, second direction DR2 ) perpendicular to its extending direction (eg, third direction DR3 ).

[0256] In addition, if Fig. 20 As shown in , the heat dissipation layer 200 may further include a fourth side plate 264 .

[0257] The fourth side plate 264 may be located at the other edge of the middle plate 252. The fourth side plate 264 may have a rectangular shape extending from the other side edge of the middle plate 252 in the third direction DR3. For example, the fourth side plate 264 may be located between the other edge of the middle plate 252 and the other edge of the upper plate 253. The fourth side plate 264 may be connected to the other edge of the middle plate 252 and the other edge of the upper plate 253. The fourth side plate 264 may have a through hole 294 penetrating the fourth side plate 264 in a direction perpendicular to its extending direction (e.g., the second direction DR2). The fourth side plate 264 may face the third side plate 263, or may be opposite to the third side plate 263.

[0258] At the same time, Fig. 20 In the display device 10 , the lower plate 251 may not have a through hole.

[0259] Fig.21 is a cross-sectional view of a display device according to one or more embodiments.

[0260] Fig.21 The display device 10 shown in FIG. Fig.10 The display device 10 of FIG. 1 is different in the structure of the heat dissipation layer 200. The following description will mainly focus on this difference.

[0261] Reference Fig.21 , the heat dissipation layer 200 may include a lower plate 251, a plurality of middle plates (e.g., a first middle plate 252-1 and a second middle plate 252-2), an upper plate 253, a first side plate 261, a second side plate 262, a third side plate 263, a plurality of chambers (e.g., a first chamber 211, a second chamber 212, and a third chamber 213), a support member 280, and a piezoelectric element 600. Here, the above-mentioned chambers 211, 212, and 213 or the spaces of these chambers 211, 212, and 213 may be defined by the lower plate 251, the plurality of middle plates 252-1 and 252-2, the upper plate 253, the first side plate 261, the second side plate 262, and the third side plate 263.

[0262] The lower plate 251 , the first middle plate 252 - 1 , the second middle plate 252 - 2 , the upper plate 253 , the first side plate 261 , the second side plate 262 , the third side plate 263 , and the support 280 may be integrally formed.

[0263] The lower plate 251 may be located on the driving circuit 450. For example, the lower plate 251 may be located on the driving circuit 450 in the third direction DR3 to overlap the driving circuit 450. The lower plate 251 may have a rectangular shape extending in the second direction DR2. The lower plate 251 may contact the circuit board 300.

[0264] The first intermediate plate 252-1 may be located on the lower plate 251. For example, the first intermediate plate 252-1 may be located on the lower plate 251 in the third direction DR3 to overlap with the lower plate 251. In this case, the first intermediate plate 252-1 may be located between the lower plate 251 and the second intermediate plate 252-2. The first intermediate plate 252-1 may overlap with the lower plate 251 and the second intermediate plate 252-2. The first intermediate plate 252-1 may have a rectangular shape extending in the second direction DR2. The first intermediate plate 252-1 may have at least one through hole 291 penetrating the first intermediate plate 252-1 in a direction perpendicular to its extending direction (e.g., the third direction DR3).

[0265] The second middle plate 252-2 may be located on the first middle plate 252-1. For example, the second middle plate 252-2 may be located on the first middle plate 252-1 in the third direction DR3 to overlap with the first middle plate 252-1. In this case, the second middle plate 252-2 may be located between the first middle plate 252-1 and the upper plate 253. The second middle plate 252-2 may overlap with the first middle plate 252-1 and the upper plate 253. The second middle plate 252-2 may have a rectangular shape extending in the second direction DR2. The second middle plate 252-2 may have at least one through hole 292 penetrating in a direction perpendicular to the extending direction of the second middle plate 252-2 (e.g., the third direction DR3).

[0266] The upper plate 253 may be located on the second middle plate 252-2. For example, the upper plate 253 may be located on the second middle plate 252-2 in the third direction DR3 to overlap the second middle plate 252-2. The upper plate 253 may have a rectangular shape extending in the second direction DR2. The upper plate 253 may contact the heat conductive layer 123.

[0267] The first side plate 261 may be located at one edge of the lower plate 251. The first side plate 261 may have a rectangular shape extending from one edge of the lower plate 251 in the third direction DR3. The first side plate 261 may be located between one edge of the lower plate 251 and one edge of the first middle plate 252-1. The first side plate 261 may be connected to one edge of the lower plate 251 and one edge of the first middle plate 252-1.

[0268] The second side plate 262 may be located at the other edge of the first middle plate 252-1. The second side plate 262 may have a rectangular shape extending from the other edge of the first middle plate 252-1 in the third direction DR3. For example, the second side plate 262 may be located between the other edge of the first middle plate 252-1 and the other edge of the second middle plate 252-2. The second side plate 262 may be connected to the other edge of the first middle plate 252-1 and the other edge of the second middle plate 252-2.

[0269] The third side plate 263 may be located at one edge of the second middle plate 252-2. The third side plate 263 may have a rectangular shape extending from one edge of the second middle plate 252-2 in the third direction DR3. For example, the third side plate 263 may be located between one edge of the second middle plate 252-2 and one edge of the upper plate 253. The third side plate 263 may be connected to one edge of the second middle plate 252-2 and one edge of the upper plate 253.

[0270] The heat dissipation layer 200 may have a first opening 299-1 between the other edge of the lower plate 251 and the other edge of the first intermediate plate 252-1. In other words, the first opening 299-1 may be located between the other edge of the lower plate 251 and the other edge of the first intermediate plate 252-1. The first opening 299-1 may face the first side plate 261 or may be opposite to the first side plate 261.

[0271] The heat dissipation layer 200 may have a second opening 299-2 between one edge of the first middle plate 252-1 and one edge of the second middle plate 252-2. In other words, the second opening 299-2 may be located between one edge of the first middle plate 252-1 and one edge of the second middle plate 252-2. The second opening 299-2 may face the second side plate 262 described above, or may be opposite to the second side plate 262 described above.

[0272] The heat dissipation layer 200 may have a third opening 299-3 between the other edge of the second middle plate 252-2 and the other edge of the upper plate 253. In other words, the third opening 299-3 may be located between the other edge of the second middle plate 252-2 and the other edge of the upper plate 253. The third opening 299-3 may face the third side plate 263 or may be opposite to the third side plate 263.

[0273] The first chamber 211 may be located between the lower plate 251 and the first middle plate 252-1 described above. For example, the first chamber 211 may be a region surrounded by the lower plate 251, the first middle plate 252-1, and the first side plate 261 to define a (lateral) U-shape. In addition, the first chamber 211 may be a structure including the lower plate 251, the first middle plate 252-1, the first side plate 261, and all the structures in the space surrounded by them.

[0274] The second chamber 212 may be located between the first middle plate 252-1 and the second middle plate 252-2 described above. For example, the second chamber 212 may be a region surrounded by the first middle plate 252-1, the second middle plate 252-2, and the second side plate 262 to define a (lateral) U-shape. In addition, the second chamber 212 may be all structures including the first middle plate 252-1, the second middle plate 252-2, the second side plate 262, and the space surrounded by them.

[0275] The third chamber 213 may be located between the second middle plate 252-2 and the upper plate 253 described above. For example, the third chamber 213 may be a region defined in a (lateral) U-shape surrounded by the second middle plate 252-2, the upper plate 253, and the third side plate 263. In addition, the third chamber 213 may be all structures including the second middle plate 252-2, the upper plate 253, the third side plate 263, and the space surrounded by them.

[0276] The support member 280 may be located in at least one chamber. For example, the support member 280 may be located in the second chamber 212 between the first intermediate plate 252-1 and the second intermediate plate 252-2. When the support member 280 is located in the second chamber 212, the support member 280 may extend from the bottom surface of the second intermediate plate 252-2 in a third opposite direction. The support member 280 may have a through hole 297 that penetrates in a direction perpendicular to the extension direction of the support member 280 (e.g., the first direction DR1 and / or the second direction DR2).

[0277] Fig. 22 is a cross-sectional view of a display device according to one or more embodiments.

[0278] Fig. 22 The display device 10 shown in FIG. Fig.10 The display device 10 of FIG. 1 is different in that it further includes at least one protrusion. The following description will mainly focus on this difference.

[0279] Reference Fig. 22 , the heat dissipation layer 200 may include at least one protrusion.

[0280] The protrusion may be located in at least one chamber. Fig. 22 In the example shown in FIG. 2 , the protrusions may include one or more first protrusions 441 and one or more second protrusions 442. The first protrusions 441 may be located in the first chamber 211, and the second protrusions 442 may be located in the second chamber 212.

[0281] The first protrusion 441 may be located on the top surface of the lower plate 251. The first protrusion 441 may have a rectangular rod shape protruding from the top surface of the lower plate 251 in the third direction DR3. For example, the first protrusion 441 may have a rectangular rod shape (or a rectangular column shape) extending in the first direction DR1. When the first protrusion 441 is provided in plurality, the plurality of first protrusions 441 may be spaced apart from each other in the second direction DR2. The distance between the first protrusions 441 may be constant or different.

[0282] The second protrusion 442 may be located on the bottom surface of the upper plate 253. The second protrusion 442 may have a rectangular rod shape protruding from the bottom surface of the upper plate 253 in the third opposite direction. For example, the second protrusion 442 may have a rectangular rod shape (or a rectangular column shape) extending in the first direction DR1. When the second protrusion 442 is provided in plurality, the plurality of second protrusions 442 may be spaced apart from each other in the second direction DR2. The distance between the second protrusions 442 may be constant or different.

[0283] The plurality of first protrusions 441 and the plurality of second protrusions 442 may correspond to each other. For example, the number of the first protrusions 441 may be the same as the number of the second protrusions 442. In this case, the first protrusions 441 may face the second protrusions 442, respectively, or may be opposite to the second protrusions 442, respectively.

[0284] In one or more embodiments, at least one of the first protrusion 441 and the second protrusion 442 may include copper fibers.

[0285] The first protrusions 441 and the second protrusions 442 may increase the surface areas of the first chambers 211 and the second chambers 212 of the heat dissipation layer 200. Accordingly, the heat dissipation effect of the heat dissipation layer 200 may be improved.

[0286] Fig.23 is a cross-sectional view of a display device according to one or more embodiments. Fig.24 yes Fig.23 An exploded plan view of the first valve.

[0287] Fig.23 The display device 10 shown in FIG. Fig.10 The display device 10 of FIG. 1 is different in that it also includes at least one valve. The following description will mainly focus on this difference.

[0288] The valves may include at least one first valve VL1 and at least one second valve VL2 .

[0289] The first valve VL1 may be located in the first chamber 211. For example, the first valve VL1 may be located on the top surface of the lower plate 251 in the first chamber 211. In this case, the first valve VL1 may be located on the top surface of the lower plate 251 to overlap the through hole 291 of the lower plate 251.

[0290] Reference Fig.24 , the first valve VL1 may include a first layer LL1 and a second layer LL2.

[0291] The first layer LL1 of the first valve VL1 may be located on the top surface of the lower plate 251. The first layer LL1 has a through hole 296 penetrating the first layer LL1 in the third direction DR3 such that the through hole 296 of the first layer LL1 may overlap with the through hole 291 of the lower plate 251.

[0292] The second layer LL2 of the first valve VL1 may be located on the first layer LL1 . The second layer LL2 may include a body portion 488 , a cover portion 388 , and a connection portion 288 .

[0293] The body portion 488 of the second layer LL2 may have a through hole 289 penetrating the body portion 488. The through hole 289 may have a circular shape.

[0294] The cover portion 388 of the second layer LL2 may be located in the through hole 289 of the body portion 488. The cover portion 388 may have a circular shape. The cover portion 388 may overlap the through hole 289 of the body portion 488. The cover portion 388 may have a diameter larger than the diameter of the through hole 289 of the body portion 488. For example, the cover portion 388 may have a size sufficient to completely cover the through hole 289 of the body portion 488.

[0295] The connection portion 288 of the second layer LL2 may connect the cover portion 388 to the body portion 488. The connection portion 288 may have a variable length.

[0296] The second valve VL2 may be located in the second chamber 212. For example, the second valve VL2 may be located on the top surface of the middle plate 252 in the second chamber 212. In this case, the second valve VL2 may be located on the top surface of the middle plate 252 to overlap with the through hole 292 of the middle plate 252. In addition, the second valve VL2 may also overlap with the piezoelectric element 600.

[0297] like Fig.23 As shown in , the second valve VL2 may include a first layer LL1 and a second layer LL2.

[0298] The first layer LL1 of the second valve VL2 may be located on the top surface of the middle plate 252. The first layer LL1 of the second valve VL2 has a through hole penetrating the first layer LL1 of the second valve VL2 in the third direction DR3 so that the through hole of the first layer LL1 of the second valve VL2 may overlap with the through hole 292 of the middle plate 252.

[0299] The first layer LL1 and the second layer LL2 of the second valve VL2 can be connected with Fig.24 The first layer LL1 and the second layer LL2 of the first valve VL1 are respectively identical.

[0300] Fig.25 and Fig.26 It is used to explain Fig.23 A diagram showing the operation of the device.

[0301] First, if Fig.25As shown in , when the piezoelectric element 600 is deformed to have a parabolic shape convex in the third direction DR3, the pressure of the first chamber 211 becomes lower than the pressure outside the heat dissipation layer 200, so that the first valve VL1 can be opened. For example, as the pressure of the first chamber 211 becomes lower than the pressure outside the heat dissipation layer 200, the cover portion of the first valve VL1 moves upward in the third direction DR3, so that the first valve VL1 can be opened. As the first valve VL1 is opened, air outside the heat dissipation layer 200 can be introduced into the first chamber 211 through the through hole 291 of the lower plate 251. Then, the pressure of the first chamber 211 increases, and thus the pressure of the first chamber 211 can become higher than the pressure of the second chamber 212. Accordingly, the second valve VL2 can be opened. For example, as the pressure of the first chamber 211 becomes higher than the pressure of the second chamber 212, the cover portion of the second valve VL2 moves upward in the third direction DR3, so that the second valve VL2 can be opened. As the second valve VL2 is opened, the air in the first chamber 211 may be introduced into the second chamber 212 through the through hole 292 of the middle plate 252. Then, the pressure of the second chamber 212 increases, and thus the pressure of the second chamber 212 may become higher than the pressure outside the heat dissipation layer 200. Accordingly, the air introduced into the second chamber 212 may be discharged to the outside of the heat dissipation layer 200 through the opening 299. For example, along the Fig.25 In the direction indicated by the arrow shown in , the external air introduced into the heat dissipation layer 200 can pass through the through hole 291 of the lower plate 251, the first chamber 211, the through hole 292 of the middle plate 252, the second chamber 212 and the opening 299 to be discharged to the outside of the heat dissipation layer 200. In other words, the air outside the heat dissipation layer 200 can be introduced into the heat dissipation layer 200 through the through hole 291 of the lower plate 251, and then can be discharged to the outside through the opening 299 of the heat dissipation layer 200. Accordingly, the hot air in the first chamber 211 and the second chamber 212 can be discharged to the outside. Therefore, the heat of the driving circuit 450 and the display panel 100 is easily released to the outside, so that the heat can be effectively dissipated from the display device 10.

[0302] On the other hand, Fig.26 As shown in , when the piezoelectric element 600 is deformed to have a parabolic shape convex in the third opposite direction, the pressure of the second chamber 212 becomes higher than the pressure of the first chamber 211, so that the second valve VL2 can be closed. Moreover, in this case, the pressure of the first chamber 211 becomes higher than the pressure outside the heat dissipation layer 200, so that the first valve VL1 can also be closed.

[0303] like Fig.25 and Fig.26 As shown in FIG. 1 , as the piezoelectric element 600 is deformed alternately in the third direction DR3 and the third opposite direction, air circulation occurs more actively in the heat dissipation layer 200. Accordingly, heat dissipation of the display device 10 can be performed more effectively.

[0304] Fig. 27 is a cross-sectional view of a display device according to one or more embodiments.

[0305] Fig. 27 The display device 10 shown in FIG. Fig.23 The display device 10 of FIG. 1 is different in that at least two portions of the heat dissipation layer 200 are made of different materials. The following description will mainly focus on this difference.

[0306] Reference Fig. 27 , the lower plate 251 of the heat dissipation layer 200 may include sub-lower plates 251-1 and 251-2 made of different materials. For example, the lower plate 251 may include a first sub-lower plate 251-1 made of a first material and a second sub-lower plate 251-2 made of a second material. The first sub-lower plate 251-1 and the second sub-lower plate 251-2 may be arranged in the second direction DR2. The first sub-lower plate 251-1 may be connected to the second sub-lower plate 251-2. One edge of the second sub-lower plate 251-2 may be connected to the first side plate 261, and the other edge of the second sub-lower plate 251-2 may be connected to one edge of the first sub-lower plate 251-1. For example, the second sub-lower plate 251-2 made of the second material may overlap with the driving circuit 450. Here, for example, the first material may be plastic, and the second material may be metal. In one or more embodiments, the second material may be plastic or metal.

[0307] The upper plate 253 may include a first upper sub-plate 253-1 made of a first material and a second upper sub-plate 253-2 made of a second material. The first upper sub-plate 253-1 and the second upper sub-plate 253-2 may be arranged in the second direction DR2. The first upper sub-plate 253-1 may be connected to the second upper sub-plate 253-2. One edge of the second upper sub-plate 253-2 may be connected to the third side plate 263, and the other edge of the second upper sub-plate 253-2 may be connected to one edge of the first upper sub-plate 253-1. For example, the second upper sub-plate 253-2 made of the second material may overlap with the display panel 100. Here, for example, the first material may be plastic, and the second material may be metal.

[0308] Thus, when the portion of the heat dissipation layer 200 that is adjacent to and overlaps with the driving circuit 450 and the display panel 100 serving as heat-generating elements in the third direction DR3 is made of a metal material, heat from the driving circuit 450 and the display panel 100 can be more effectively transferred to the heat dissipation layer 200, and thus heat dissipation of the display device 10 can be more effectively performed.

[0309] Fig.28 is a cross-sectional view of a display device according to one or more embodiments.

[0310] Fig.28The display device 10 shown in FIG. Fig.10 The display device 10 of FIG. 1 is different in the structure of the heat dissipation layer 200. The following description will mainly focus on this difference.

[0311] The heat dissipation layer 200 may include a lower plate 251, a middle plate 252, an upper plate 253, a first side plate 261, a second side plate 262, a third side plate 263, a plurality of supports 280-1 and 280-2, a plurality of chambers 211 and 212, a piezoelectric element 600, and a plurality of valves VL1 and VL2. Here, each of the above-mentioned chambers 211 and 212 or a space of each of the chambers 211 and 212 may be defined by the lower plate 251, the middle plate 252, the upper plate 253, the first side plate 261, the second side plate 262, and the third side plate 263.

[0312] The above-mentioned lower plate 251, middle plate 252, upper plate 253, first side plate 261, second side plate 262, third side plate 263 and plurality of supports 280-1 and 280-2 may be integrally formed.

[0313] The lower plate 251 may be located above the driving circuit 450. For example, the lower plate 251 may be located above the driving circuit 450 in the third direction DR3 to overlap the driving circuit 450. The lower plate 251 may have a rectangular shape extending in the second direction DR2. The lower plate 251 may contact the circuit board 300.

[0314] The middle plate 252 may be located above the lower plate 251. For example, the middle plate 252 may be located above the lower plate 251 in the third direction DR3 to overlap the lower plate 251. In this case, the middle plate 252 may be located between the lower plate 251 and the upper plate 253. The middle plate 252 may overlap the lower plate 251 and the upper plate 253. The middle plate 252 may have a rectangular shape extending in the second direction DR2.

[0315] The upper plate 253 may be located above the middle plate 252. For example, the upper plate 253 may be located above the middle plate 252 in the third direction DR3 to overlap the middle plate 252. The upper plate 253 may have a rectangular shape extending in the second direction DR2. The upper plate 253 may contact the heat conductive layer 123.

[0316] The first side plate 261 may be located on one edge of the lower plate 251. The first side plate 261 may have a rectangular shape extending from one edge of the lower plate 251 in the third direction DR3. The first side plate 261 may be located, for example, between one edge of the lower plate 251 and one edge of the upper plate 253. The first side plate 261 may be connected to one edge of the lower plate 251 and one edge of the upper plate 253. The first side plate 261 may face the piezoelectric element 600 in the second direction DR2, or may be opposite to the piezoelectric element 600. The first side plate 261 may be spaced apart from the middle plate 252 in the second direction DR2.

[0317] The second side plate 262 may be located on the other edge of the lower plate 251. The second side plate 262 may have a rectangular shape extending from the other edge of the lower plate 251 in the third direction DR3. The second side plate 262 may be located, for example, between the other edge of the lower plate 251 and the other edge of the middle plate 252. The second side plate 262 may be connected to the other edge of the lower plate 251 and the other edge of the middle plate 252. The second side plate 262 may face the piezoelectric element 600, or may be opposite to the piezoelectric element 600. The second side plate 262 may have a through hole 293 penetrating in a direction perpendicular to its extending direction (e.g., the second direction DR2).

[0318] The third side plate 263 may be located on the other edge of the middle plate 252. The third side plate 263 may have a rectangular shape extending from the other edge of the middle plate 252 in the third direction DR3. The third side plate 263 may be located, for example, between the other edge of the middle plate 252 and the other edge of the upper plate 253. The third side plate 263 may be connected to the other edge of the middle plate 252 and the other edge of the upper plate 253. The third side plate 263 may have a through hole 294 penetrating in a direction perpendicular to its extending direction (e.g., the second direction DR2).

[0319] The first chamber 211 may be located between the above-mentioned lower plate 251 and the middle plate 252. For example, the first chamber 211 may be a region surrounded and defined by the lower plate 251, the middle plate 252, the first side plate 261, and the second side plate 262. In addition, the first chamber 211 may be a structure including the lower plate 251, the middle plate 252, the first side plate 261, the second side plate 262, and a space surrounded by them.

[0320] The second chamber 212 may be located between the above-mentioned middle plate 252 and the upper plate 253. For example, the second chamber 212 may be a region surrounded and defined by the middle plate 252, the upper plate 253, the first side plate 261, and the third side plate 263. In addition, the second chamber 212 may be all structures including the middle plate 252, the upper plate 253, the first side plate 261, the third side plate 263, and the space surrounded by them.

[0321] The first chamber 211 may communicate with the second chamber 212 through an opening 234 between the piezoelectric element 600 and one edge of the middle plate 252 .

[0322] The first support 280-1 may be located in the first chamber 211. For example, the first support 280-1 may be located around a connection portion between the lower plate 251 and the first side plate 261. The first support 280-1 may extend from one edge (eg, a lower edge) of the first side plate 261 in the second direction DR2.

[0323] The second support 280-2 may be located in the second chamber 212. For example, the second support 280-2 may be located around a connection portion between the upper plate 253 and the first side plate 261. The second support 280-2 may extend from another edge (eg, an upper edge) of the first side plate 261 in the second direction DR2.

[0324] The piezoelectric element 600 may be located on the first support 280-1 and the second support 280-2. For example, one edge of the piezoelectric element 600 may be located on the first support 280-1, and the other edge of the piezoelectric element 600 may be located on the second support 280-2. The opening 234 may be located between the piezoelectric element 600 and the intermediate plate 252. The first chamber 211 and the second chamber 212 described above may be connected to each other through the opening 234. In one or more embodiments, the piezoelectric element 600 may be fixed to the supports 280-1 and 280-2 via a fixing device connected to the supports 280-1 and 280-2.

[0325] The piezoelectric element 600 may be deformed according to a voltage from the outside. For example, the piezoelectric element 600 may be deformed to bulge in the second direction DR2 or in a direction opposite to the second direction DR2 (hereinafter referred to as the second opposite direction) depending on the direction of the current flowing through the piezoelectric element 600. For example, according to the above-mentioned current direction, the piezoelectric element 600 may be deformed to have a parabolic shape bulging in the second direction DR2 or a parabolic shape bulging in the second opposite direction.

[0326] The first valve VL1 may be located on the second side plate 262 outside the heat dissipation layer 200. For example, a first layer of the first valve VL1 may be located on an outer surface of the second side plate 262, and a second layer of the first valve VL1 may be located on the first layer of the first valve VL1. Also, the first valve VL1 may be located on an outer surface of the second side plate 262 to overlap with the through hole 293 of the second side plate 262.

[0327] The second valve VL2 may be located on the third side plate 263 in the second chamber 212. For example, a first layer of the second valve VL2 may be located on an inner surface of the third side plate 263, and a second layer of the second valve VL2 may be located on the first layer of the second valve VL2. In addition, the second valve VL2 may be located on an inner surface of the third side plate 263 to overlap with the through hole 294 of the third side plate 263.

[0328] The first valve VL1 and the second valve VL2 may operate opposite to each other. For example, when the first valve VL1 is opened, the second valve VL2 may be closed. Also, when the first valve VL1 is closed, the second valve VL2 may be opened.

[0329] Fig.29 and Fig.30 It is used to explain Fig.28A diagram showing the operation of the device.

[0330] First, if Fig.29 As shown in , when the piezoelectric element 600 is deformed to have a parabolic shape convex in the second opposite direction, the pressure of the first chamber 211 and the second chamber 212 becomes lower than the pressure outside the heat dissipation layer 200, so that the first valve VL1 can be closed and the second valve VL2 can be opened. For example, as the pressure of the first chamber 211 and the second chamber 212 becomes lower than the pressure outside the heat dissipation layer 200, the cover portion of the first valve VL1 moves downward in the second opposite direction, thereby closing the first valve VL1, and the cover portion of the second valve VL2 moves upward in the second opposite direction, thereby opening the second valve VL2. Then, the air outside the heat dissipation layer 200 is introduced into the second chamber 212 through the opened second valve VL2 and the through hole 294 of the third side plate 263.

[0331] Then, if Fig.30 As shown in , when the piezoelectric element 600 is deformed to have a parabolic shape convex in the second direction DR2, the pressure of the first chamber 211 and the second chamber 212 becomes higher than the pressure outside the heat dissipation layer 200, so that the first valve VL1 can be opened and the second valve VL2 can be closed. For example, as the pressure of the first chamber 211 and the second chamber 212 becomes higher than the pressure outside the heat dissipation layer 200, the cover portion of the first valve VL1 moves upward in the second direction DR2, thereby opening the first valve VL1, and the cover portion of the second valve VL2 moves downward in the second direction DR2, thereby closing the second valve VL2. Then, the air in the first chamber 211 and the second chamber 212 can be discharged to the outside of the heat dissipation layer 200 through the opened first valve VL1 and the through hole 293 of the second side plate 262.

[0332] For example, along Fig.29 and Fig.30 In the direction indicated by the arrow shown in , the external air introduced into the heat dissipation layer 200 can sequentially pass through the through hole 294 of the third side plate 263, the second chamber 212, the opening 234, the first chamber 211, and the through hole 293 of the second side plate 262 to be discharged to the outside of the heat dissipation layer 200. In other words, the air outside the heat dissipation layer 200 can be introduced into the heat dissipation layer 200 through the through hole 294 of the third side plate 263, and can be discharged to the outside through the through hole 293 of the second side plate 262. Accordingly, the hot air in the first chamber 211 and the second chamber 212 can be discharged to the outside. Therefore, the heat from the driving circuit 450 and the display panel 100 can be easily released to the outside, so that the heat can be effectively dissipated from the display device 10.

[0333] like Fig.29 and Fig.30As shown in FIG. 1 , as the piezoelectric element 600 is deformed alternately in the second opposite direction and the second direction DR2, air circulation occurs more actively in the heat dissipation layer 200. Accordingly, heat dissipation of the display device 10 can be performed more effectively.

[0334] Fig.31 is a cross-sectional view of a display device according to one or more embodiments.

[0335] Fig.31 The display device 10 shown in FIG. Fig.10 The display device 10 of FIG. 1 is different in that it further includes an external power supply 321. The following description will mainly focus on this difference.

[0336] Reference Fig.31 , the piezoelectric element 600 may receive an AC voltage from the external power source 321. For example, the external power source 321 may be located on a setting plate. In this case, the piezoelectric element 600 may be connected to the external power source 321 via the setting plate.

[0337] Fig.32 is a cross-sectional view of a display device according to one or more embodiments.

[0338] Fig.32 The display device 10 shown in FIG. Fig.31 The display device 10 of FIG. 1 is different in that power is supplied to the piezoelectric element 600. The following description will mainly focus on this difference.

[0339] Reference Fig.32 , the piezoelectric element 600 may receive an AC voltage from, for example, the driving circuit 450 instead of the external power source 321 described above. To this end, in one or more embodiments, the piezoelectric element 600 may be connected to the driving circuit 450 via the circuit board 300. For example, the piezoelectric element 600 may be connected to the timing control circuit 400 or the power supply circuit 500 (see Figure 1 In this case, the timing control circuit 400 or the power supply circuit 500 may provide an AC voltage.

[0340] Those skilled in the art to which the present disclosure belongs will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the above-mentioned embodiments are illustrative rather than restrictive in all aspects. It should be understood that the scope of the present disclosure is defined by the claims rather than the above-mentioned detailed description, and all modifications and changes derived from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device, comprising: Driving circuit; A display panel, wherein the display panel is located above the driving circuit along a first direction; as well as A heat dissipation layer is located between the driving circuit and the display panel and includes a plurality of chambers and a piezoelectric element located in at least one of the plurality of chambers, the piezoelectric element being configured to deform in the first direction or in a direction opposite to the first direction.

2. The display device according to claim 1, wherein: The heat dissipation layer also includes: a lower plate, the lower plate being adjacent to the driving circuit; an upper plate, the upper plate being adjacent to the display panel; and A middle plate is located between the lower plate and the upper plate and defines a through hole.

3. The display device according to claim 2, wherein: The plurality of chambers include: a first chamber located between the lower plate and the middle plate; and A second chamber is located between the middle plate and the upper plate.

4. The display device according to claim 3, wherein: The lower plate defines a through hole extending through the lower plate, and Wherein, the heat dissipation layer further comprises: a first side panel connecting an edge of the lower panel to an edge of the middle panel; a second side panel connecting another edge of the lower panel to another edge of the middle panel; a third side panel connecting the one edge of the middle panel to one edge of the upper panel; and An opening is located between the other edge of the middle plate and the other edge of the upper plate.

5. The display device according to claim 4, wherein: The piezoelectric element overlaps the through hole of the intermediate plate.

6. The display device according to claim 1, wherein: The heat dissipation layer also includes: A support member is located in at least one of the plurality of chambers to support the piezoelectric element.

7. The display device according to claim 6, wherein: The support member defines a through hole penetrating the support member in a second direction perpendicular to the first direction.

8. The display device according to claim 1, further comprising: A heat-conducting layer is located between the display panel and the heat-dissipating layer.

9. The display device according to claim 8, further comprising: A metal layer is located between the heat conducting layer and the heat dissipating layer.

10. The display device according to claim 1, further comprising: A circuit board is located between the driving circuit and the heat dissipation layer.

11. The display device according to claim 4, wherein: The heat dissipation layer also includes: a first protrusion defined by the lower plate in the first chamber; and A second protrusion is defined by the upper plate in the second chamber.

12. The display device according to claim 4, wherein: The heat dissipation layer also includes: a first valve overlapping the through hole of the lower plate in the first chamber; and A second valve overlaps the through hole of the intermediate plate in the second chamber.

13. The display device according to claim 12, wherein: The second valve overlaps the piezoelectric element.

14. The display device according to claim 4, wherein: The lower plate includes a plurality of lower sub-plates, the plurality of lower sub-plates include different corresponding materials, and Wherein, the upper plate includes a plurality of sub-upper plates, and the plurality of sub-upper plates include different corresponding materials.

15. The display device according to claim 14, wherein: One of the plurality of sub-lower boards overlapping the driving circuit comprises a metal material, The remaining one or more sub-lower panels of the plurality of sub-lower panels comprise plastic material. wherein one of the plurality of upper sub-panels overlapping the display panel comprises a metal material, and The remaining one or more sub-upper boards among the plurality of sub-upper boards include plastic material.

16. The display device according to claim 3, wherein: The heat dissipation layer further includes a first side plate connecting the other edge of the lower plate to the other edge of the middle plate and a second side plate connecting one edge of the middle plate to one edge of the upper plate; as well as The heat dissipation layer defines a first opening between one edge of the lower plate and the one edge of the middle plate and a second opening between the other edge of the middle plate and the other edge of the upper plate.

17. The display device according to claim 3, wherein: The heat dissipation layer also includes: a first side panel connecting an edge of the lower panel to an edge of the middle panel; a second side plate connecting the other edge of the lower plate to the other edge of the middle plate and defining a through hole; a third side panel connecting the one edge of the middle panel to one edge of the upper panel; and A fourth side plate connects the other edge of the middle plate to the other edge of the upper plate and defines a through hole.

18. The display device according to claim 2, wherein: The intermediate plate comprises: a first intermediate plate located between the lower plate and the upper plate and defining a through hole; and A second middle plate is located between the first middle plate and the upper plate and defines a through hole.

19. The display device according to claim 18, wherein: The plurality of chambers include: a first chamber, the first chamber being located between the lower plate and the first intermediate plate; a second chamber located between the first intermediate plate and the second intermediate plate; and A third chamber is located between the second middle plate and the upper plate.

20. The display device according to claim 19, wherein: The heat dissipation layer also includes: a first side panel connecting an edge of the lower panel to an edge of the first middle panel; a second side panel connecting the other edge of the first middle panel to the other edge of the second middle panel; and a third side panel connecting one edge of the second middle panel to one edge of the upper panel, and Wherein, the heat dissipation layer defines: a first opening, the first opening being located between the other edge of the lower plate and the other edge of the first middle plate; a second opening located between the one edge of the first middle plate and the one edge of the second middle plate; and A third opening is located between the other edge of the second middle plate and the other edge of the upper plate.

21. The display device according to claim 1, wherein: The piezoelectric element is connected to an external power source.

22. The display device according to claim 1, wherein: The piezoelectric element is connected to the drive circuit.

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