Memory and firmware down-refreshing time test method of memory

Abstract

The invention provides a memory and a firmware downswipe time test method of the memory, and relates to the technical field of memorizers, the memory comprises a buffer used for caching to-be-tested data written by a host; the flash memory module is used for receiving to-be-tested data which are continuously written after the buffer is fully written; and the main control module is used for initializing the memory, executing initialization operation when the to-be-tested data is written into the buffer and after a preset delay time, judging whether the to-be-tested data is completely brushed to the flash memory module from the buffer or not, if not, reconfiguring the preset delay time, rewriting the to-be-tested data, and if not, rewriting the to-be-tested data into the flash memory module. And until the to-be-tested data is completely brushed into the flash memory module. According to the memory provided by the invention, the data down-refreshing time of the firmware of which the cache function is started can be tested in a manner of stepping power failure after reading and writing.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory and a method for testing the firmware refresh time of the memory. Background Art

[0002] MMC is the abbreviation of MultiMediaCard. In essence, it is a memory card specification for solid-state non-volatile storage, which defines various aspects such as the card's form, size, capacity, electrical signals, and communication protocols between hosts. eMMC is the abbreviation of "embedded multimedia controller", which refers to a package consisting of flash memory and a flash memory controller integrated on the same silicon chip. The eMMC solution contains at least three components: MMC (Multimedia Card) interface, flash memory, and flash memory controller. eMMC includes a controller and NAND (NAND memory) chips, which have unified, high-speed data interfaces, forward and backward compatibility, and high storage density. Cache is called high-speed cache memory. High-speed cache memory is a primary memory between the main memory and the CPU. It is composed of static memory chips (SRAM). It has a relatively small capacity but a much higher speed than the main memory, close to the speed of the CPU.

[0003] Many manufacturers' eMMC chips currently have the cache function enabled by default to reduce the frequency of NAND flashing and increase product life. However, there will be a SPOR (sudden power failure) test during use, which may cause data loss due to the inability to completely flash data to NAND. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a memory and a method for testing the firmware refresh time of the memory, so as to solve the problem in the prior art that during the use of the eMMC chip, there will be a SPOR (sudden power failure) test, which is prone to data loss due to the inability to completely refresh the data to the NAND.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a memory, comprising: a buffer, for caching the data to be tested written by the host; a flash memory module, for receiving the data to be tested that continues to be written after the buffer is full; and a main control module, for initializing the memory, and when the data to be tested is written to the buffer and after a preset delay time, performing an initialization operation to determine whether the data to be tested is completely flushed from the buffer to the flash memory module, if not, reconfiguring the preset delay time, and rewriting the data to be tested until the data to be tested is completely flushed to the flash memory module; when the main control module performs the initialization operation, the flash memory module is powered on again, and the written data flushed to the flash memory module before the last power failure is read back; when the main control module determines whether the data to be tested is completely flushed from the buffer to the flash memory module, the written data is compared with the data to be tested to see whether they are consistent, if the written data is consistent with the data to be tested, the flushing is successful; if the written data is inconsistent with the data to be tested, the flushing fails.

[0006] In one embodiment of the present invention, when the main control module determines that the data to be tested is completely flushed from the cache to the flash memory module, it reconfigures the delay preset time to be reduced in sequence, and uses the reduced delay preset time to perform the initialization operation after the data to be tested is written, and to determine whether the data to be tested is completely flushed from the cache to the flash memory module.

[0007] In one embodiment of the present invention, when the main control module is reconfigured to sequentially reduce the preset delay time, the preset delay time is sequentially reduced according to the set self-decrement value and the number of self-decrement times.

[0008] In one embodiment of the present invention, when the main control module determines that the data to be tested cannot be completely flushed from the cache to the flash memory module, as the number of self-decrement times decreases successively, it outputs the shortest delay time corresponding to the previous self-decrement times before the data to be tested cannot be completely flushed to the flash memory module for the first time.

[0009] In one embodiment of the present invention, the main control module determines that the data to be tested is not completely flushed from the cache to the flash memory module, and reconfigures the delay preset time. When the data to be tested is rewritten, the delay preset time is reconfigured to increase in sequence, and the increased delay preset time is used to perform the initialization operation after the data to be tested is written, and to determine whether the data to be tested is completely flushed from the cache to the flash memory module.

[0010] In one embodiment of the present invention, when the main control module is reconfigured to sequentially increase the delay preset time, the delay preset time is sequentially increased according to the set increment value and the number of self-increment times.

[0011] In one embodiment of the present invention, when the main control module determines that the test data is completely flushed from the buffer to the flash memory module, it outputs the shortest delay time corresponding to the first complete flush of the test data to the flash memory module as the self-increment times increase.

[0012] In one embodiment of the present invention, when the main control module initializes the memory, it sends a variety of control instructions and parameters corresponding to the control instructions to communicate with the flash memory module.

[0013] The present invention also provides a method for testing the firmware flash time of a memory, comprising the following steps: Receive the test data written by the host, and cache the test data in the buffer; receiving the data to be tested after the buffer is full, and continuing to write the data to be tested into the flash memory module; Initialize the memory through the main control module, and perform the initialization operation when the data to be tested is written into the buffer and after a preset delay time; Through the main control module, it is determined whether the data to be tested is completely flushed from the buffer to the flash memory module. If not, the preset delay time is reconfigured and the data to be tested is rewritten until the data to be tested is completely flushed to the flash memory module. When the main control module performs the initialization operation, it powers on the flash memory module again and reads back the written data that was flushed to the flash memory module before the last power failure; When the main control module determines whether the data to be tested is completely flushed from the buffer to the flash memory module, it compares whether the written data is consistent with the data to be tested. If the written data is consistent with the data to be tested, the flushing is successful; if the written data is inconsistent with the data to be tested, the flushing fails.

[0014] Beneficial effects of the present invention: The present invention proposes a memory and a method for testing the firmware refresh time of the memory. The memory and the method for testing the firmware refresh time of the memory can effectively use a step-by-step power-off method to test the data refresh time of a flash memory module with a cache enabled, thereby reducing data loss.

[0015] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the connection structure between the main control module Host and the eMMC chip of the present invention.

[0017] Figure 2 It is a schematic diagram of the structure of the memory of the present invention.

[0018] Figure 3 The present invention is a flow chart of a method for testing the firmware flash time of a memory.

[0019] Figure 4 For the present invention Figure 3 Schematic diagram of step S3 and step S4 in FIG.

[0020] Figure 5A preferred embodiment of the present invention provides Figure 3 Schematic diagram of the specific steps of step S4.

[0021] Component number description Host 10; memory 20; cache 21; flash memory module 22; main control module 23. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0023] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0025] See also Figure 1 , Figure 1The figure is a schematic diagram of the connection structure between the main control module Host and the flash memory module of the memory in one embodiment of the present invention. The flash memory module can adopt an eMMC chip. The eMMC chip has a total of 11 buses, namely CMD (command), DATA0-7, CLK and Data Strobe. Among them, CMD is 1 line, bidirectional transmission, that is, it is used for the main control module Host to send Command to eMMX and eMMC to send the corresponding Response to the main control module Host. In one clock cycle, both CMD and DATA0-7 signals can support the transmission of 1 bit, that is, SDR (Single Data Rate) mode. In addition, DATA0-7 signals also support configuration as DDR (Double Data Rate) mode, and 2 bits can be transmitted in one clock cycle. The main control module Host can dynamically adjust the frequency of the clock signal during the communication process. By adjusting the clock frequency, power saving or data flow control (avoiding Over-run (over-limit operation) or Under-run (insufficient processing power)) functions can be achieved. In some scenarios, the host module Host can also turn off the clock, such as when the eMMC is in Busy state, or when it enters Programming State after receiving data. The DATA0-7 signal is mainly used for data transmission between the host module Host and the eMMC. After the eMMC is powered on or soft reset, only DATA0 can be used for data transmission. After initialization, DATA0-3 or DATA0-7 can be configured for data transmission, that is, the data bus can be configured as 4 bits or 8 bits mode. The DataStrobe (a data transmission encoding method) clock signal is sent by the eMMC to the Host, with the same frequency as the CLK signal, and is used for synchronization of data reception at the Host end. The CLK signal is used to output the clock signal from the host end of the host module to synchronize data transmission and drive device operation. The Data Strobe signal can only be configured and enabled in HS400 (a multi-chip package memory) mode. After enabling, the stability of data transmission can be improved and the bus tuning process can be omitted.

[0026] See also Figures 1 to 5The present invention provides a memory and a method for testing the firmware refresh time of the memory, which can be applied to solid-state storage fields such as eMMC (Embedded Multi Media Card), UFS (Universal Flash Storage), and SDD (Solid State Disk). The present invention can use a step-by-step power-off method to effectively test the data refresh time of the flash memory module when the cache is turned on for the memory test, thereby reducing data loss. The following is a detailed description through specific embodiments.

[0027] See also Figure 2 The present invention provides a memory 20, comprising a buffer 21, a flash memory module 22 and a main control module 23. The buffer 21 is used to cache the test data written by the host 10. The flash memory module 22 is used to receive the test data that continues to be written after the buffer 21 is full. The main control module 23 is used to initialize the memory 20, and when the test data is written to the buffer 21 and after a preset delay time, perform an initialization operation. The main control module 23 is also used to determine whether the test data is completely flushed from the buffer 21 to the flash memory module 22. If not, reconfigure the preset delay time and rewrite the test data until the test data is completely flushed to the flash memory module 22.

[0028] In one embodiment of the present invention, the main control module 23 is the control center of the memory 20, which is responsible for controlling the writing of the test data sent by the host 10 into the flash memory module 22, and is responsible for reading the data in the flash memory module 22. Specifically, when the test data is written into the flash memory module 22, the test data will be cached in the buffer 21 first. After the test data in the buffer 21 is full, it will continue to be written into the flash memory module 22. In this process, the main control module 23 will initialize the memory 20 before writing the test data into the flash memory module 22, and then write the test data. When the test data is written, it is first written into the buffer 21. By setting a preset delay preset time, and starting from the time of writing into the buffer 21, after the preset delay preset time, the memory 20 is initialized again. Then the data in the flash memory module 22 is read by the main control module 23, and it is determined whether the test data has completed the complete flushing of the flash memory module 22 from the buffer 21. And by continuously adjusting the preset delay time, the data to be tested is rewritten so that the data to be tested can be completely flushed from the buffer 21 to the flash memory module 22 .

[0029] See also Figure 2In one embodiment of the present invention, before the test data is written into the flash memory module 22, the memory 20 needs to be initialized by the main control module 23. When the test data is written into the buffer 21, after a preset delay time, the memory 20 also needs to be initialized by the main control module 23. Specifically, when the main control module 23 initializes the memory, it sends a variety of control instructions and parameters corresponding to the control instructions to communicate with the flash memory module 22. For example, the main control module 23 will send a cmd0+0 instruction to the flash memory module 22, reset device (perform a reset action) (eMMC flash memory chip), where "cmd0" is a control instruction, and the other "0" after the "+" is a parameter corresponding to the control instruction.

[0030] When the main control module 23 performs the initialization operation, it powers on the flash memory module 22 again and reads back the written data that was flushed to the flash memory module 22 before the last power failure; when the main control module 22 determines that the data to be tested is completely flushed from the buffer 21 to the flash memory module 22, it compares whether the written data is consistent with the data to be tested. If the written data is consistent with the data to be tested, the flushing is successful; if the written data is inconsistent with the data to be tested, the flushing fails.

[0031] In one embodiment of the present invention, when the data to be tested is written into the buffer 21, the power will be automatically cut off at the time node when the preset delay time is reached according to the preset delay time. After the power is cut off, the data to be tested buffered in the buffer 21 is lost. Subsequently, the flash memory module 22 is powered on again. After the flash memory module 22 is initialized and powered on again, the written data flushed from the buffer 21 to the flash memory module 22 before the power is cut off is read back. The length of the preset delay time will affect the integrity of the data to be tested flushed into the flash memory module 22. That is to say, when the preset delay time is set to be short, the data to be tested may not be completely flushed into the flash memory module 22 when it is written into the buffer 21. Therefore, in this case, it is easy to cause the write data written into the flash memory module 22 to be inconsistent with the data to be tested. Based on this situation, the main control module 23 will further judge whether the data to be tested has been completely flushed from the buffer 21 to the flash memory module 22. That is, after power is turned on again, the written data read back from the flash memory module 22 is compared with the test data originally written into the buffer 21 for consistency. If the two are consistent, it means that the test data has completed the complete flushing from the retarder 21 to the flash memory module 22, or the flushing is successful. Otherwise, it means that the test data is incomplete when it is flushed from the retarder 21 to the flash memory module 22, or the flushing fails.

[0032] In one embodiment of the present invention, when the main control module 23 determines whether the data to be tested is completely flushed from the buffer 21 to the flash memory module 22, there are two situations in which the corresponding initially set delay preset time is greater than or less than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22. That is to say, there are two situations in which the initially set delay preset time is set. One is when the main control module 23 determines that the data to be tested cannot be completely flushed from the buffer 21 to the flash memory module 22, indicating that the delay preset time may be greater than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22. The other is when the main control module 23 determines that the data to be tested is completely flushed from the buffer 21 to the flash memory module 22, indicating that the delay preset time may also be less than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22.

[0033] When the main control module 23 determines that the data to be tested is completely flushed from the buffer 21 to the flash memory module 22, it indicates that the preset delay time set for the initial flushing is greater than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22. In other words, when the preset delay time set for the initial flushing is greater than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22, the main control module 23 will first determine that the data to be tested is completely flushed from the buffer 21 to the flash memory module 22. Specifically, when the main control module 23 determines that the data to be tested is completely flushed from the buffer 21 to the flash memory module 22, it reconfigures to reduce the preset delay time in sequence, and uses the reduced preset delay time to perform the initialization operation after the data to be tested is written, and to determine whether the data to be tested is completely flushed from the buffer 21 to the flash memory module 22.

[0034] In one embodiment of the present invention, when the flash is just started, the preset delay time may be longer than the time it takes for the data to be tested to be completely written from the buffer 21 to the flash memory module 22. After confirming that the data to be tested is completely flushed from the buffer 21 to the flash memory module 22, the main control module 23 will continue to reconfigure the preset delay time so that the preset delay time is reduced in sequence. And then re-execute the write test of the data to be tested with the preset delay time that has been reduced in sequence. The write test is specifically as follows: write the data to be tested into the buffer 21, and perform the initialization operation after the preset delay time that has been reduced in sequence. After the flash memory module 23 is powered on again, read back the written data in the flash memory module 23. And compare the written data with the data to be tested to determine again whether the data to be tested is completely flushed from the buffer 21 to the flash memory module 22.

[0035] At the beginning of the refresh, the preset delay time may be longer than the time for the test data to be completely written from the buffer 21 to the flash memory module 22, and the preset delay time needs to be further reduced according to whether the test data is completely flushed from the buffer 21 to the flash memory module 22. When the main control module 23 is reconfigured to reduce the preset delay time, the preset delay time is reduced in sequence according to the set self-decrement value and the number of self-decrement times. In this embodiment, the preset delay time can be extended from the first initial →0. You can set the decrement value. and the number of self-decrements To reduce the delay preset time, that is, to obtain the reduced delay preset time .

[0036] When using the setting self-decrement value and the number of self-decrements To reduce the delay preset time, the data to be tested will be reduced in the number of times When the test data cannot be completely flushed from the buffer 21 to the flash memory module 22, the main control module 23 determines that the test data cannot be completely flushed from the buffer 21 to the flash memory module 22, and outputs the shortest delay time corresponding to the previous self-decrement number before the test data cannot be completely flushed to the flash memory module 22 for the first time as the self-decrement number decreases successively.

[0037] In one embodiment of the present invention, the main control module 23 is based on the number of self-decrement and self-decrement value When reducing the delay preset time, assuming the number of self-decrements is When the data to be tested cannot be completely flushed to the flash memory module 22 for the first time. The delay preset time corresponding to the failure to complete the flushing for the first time The number of self-decrements before the first failure to complete the next refresh When , it corresponds to the last time that the data to be tested can be completely flushed to the flash memory module 22. Then the delay preset time of the last time that the data to be tested can be completely flushed to the flash memory module 22 can be obtained. , and use this as the shortest delay time for the data to be tested to be completely flushed from the buffer 21 to the flash memory module 22.

[0038] When the main control module 23 determines that the data to be tested is not completely flushed from the buffer 21 to the flash memory module 22, it indicates that the preset delay time set for the initial flushing is less than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22. In other words, when the preset delay time set for the initial flushing is less than the time when the data to be tested is just completely written from the buffer 21 to the flash memory module 22, the main control module 23 will first determine that the data to be tested is not completely flushed from the buffer 21 to the flash memory module 22. Specifically, the main control module 23 determines that the data to be tested is not completely flushed from the buffer 21 to the flash memory module 22, and reconfigures the preset delay time. When the data to be tested is rewritten, the preset delay time is reconfigured to increase the preset delay time in sequence, and the increased preset delay time is used to perform the initialization operation after the data to be tested is written, and to determine whether the data to be tested is completely flushed from the buffer 21 to the flash memory module 22. When the main control module 23 determines that the data to be tested is not completely flushed from the buffer 21 to the flash memory module 22, its corresponding Figure 5 In step S41 to step S47, the main control module 23 controls the specific process of sequentially increasing the delay preset time.

[0039] In one embodiment of the present invention, at the beginning of the refresh, the preset delay time may be less than the time for the data to be tested to be completely written from the buffer 21 to the flash memory module 22. After confirming that the data to be tested has not been completely refreshed from the buffer 21 to the flash memory module 22, the main control module 23 will continue to reconfigure the preset delay time so that the preset delay time increases sequentially. And then re-execute the write test of the data to be tested with the sequentially increased preset delay time. The write test is specifically as follows: write the data to be tested into the buffer 21, and after the sequentially increased preset delay time, perform the initialization operation. After the flash memory module 23 is powered on again, read back the written data in the flash memory module 23. And compare the written data with the data to be tested to determine again whether the data to be tested has been completely refreshed from the buffer 21 to the flash memory module 22.

[0040] At the beginning of the refresh, the preset delay time may be less than the time for the test data to be completely written from the buffer 21 to the flash memory module 22, and the preset delay time needs to be further increased according to whether the test data is completely flushed from the buffer 21 to the flash memory module 22. When the main control module 23 is reconfigured to increase the preset delay time, the preset delay time is increased according to the set increment value and the number of self-increment times. In this embodiment, the preset delay time can be extended from the second initial value. → The increment value can be set. And the number of increments To increase the delay preset time, that is, to get the increased delay preset time .in, Indicates that the value is greater than The extended time limit value.

[0041] When using the auto-increment value And the number of increments To increase the delay preset time, the data to be tested will be incremented by When the data to be tested can be completely flushed from the buffer 21 to the flash memory module 22, the main control module 23 determines that the data to be tested is completely flushed from the buffer 21 to the flash memory module 22, and outputs the shortest delay time corresponding to the first complete flush of the data to be tested to the flash memory module 22 as the self-increment times increase.

[0042] In one embodiment of the present invention, the main control module 23 performs the self-incrementing operation according to the number of and auto-increment value When increasing the delay preset time, assuming the number of self-increment times is When the data to be tested can be completely flushed to the flash memory module 22 for the first time. The delay preset time corresponding to the first flushing can be completed , and use this as the shortest delay time for the data to be tested to be completely flushed from the buffer 21 to the flash memory module 22.

[0043] like Figure 3 As shown, the present invention also provides a method for testing the firmware refresh time of the memory 20, comprising the following steps: Step S1 , receiving the test data written by the host 10 , and buffering the test data into the buffer 21 .

[0044] Step S2 , receiving the data to be tested after the buffer 21 is full, and continuing to write the data to be tested into the flash memory module 22 .

[0045] Step S3, initializing the memory 20 through the main control module 23, and performing the initialization operation when the data to be tested is written into the buffer 21 and after a preset delay time.

[0046] Step S4, determining through the main control module 23 whether the test data is completely flushed from the buffer 21 to the flash memory module 22, if not, reconfiguring the delay preset time and rewriting the test data until the test data is completely flushed to the flash memory module 22.

[0047] Step S1, receiving the test data written by the host 10, and buffering the test data into a buffer.

[0048] In one embodiment of the present invention, when the host 10 writes the data to be tested into the flash memory module 22, it will first be cached in the buffer 21. The data to be tested may be one or more data packets.

[0049] Step S2 , receiving the data to be tested after the buffer 21 is full, and continuing to write the data to be tested into the flash memory module 22 .

[0050] In one embodiment of the present invention, during the process of writing data into the buffer 21 , after the buffer 21 is full, the data will be further written from the buffer 21 into the flash memory module 22 .

[0051] Step S3, initializing the memory 20 through the main control module 23, and performing the initialization operation when the data to be tested is written into the buffer 21 and after a preset delay time.

[0052] In one embodiment of the present invention, when the host 10 writes the data to be tested into the flash memory module 22, it will first be cached in the buffer 21. Therefore, when the buffer 21 starts caching, after recording the preset delay time, the memory 10 is powered off and then powered on to perform initialization. While the cache in the buffer 21 is cleared, if there is data written from the buffer 21 to the flash memory module 22, the corresponding data written to the flash memory module 22 can be further read after powering on.

[0053] Step S4, determining through the main control module 23 whether the test data is completely flushed from the buffer 21 to the flash memory module 22, if not, reconfiguring the delay preset time and rewriting the test data until the test data is completely flushed to the flash memory module 22.

[0054] In one embodiment of the present invention, after the delay preset time has passed and the initialization operation has been performed, that is, after the flash memory module 22 is powered on again, whether there is complete data to be tested in the flash memory module 22 is read. If there is no complete data to be tested, it means that the flash memory module 22 has not been completely flushed through the buffer 21. In other words, the initially configured delay preset time is not enough to achieve a complete flush of the data to be tested to the flash memory module 22. Therefore, it is necessary to readjust the configuration delay preset time so that the amount of the buffer 21 flushing the flash memory module 22 increases continuously until the configured delay preset time can satisfy the complete flushing of the data to be tested to the flash memory module 22.

[0055] See also Figure 4 In a preferred embodiment, the present invention further provides a step-by-step test method for testing the cache on firmware refresh time based on the flash memory chip eMMC, such as the above step S3, which specifically includes the following steps: Steps S301-S310: the main control module Host initializes the eMMC chip; Step S311, prepare a data packet of the data to be tested, and prepare to write it into the eMMC chip; Step S312: After the Host issues a write command to write data into the eMMc chip, the power is turned off after a certain delay (execution pause).

[0056] Specifically, in steps S301 to S310: Step S301, the XU4 master controller is powered on, and the eMMc flash memory chip is powered on; Step S302, XU4 sends cmd0+0, reset device (eMMC flash memory chip); Step S303, XU4 sends cmd1+0x40FF8080; Step S304, XU4 sends cmd2+0x40FF8080 to obtain CID; Step S305, XU4 sends cmd3+RCA; Step S306, XU4 sends cmd9+RCA to obtain the CSD register; Step S307, XU4 sends cmd13+RCA, obtains the current state RCA, obtains the current state; Step S308, XU4 sends cmd7+RCA to perform the select card action; Step S309, XU4 sends cmd13+RCA to obtain the current status; Step S310, XU4 sends cmd6+arg to set the transmission timing (memory timing) and buswidth (data bus width).

[0057] In step S301 to step S310, XU4 is the control card specifically used by the Host. After the main control module and the eMMC chip are powered on, the cmd0+0 command issued by the main control module is received, and the eMMC chip performs a reset action, and the eMMC chip enters the Idle state (i.e., idle state) through cmd0+0. Then the cmd1+0x40ff8080 command issued by the main control module is received. The parameter 0x40ff8080 of the command indicates the voltage value to be used by the main control module. After receiving the command, the eMMC chip will return the response data R3 (a register). The busy bit in R3 is 0, indicating that the eMMC chip is not ready yet. The main control module will repeatedly send cmd1 and wait for the eMMC chip to return ready. After receiving the ready data of the eMMC chip, the main control module continues to issue the cmd2+0x40ff8080 command. After receiving the command, the eMMC chip will feedback the device authentication identification (Device Identification, CID). After receiving the CID, the main control module will dynamically allocate a relative device address (Relative device address, RCA) for the eMMC chip according to the CID, and transmit the allocated relative device address to the eMMC chip through the command cmd3+RCA. Specifically, after obtaining the relative device address according to the aforementioned command issued by the main control module, the Device-specific-data (CSD) of the eMMC chip is sent to the CMD bus according to the cmd9+RCA command issued by the main control module. The CSD register stores device-specific data, including information such as device working conditions. Further, according to the cmd13+RCA command issued by the main control module Host, the eMMC sends the status register to the CMD bus, and the main control module Host can determine the current state of the eMMC chip according to the status register. Since the main control module Host can connect to multiple eMMC chips at the same time, after obtaining the current state of the eMMC chip, the main control module Host can issue the cmd7+RCA command to select the eMMC chip through the current RCA. After completing the chip selection, the cmd13+RCA command is sent again, and the selected eMMC chip returns its current state. When the current state of the eMMC chip meets the requirements, the host module Host sends the cmd6+arg (arg represents the parameter) command to set the initial data transmission rate and bus width of the data transmission. This completes the initialization process of the entire eMMC chip.

[0058] Step S4 includes the following steps: Step S401, after powering on, go through S301 to S310 again, read back the just written data and compare; Step S402, determining whether the data comparison between the test data and the written data passes; Step S4021: If the data comparison is pass, it means that the device successfully refreshes the data within the delay time; Step S4022: If the data comparison fails, it means that the device has not successfully refreshed the data within the delay time.

[0059] See also Figure 5 In a preferred embodiment, when executing step S4, the following steps are performed: Step S41, XU4 initializes a series of CMD chips for the eMMC chip; Step S42, enter the cycle (cycle value starts from 0) loop, prepare the data packet of the data to be tested, and prepare to write it into the eMMC chip; Step S43: After the Host issues a write command to write data into the eMMC chip, delay Tms (ms level, T starts from 0 to power off); Step S44, after powering on, go back to S41 to read back and compare the data just written; Step S45, data comparison whether pass; Step S451: If the data comparison is pass, it means that the device successfully refreshes the data within the delay time; Step S452: If the data comparison fails, it means that the device has not successfully refreshed the data within the delay time; Step S46, record the result of S44, the T value is incremented by 1, and the cycle value is incremented by 1; Step S47, return to S42, until the cycle value increases to 1000.

[0060] In summary, the present invention provides a memory and a method for testing the firmware refresh time of the memory, which can effectively test the data refresh time of the flash memory module when the cache is turned on by using a step-by-step power-off method to reduce data loss.

[0061] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: A buffer, used for caching the data to be tested written by the host; A flash memory module, used for receiving the data to be tested which is continuously written after the buffer is full; as well as A main control module, used to initialize the memory, and when the data to be tested is written into the buffer and after a preset delay time, perform an initialization operation to determine whether the data to be tested is completely flushed from the buffer to the flash memory module, and if not, reconfigure the preset delay time and rewrite the data to be tested until the data to be tested is completely flushed to the flash memory module; When the main control module performs the initialization operation, the flash memory module is powered on again, and the written data flushed to the flash memory module before the last power failure is read back; When the main control module determines whether the data to be tested is flushed from the buffer to the flash memory module, it compares whether the written data is consistent with the data to be tested. If the written data is consistent with the data to be tested, the flushing is successful; if the written data is inconsistent with the data to be tested, the flushing fails.

2. The memory according to claim 1, characterized in that: When the main control module determines that the data to be tested is completely flushed from the buffer to the flash memory module, it reconfigures the delay preset time to be reduced in sequence, and uses the reduced delay preset time to perform the initialization operation after the data to be tested is written, and to determine whether the data to be tested is completely flushed from the buffer to the flash memory module.

3. The memory according to claim 2, characterized in that: When the main control module is reconfigured to sequentially reduce the preset delay time, the preset delay time is sequentially reduced according to the set self-decrement value and the number of self-decrement times.

4. The memory according to claim 3, characterized in that: When the main control module determines that the data to be tested cannot be completely flushed from the buffer to the flash memory module, as the self-decrement times decrease successively, it outputs the shortest delay time corresponding to the last self-decrement times before the data to be tested cannot be completely flushed to the flash memory module for the first time.

5. The memory according to claim 1, characterized in that: The main control module determines that the data to be tested is not completely flushed from the buffer to the flash memory module, and reconfigures the delay preset time. When the data to be tested is rewritten, the delay preset time is reconfigured to increase in sequence, and the increased delay preset time is used to perform the initialization operation after the data to be tested is written, and to determine whether the data to be tested is completely flushed from the buffer to the flash memory module.

6. The memory according to claim 5, characterized in that: When the main control module is reconfigured to sequentially increase the preset delay time, the preset delay time is sequentially increased according to the set increment value and the number of self-increment times.

7. The memory according to claim 6, characterized in that: When the main control module determines that the data to be tested is completely flushed from the buffer to the flash memory module, it outputs the shortest delay time corresponding to the first complete flush of the data to be tested to the flash memory module as the self-increment times increase successively.

8. The memory according to claim 1, characterized in that: When the main control module initializes the memory, it sends a variety of control instructions and parameters corresponding to the control instructions to communicate with the flash memory module.

9. A method for testing the firmware flash time of a memory, characterized in that: The steps include: Receiving the data to be tested written by the host, and buffering the data to be tested in a buffer; receiving the data to be tested after the buffer is full, and continuing to write the data to be tested into the flash memory module; Initializing the memory through the main control module, and performing an initialization operation when the data to be tested is written into the buffer and after a preset delay time; By means of the main control module, it is determined whether the data to be tested is completely flushed from the buffer to the flash memory module; if not, the preset delay time is reconfigured, and the data to be tested is rewritten until the data to be tested is completely flushed to the flash memory module; When the main control module performs the initialization operation, the flash memory module is powered on again, and the written data flushed to the flash memory module before the last power failure is read back; When the main control module determines whether the data to be tested is flushed from the buffer to the flash memory module, it compares whether the written data is consistent with the data to be tested. If the written data is consistent with the data to be tested, the flushing is successful; if the written data is inconsistent with the data to be tested, the flushing fails.

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