Wafer with zero internal cavity and preparation method thereof

Abstract

The preparation method comprises the following steps: determining wafer physical parameters according to application requirements of a target wafer, selecting an optimal seed crystal by using a fuzzy logic control system, and carrying out surface treatment; a fuzzy logic control system is adopted to adjust the crystal growth rate in a high-temperature environment to obtain single crystals; the method comprises the following steps: cutting a single crystal ingot into a wafer, carrying out primary grinding, and carrying out dynamic adjustment by adopting a chemical mechanical polishing process and a fuzzy logic control system to obtain a wafer with a smooth surface; the method comprises the following steps: introducing impurities through a doping and diffusion process, optimizing the concentration of a dopant and a diffusion temperature gradient to obtain an optimized wafer, performing pattern etching on the optimized wafer, performing annealing and heat treatment operations, and optimizing an annealing curve by using a fuzzy logic control system to obtain a wafer finished product. Therefore, the generation of cavities in the wafer is effectively controlled and reduced, the integrity of the internal structure of the wafer can be remarkably improved, and high-quality preparation of the wafer with zero cavities inside is realized.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an internal zero-void wafer and a preparation method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, the quality of wafers, as the basic material for integrated circuit manufacturing, directly affects the performance and reliability of electronic devices. High-quality wafers have broad application prospects in multiple application fields such as microelectronics, optoelectronics, power devices, and advanced packaging. For example, in cutting-edge technologies such as high-frequency communications, artificial intelligence computing, and high-performance computing, higher requirements are placed on the internal structural integrity and defect control of wafers. Therefore, the research and development of advanced process methods that can prepare internal zero-void wafers is of great significance for improving the performance of semiconductor devices and promoting technological progress in related industries.

[0003] Existing wafer preparation technology includes multiple links. In conventional processes, since the parameter control of each preparation step depends on pre-setting, it is difficult to achieve precise control of complex process conditions, which leads to internal voids and other defects in the wafer during the growth process. In addition, the existing technology lacks control over doping uniformity and stress release, further increasing the uncontrollability of the void rate inside the wafer. These shortcomings not only reduce the overall quality and consistency of the wafer, but also limit its reliability and performance in high-end applications.

[0004] Therefore, there is an urgent need for a preparation method that can optimize key process parameters through intelligent means and significantly reduce the void rate inside the wafer to meet the urgent demand of the modern semiconductor industry for high-quality wafers. Summary of the invention

[0005] The purpose of the present invention is to provide an internal zero-void wafer and a preparation method thereof to solve the above technical problems.

[0006] To achieve this object, the present invention adopts the following technical solutions: A method for preparing an internal zero-void wafer, comprising: Step S1, according to the application requirements of the target wafer, determine the corresponding wafer physical parameters, use the fuzzy logic control system to select the optimal seed crystal, and perform surface treatment on the selected optimal seed crystal; Step S2, using a fuzzy logic control system to adjust the crystal growth rate in a high temperature environment, and achieving the growth of a single crystal by rotating the seed crystal and the crucible to obtain a single crystal; Step S3, cutting the single crystal ingot into wafers and performing preliminary grinding, then using a chemical mechanical polishing process, and dynamically adjusting the pressure, speed and chemical liquid concentration of the polishing pad through a fuzzy logic control system to obtain a wafer with a smooth surface; Step S4, introducing impurities through doping and diffusion processes, using a fuzzy logic control system to optimize dopant concentration and diffusion temperature gradient, making internal doping uniform to reduce internal voids, and obtaining an optimized wafer; Step S5, after pattern etching the optimized wafer, annealing and heat treatment operations are performed, and the fuzzy logic control system is used to optimize the annealing curve. The optimization process includes the heating rate, the holding time and the cooling rate to prepare the finished wafer.

[0007] Optionally, the step S1 specifically includes: Step S11, determining key physical parameters of the wafer according to application requirements of the target wafer by analyzing performance requirements and working environment of the electronic device, wherein the key physical parameters include lattice constant, purity, doping concentration range and thermal conductivity; Step S12, using a fuzzy logic control system to input the key physical parameters, and combining the seed characteristics in the existing seed database, through fuzzy rule evaluation and weight calculation, select the optimal seed that best meets the target parameter requirements; Step S13, performing surface cleaning treatment on the optimal seed crystal, using a plasma cleaning method at a power of 400 W for 30 minutes to remove organic pollutants and particles on the surface of the seed crystal; Step S14, performing seed crystal surface finishing, treating the seed crystal surface by chemical mechanical polishing process under preset pressure and polishing liquid flow rate conditions, so that the seed crystal surface flatness reaches Ra<1 nm; Step S15, using a fuzzy logic control system to monitor and adjust the temperature, humidity and treatment time during the surface treatment process.

[0008] Optionally, the step S2 specifically includes: Step S21, setting and maintaining the temperature required for crystal growth in the high temperature growth chamber, the temperature range being controlled between 1400° C. and 1600° C.; Step S22, inputting key physical parameters and growth requirements of the wafer through a fuzzy logic control system, the growth requirements including growth rate, temperature gradient and environmental pressure, and evaluating and calculating the optimal growth conditions in real time; Step S23, starting the rotating device to rotate the seed crystal at a speed of 300 to 500 revolutions per minute, and the crucible at a speed of 100 to 200 revolutions per minute; Step S24, based on the data feedback of real-time monitoring of the rotation speed and temperature of the rotating device, the fuzzy logic control system is used to dynamically adjust the rotation speed and temperature gradient to optimize the crystal growth rate.

[0009] Optionally, after step S24, the following steps may be further performed: Step S25, during the single crystal growth process, using thermocouples and optical sensors to monitor the temperature distribution of the growth environment and the crystal surface morphology in real time, and inputting the data into the fuzzy logic control system for analysis and adjustment; Step S26, coordinating atmosphere control through a fuzzy logic control system, the atmosphere control process includes adjusting the inert gas flow and pressure; Step S27, after the single crystal growth is completed, the temperature of the growth chamber is lowered to room temperature, and a gradual cooling technique is used to reduce the stress inside the crystal and prevent the generation of thermal cracks to obtain a single crystal.

[0010] Optionally, the step S3 specifically includes: Step S31, fixing the single crystal ingot on a cutting device, using a diamond wire saw to cut the wafer, and controlling the cutting rate to 20 to 30 mm per minute; Step S32, performing preliminary grinding on the cut wafers, using a grinding wheel grinder at a speed of 500 to 700 revolutions per minute; Step S33, cleaning the wafer after preliminary grinding, using deionized water and ultrasonic cleaning technology, and the cleaning time is 10 minutes to remove the abrasive and particles remaining in the grinding process; Step S34, implement chemical mechanical polishing process to further polish the wafer surface. During the polishing process, a polishing slurry containing aluminum oxide particles is used, the polishing liquid flow rate is controlled at 100 to 150 ml / min, the polishing pressure is maintained at 5 to 10N, and the polishing disk speed is set at 50 to 100 rpm.

[0011] Optionally, after step S34, the following steps may be further performed: Step S35, dynamically adjusting the pressure, speed and chemical solution concentration of the polishing pad by a fuzzy logic control system; specifically, the fuzzy logic control system adjusts the pressure applied by the polishing pad to a range of 5 to 10 Newtons, the rotation speed of the polishing disk to a range of 50 to 100 revolutions per minute, and the concentration of aluminum oxide particles in the chemical slurry to a range of 5% to 15% according to the real-time monitored surface roughness data of the wafer; Step S36, after the chemical mechanical polishing is completed, the surface morphology is detected, the surface of the wafer is detected using an optical scanning device, and the detection data is recorded; Step S37, based on the surface morphology detection result, feedback is given to the fuzzy logic control system. If it is detected that the surface roughness does not meet the standard, the polishing parameters are adjusted and the polishing process is performed again until the wafer surface reaches the predetermined surface roughness standard.

[0012] Optionally, the step S4 specifically includes: Step S41, placing the wafer that has undergone chemical mechanical polishing in a high-temperature diffusion furnace, and introducing a dopant of a predetermined concentration by a diffusion process; Step S42, inputting key control parameters of dopant concentration, diffusion temperature gradient and diffusion time through a fuzzy logic control system, real-time monitoring and dynamic adjustment of temperature distribution and dopant concentration during the diffusion process; Step S43, during the diffusion process, temperature gradient control technology is used to make the temperature of the wafer in the diffusion furnace increase or decrease linearly in the vertical direction, and the temperature gradient range is controlled within a range of 50 to 200°C / cm.

[0013] Optionally, after step S43, the following steps are further included: Step S44, using a fuzzy logic control system to automatically adjust the heating power and cooling rate of the diffusion furnace according to the real-time feedback data of the doping concentration distribution and the temperature gradient change, so as to optimize the diffusion environment; Step S45, after the diffusion is completed, slowly cooling the wafer to room temperature, using a gradual cooling technique to reduce thermal stress and crystal defects inside the wafer; Step S46, performing doping uniformity detection on the diffused wafer, using ion detection technology to measure the doping concentration distribution, and confirming that the doping concentration is within a preset range.

[0014] Optionally, after step S5, the following steps may be further performed: Step S6, performing quality inspection on the finished wafer product, evaluating the wafer quality based on the inspection data, and feeding back to the fuzzy logic control system to adjust the logic preference of its process parameters to optimize the wafer preparation process.

[0015] The present invention further provides an internal zero-void wafer, which is prepared by the method for preparing the internal zero-void wafer as described above, and the internal zero-void wafer specifically comprises: A single crystal substrate is formed by a crystal growth process using a selected optimal seed crystal; Uniformly doped layers, formed by uniform dopant distribution introduced by doping and diffusion processes optimized by a fuzzy logic control system; A surface layer, wherein the surface layer is etched with a preset pattern and the surface layer is subjected to chemical mechanical polishing; and a main layer with low void ratio.

[0016] Compared with the prior art, the present invention has the following beneficial effects: first, the physical parameters of the wafer are determined according to the application requirements of the target wafer, and the optimal seed crystal is selected and surface treatment is performed using a fuzzy logic control system to ensure the quality and adaptability of the seed crystal; second, the crystal growth rate is adjusted by a fuzzy logic control system in a high temperature environment, and the seed crystal and the crucible are rotated to achieve uniform growth of the single crystal, thereby obtaining a high-quality single crystal; the single crystal ingot is cut into wafers and initially ground, and then a chemical mechanical polishing process is adopted, and the pressure, speed and chemical liquid concentration of the polishing pad are dynamically adjusted by a fuzzy logic control system to obtain a wafer with a smooth surface and no stress concentration; then, impurities are introduced by a doping and diffusion process, and the concentration and The temperature gradient is diffused to ensure the uniformity of internal doping, thereby reducing the formation of internal voids; the optimized wafer is patterned and annealed and heat treated, and the annealing curve is optimized by a fuzzy logic control system, including the heating rate, the holding time and the cooling rate, so as to further eliminate stress and defects, and finally prepare a high-quality wafer with zero internal voids; the method introduces a fuzzy logic control system in each key preparation step to achieve intelligent optimization and dynamic adjustment of seed selection, crystal growth rate, grinding and polishing parameters, doping concentration and diffusion temperature gradient and annealing curve, thereby effectively controlling and reducing the generation of voids inside the wafer, and can significantly improve the internal structural integrity of the wafer, and achieve high-quality preparation of wafers with zero internal voids. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0019] Figure 1 This is a schematic diagram of a process of preparing a wafer with zero internal voids according to the first embodiment of the present invention; Figure 2 The second schematic diagram is a flow chart of the method for preparing an internal zero-void wafer of the first embodiment of the present invention; Figure 3This is the third flow chart of the method for preparing an internal zero-void wafer according to the first embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0022] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0023] Embodiment 1: Combination Figures 1 to 3 As shown, an embodiment of the present invention provides a method for preparing an internal zero-void wafer, comprising: Step S1, according to the application requirements of the target wafer, determine the corresponding wafer physical parameters, use the fuzzy logic control system to select the optimal seed crystal, and perform surface treatment on the selected optimal seed crystal; After selecting the optimal seed crystal, surface treatment processes such as cleaning, polishing or chemical modification are performed to remove defects and impurities on the surface of the seed crystal and improve the surface quality of the seed crystal.

[0024] It should be noted that in the internal zero-void wafer preparation method of the present invention, the fuzzy logic control system (FLCS) plays a core intelligent optimization role throughout the key steps of the entire preparation process. The system simulates the decision-making process of technicians in an uncertain and fuzzy environment to achieve dynamic adjustment and optimization of preparation parameters, thereby significantly improving the quality of wafers and the stability of the preparation process. The operating logic of the fuzzy logic control system in this method and its specific application will be explained in detail below.

[0025] Fuzzy logic control system is based on fuzzy set theory and fuzzy reasoning mechanism, which can handle nonlinear and complex process parameter relationships. The system mainly includes the following components: Fuzzification module: converts the input fuzzy data (such as temperature, pressure, doping concentration, etc.) into fuzzy sets for subsequent processing.

[0026] Knowledge base and rule base: Contains professional knowledge and experience-based fuzzy rules to guide the system's decision-making process under different process conditions.

[0027] Inference engine: Based on the fuzzy rule base, it infers the fuzzified input data and generates control instructions.

[0028] Defuzzification module: Converts the inference results into specific control outputs, such as adjusting the temperature gradient or dopant concentration.

[0029] Step S2, using a fuzzy logic control system to adjust the crystal growth rate in a high temperature environment, and achieving the growth of a single crystal by rotating the seed crystal and the crucible to obtain a single crystal; The specific operation includes rotating the seed crystal and crucible to promote uniform growth of the crystal and reduce the accumulation of internal stress. The fuzzy logic control system dynamically adjusts the rotation speed and heating power according to real-time monitoring data (such as temperature, solution concentration and growth rate) to ensure that the crystal remains stable and consistent throughout the growth process. Through this intelligent control method, the formation of crystal defects can be effectively suppressed and high-quality single crystal materials can be obtained.

[0030] In step S3, the single crystal ingot is cut into wafers and initially ground, followed by a chemical mechanical polishing process, and a fuzzy logic control system is used to dynamically adjust the pressure, speed and chemical liquid concentration of the polishing pad to obtain a wafer with a smooth surface.

[0031] Step S4, introducing impurities through doping and diffusion processes, using a fuzzy logic control system to optimize dopant concentration and diffusion temperature gradient, making internal doping uniform to reduce internal voids, and obtaining an optimized wafer; The specific process includes placing the wafer in a high-temperature diffusion furnace, introducing a predetermined concentration of dopant (such as boron, phosphorus or arsenic), and using a fuzzy logic control system to monitor and adjust the temperature distribution and dopant concentration during the diffusion process in real time. This not only improves the uniformity and depth of doping, but also effectively reduces internal stress and void defects, thereby obtaining an optimized internal zero-void wafer.

[0032] Step S5, after pattern etching the optimized wafer, annealing and heat treatment operations are performed, and the fuzzy logic control system is used to optimize the annealing curve. The optimization process includes the heating rate, the holding time and the cooling rate to prepare the finished wafer.

[0033] The fuzzy logic control system dynamically adjusts the annealing parameters based on real-time monitoring data to ensure that the internal stress of the wafer is effectively released during the annealing process, the crystal structure is improved, and finally a high-quality wafer product is produced. This optimization process not only improves the structural integrity of the wafer, but also significantly improves its electrical performance to meet the manufacturing needs of high-performance semiconductor devices.

[0034] It should be noted that the internal zero-void wafer in this solution refers to a wafer with a low void rate close to zero after intelligent preparation.

[0035] The working principle of the present invention is as follows: first, the physical parameters of the wafer are determined according to the application requirements of the target wafer, and the optimal seed crystal is selected and surface treatment is performed using a fuzzy logic control system to ensure the quality and adaptability of the seed crystal; second, the crystal growth rate is adjusted by a fuzzy logic control system in a high-temperature environment, and the seed crystal and the crucible are rotated to achieve uniform growth of the single crystal, thereby obtaining a high-quality single crystal; the single crystal ingot is cut into wafers and initially ground, and then a chemical mechanical polishing process is adopted, and the pressure, speed and chemical liquid concentration of the polishing pad are dynamically adjusted by a fuzzy logic control system to obtain a wafer with a smooth surface and no stress concentration; then, impurities are introduced by a doping and diffusion process, and the concentration of the dopant and the diffusion temperature gradient are optimized by a fuzzy logic control system. degree, ensuring the uniformity of internal doping, thereby reducing the formation of internal voids; pattern etching is performed on the optimized wafer, and annealing and heat treatment operations are performed, and the annealing curve is optimized by the fuzzy logic control system, including the heating rate, the holding time and the cooling rate, so as to further eliminate stress and defects, and finally prepare a high-quality wafer with zero internal voids; the method realizes the intelligent optimization and dynamic adjustment of seed selection, crystal growth rate, grinding and polishing parameters, doping concentration and diffusion temperature gradient and annealing curve by introducing the fuzzy logic control system in each key preparation step, thereby effectively controlling and reducing the generation of voids inside the wafer, and can significantly improve the internal structural integrity of the wafer, and realize high-quality preparation of wafers with zero internal voids.

[0036] In this embodiment, it is specifically described that step S1 specifically includes: Step S11, determining key physical parameters of the wafer according to application requirements of the target wafer by analyzing performance requirements and working environment of the electronic device, wherein the key physical parameters include lattice constant, purity, doping concentration range and thermal conductivity; According to the specific application requirements of the target wafer, the performance parameters and working environment conditions of the required electronic devices are analyzed in detail. For example, high-frequency communications require wafers with high purity and low thermal conductivity, while power devices require wafers with high temperature resistance and high doping uniformity. Based on these analyses, the key physical parameters of the wafer are determined, including lattice constant, purity, doping concentration range and thermal conductivity, to ensure that the wafer can meet the technical requirements of specific applications.

[0037] Step S12, using a fuzzy logic control system to input the key physical parameters, and combining the seed characteristics in the existing seed database, through fuzzy rule evaluation and weight calculation, select the optimal seed that best meets the target parameter requirements; Fuzzy logic control system uses key physical parameters as input, and through pre-set fuzzy rules and weight calculation, comprehensively evaluates multiple seed options in the existing seed database. The system selects the optimal seed that best meets the target physical parameter requirements based on the fuzzy logic reasoning process.

[0038] Step S13, performing surface cleaning treatment on the optimal seed crystal, using a plasma cleaning method at a power of 400 W for 30 minutes to remove organic pollutants and particles on the surface of the seed crystal; The selected optimal seed crystal was cleaned by plasma cleaning at a power of 400 W for 30 minutes to effectively remove organic pollutants and particles on the surface of the seed crystal, ensuring the cleanliness of the seed crystal surface and providing an ideal substrate for subsequent surface finishing and crystal growth.

[0039] Step S14, performing seed crystal surface finishing, treating the seed crystal surface by chemical mechanical polishing process under preset pressure and polishing liquid flow rate conditions, so that the seed crystal surface flatness reaches Ra<1 nm; The surface of the seed crystal is trimmed using a chemical mechanical polishing (CMP) process. The seed crystal surface is polished under a pressure of 5 N and a polishing liquid flow rate of 50 ml / min to ensure that the surface flatness of the seed crystal reaches Ra<1 nm. This step is intended to eliminate the microscopic unevenness of the seed crystal surface and reduce stress concentration and void defects that may occur during subsequent crystal growth.

[0040] Step S15, using a fuzzy logic control system to monitor and adjust the temperature (maintained at 25°C ± 2°C), humidity (controlled at 45% RH ± 5%) and treatment time during the surface treatment process to ensure the consistency and repeatability of the surface treatment, thereby providing high-quality seeds for the subsequent single crystal growth step.

[0041] In this embodiment, it is specifically described that step S2 specifically includes: Step S21, setting and maintaining the temperature required for crystal growth in the high temperature growth chamber, the temperature range is controlled between 1400℃ and 1600℃, to provide appropriate heat energy to promote the stable growth of single crystals. The heating rate and temperature distribution are precisely controlled by the high temperature furnace system, providing sufficient heat energy to promote the orderly arrangement and growth of crystals.

[0042] Step S22, inputting key physical parameters and growth requirements of the wafer through a fuzzy logic control system, the growth requirements including growth rate, temperature gradient and environmental pressure, and evaluating and calculating the optimal growth conditions in real time; The fuzzy logic control system takes the key physical parameters of the wafer and the growth requirements as input. The system evaluates the current growth conditions in real time through preset fuzzy rules and weight calculations, and calculates the optimal combination of growth parameters to achieve the generation of high-quality single crystals.

[0043] Step S23, start the rotating device to rotate the seed crystal at a speed of 300 to 500 revolutions per minute, and the crucible at a speed of 100 to 200 revolutions per minute; to ensure the uniformity of the crystal during the growth process and reduce stress concentration.

[0044] Start the rotating device to rotate the seed crystal at a speed of 300 to 500 revolutions per minute, and the crucible rotates at a speed of 100 to 200 revolutions per minute. This dual rotation method helps to maintain uniform mixing of the seed crystal and the melt during the growth process, reduce stress concentration caused by uneven gravity, promote uniform growth of crystals, and reduce the probability of defect and void formation.

[0045] Step S24, based on the data feedback of real-time monitoring of the rotation speed and temperature of the rotating device, the fuzzy logic control system is used to dynamically adjust the rotation speed and temperature gradient to optimize the crystal growth rate, thereby preventing crystal defects caused by excessively fast or slow growth.

[0046] The rotation speed and temperature gradient are dynamically adjusted through the fuzzy logic control system. Based on the real-time monitoring data feedback, the system intelligently optimizes the crystal growth rate to ensure a smooth growth process and prevent crystal defects such as stacking faults and voids caused by improper growth rate.

[0047] Step S25, during the single crystal growth process, using thermocouples and optical sensors to monitor the temperature distribution of the growth environment and the crystal surface morphology in real time, and inputting the data into the fuzzy logic control system for analysis and adjustment; During the single crystal growth process, high-precision thermocouples and optical sensors are used to monitor the temperature distribution of the growth environment and the crystal surface morphology in real time. The collected data is input into the fuzzy logic control system, which analyzes and adjusts the growth parameters to maintain the best growth conditions and ensure that the crystal surface is flat and has minimal defects.

[0048] Step S26, coordinating atmosphere control through a fuzzy logic control system, the atmosphere control process includes adjusting the inert gas flow and pressure; maintaining a stable growth environment to prevent the introduction of impurities and the formation of voids.

[0049] Step S27, after the single crystal growth is completed, the temperature of the growth chamber is lowered to room temperature, and a gradual cooling technique is used to reduce the stress inside the crystal and prevent the generation of thermal cracks to obtain a single crystal.

[0050] The gradual cooling technology is adopted. This process adjusts the cooling rate through a fuzzy logic control system to prevent thermal stress and cracks caused by sudden temperature drop, ensuring the integrity and stability of the single crystal structure.

[0051] The single crystals grown are subjected to preliminary quality inspection, including measuring the diameter, thickness and defect-free area ratio of the crystals. Through optical microscopy and X-ray diffraction and other inspection methods, it is confirmed that the single crystals meet the high standards required for subsequent preparation steps, laying the foundation for subsequent wafer cutting and grinding.

[0052] In this embodiment, it is specifically described that step S3 specifically includes: Step S31, fixing the single crystal ingot on a cutting device, using a diamond wire saw to cut the wafer, and controlling the cutting rate to 20 to 30 mm per minute to ensure the thickness uniformity and edge smoothness of the wafer.

[0053] Step S32, performing preliminary grinding on the cut wafers, using a grinding wheel grinder and abrasives of appropriate particle size (such as 1200 mesh alumina grinding wheels), grinding at a speed of 500 to 700 revolutions per minute to remove microscopic defects and surface roughness generated during the cutting process.

[0054] Step S33, cleaning the wafer after preliminary grinding, using deionized water and ultrasonic cleaning technology, and the cleaning time is continuous for 10 minutes to remove the abrasive and particles remaining in the grinding process; ensure the cleanliness of the wafer surface.

[0055] Step S34, implement chemical mechanical polishing process to further polish the wafer surface. During the polishing process, a polishing slurry containing aluminum oxide particles is used, the polishing liquid flow rate is controlled at 100 to 150 ml / min, the polishing pressure is maintained at 5 to 10N, and the polishing disk speed is set at 50 to 100 rpm.

[0056] Step S35, dynamically adjusting the pressure, speed and chemical liquid concentration of the polishing pad through a fuzzy logic control system; specifically including: the fuzzy logic control system adjusts the pressure applied by the polishing pad to between 5 and 10 Newtons, the rotation speed of the polishing disk to between 50 and 100 rpm, and the concentration of aluminum oxide particles in the chemical slurry to between 5% and 15% based on the real-time monitored wafer surface roughness data; to achieve optimal surface smoothness.

[0057] Step S36, after the chemical mechanical polishing is completed, the surface morphology is detected by using an optical scanning device to detect the surface of the wafer and record the detection data.

[0058] Step S37, based on the surface morphology detection result, feedback is given to the fuzzy logic control system. If it is detected that the surface roughness does not meet the standard, the polishing parameters are adjusted and the polishing process is performed again until the wafer surface reaches the predetermined surface roughness standard.

[0059] In this embodiment, it is specifically described that step S4 specifically includes: Step S41, placing the wafer that has undergone chemical mechanical polishing in a high-temperature diffusion furnace, and introducing a dopant of a predetermined concentration by a diffusion process; the concentration range of the dopant is controlled to be 1×1014 to 1×1016 cm-3 to achieve the desired electrical characteristics.

[0060] Step S42, key control parameters of dopant concentration, diffusion temperature gradient and diffusion time are input through the fuzzy logic control system, and the temperature distribution and dopant concentration in the diffusion process are monitored and dynamically adjusted in real time to ensure the uniformity and depth of doping.

[0061] Step S43, during the diffusion process, the temperature gradient control technology is used to make the temperature of the wafer in the diffusion furnace increase or decrease linearly along the vertical direction, and the temperature gradient range is controlled within 50 to 200°C / cm, so as to promote uniform diffusion of dopants and reduce internal stress.

[0062] Step S44, using the fuzzy logic control system to automatically adjust the heating power and cooling rate of the diffusion furnace according to the real-time feedback data of the doping concentration distribution and the temperature gradient change, to optimize the diffusion environment and prevent excessive diffusion or uneven dopant concentration.

[0063] Step S45, after the diffusion is completed, slowly cool the wafer to room temperature, using a gradual cooling technique to reduce thermal stress and crystal defects inside the wafer.

[0064] Step S46, performing doping uniformity detection on the diffused wafer, using ion detection technology to measure the doping concentration distribution, and confirming that the doping concentration is within a preset range.

[0065] Ensure that the concentration of dopants inside the wafer is uniform and that the overall doping concentration meets the predetermined electrical property requirements.

[0066] After the doping and diffusion processes are completed, the wafers are finally cleaned using a mixture of deionized water and high-purity organic solvents (such as isopropyl alcohol) to remove dopant particles and contaminants that may remain during the diffusion process, ensuring that the cleanliness of the wafers meets the requirements of subsequent processes.

[0067] In this embodiment, it is further explained that after step S5, the following steps are further included: Step S6, performing quality inspection on the finished wafer product, evaluating the wafer quality based on the inspection data, and feeding back to the fuzzy logic control system to adjust the logic preference of its process parameters to optimize the wafer preparation process.

[0068] Embodiment 2: The present invention further provides an internal zero-void wafer, which is prepared by the method for preparing the internal zero-void wafer of the first embodiment, and the internal zero-void wafer specifically comprises: Single crystal substrate, formed by a crystal growth process from selected optimal seeds; has excellent crystal structure and low defect density.

[0069] Uniform doping layer, formed by uniform dopant distribution introduced by doping and diffusion process optimized by fuzzy logic control system; ensuring consistency of doping concentration inside the wafer and reducing internal voids.

[0070] The surface layer is etched with a preset pattern and is subjected to chemical mechanical polishing.

[0071] The preset pattern forms a fine pattern that meets the design requirements on the surface layer of the wafer for the manufacture of integrated circuits.

[0072] And a main layer with low void ratio. The void ratio inside the wafer of the main layer is significantly reduced, ensuring its application performance in high-reliability electronic devices.

[0073] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing an internal zero-void wafer, characterized in that: include: Step S1, according to the application requirements of the target wafer, determine the corresponding wafer physical parameters, use the fuzzy logic control system to select the optimal seed crystal, and perform surface treatment on the selected optimal seed crystal; Step S2, using a fuzzy logic control system to adjust the crystal growth rate in a high temperature environment, and achieving the growth of a single crystal by rotating the seed crystal and the crucible to obtain a single crystal; Step S3, cutting the single crystal ingot into wafers and performing preliminary grinding, then using a chemical mechanical polishing process, and dynamically adjusting the pressure, speed and chemical liquid concentration of the polishing pad through a fuzzy logic control system to obtain a wafer with a smooth surface; Step S4, introducing impurities through doping and diffusion processes, using a fuzzy logic control system to optimize dopant concentration and diffusion temperature gradient, making internal doping uniform to reduce internal voids, and obtaining an optimized wafer; Step S5, after pattern etching the optimized wafer, annealing and heat treatment operations are performed, and the fuzzy logic control system is used to optimize the annealing curve. The optimization process includes the heating rate, the holding time and the cooling rate to prepare the finished wafer.

2. The method for preparing an internal zero-void wafer according to claim 1, characterized in that: The step S1 specifically includes: Step S11, determining key physical parameters of the wafer according to application requirements of the target wafer by analyzing performance requirements and working environment of the electronic device, wherein the key physical parameters include lattice constant, purity, doping concentration range and thermal conductivity; Step S12, using a fuzzy logic control system to input the key physical parameters, and combining the seed characteristics in the existing seed database, through fuzzy rule evaluation and weight calculation, select the optimal seed that best meets the target parameter requirements; Step S13, performing surface cleaning treatment on the optimal seed crystal, using a plasma cleaning method at a power of 400 W for 30 minutes to remove organic pollutants and particles on the surface of the seed crystal; Step S14, performing seed crystal surface finishing, treating the seed crystal surface by chemical mechanical polishing process under preset pressure and polishing liquid flow rate conditions, so that the seed crystal surface flatness reaches Ra < 1 nm; Step S15, using a fuzzy logic control system to monitor and adjust the temperature, humidity and treatment time during the surface treatment process.

3. The method for preparing an internal zero-void wafer according to claim 1, characterized in that: The step S2 specifically includes: Step S21, setting and maintaining the temperature required for crystal growth in the high temperature growth chamber, the temperature range being controlled between 1400° C. and 1600° C.; Step S22, inputting key physical parameters and growth requirements of the wafer through a fuzzy logic control system, the growth requirements including growth rate, temperature gradient and environmental pressure, and evaluating and calculating the optimal growth conditions in real time; Step S23, starting the rotating device to rotate the seed crystal at a speed of 300 to 500 revolutions per minute, and the crucible at a speed of 100 to 200 revolutions per minute; Step S24, based on the data feedback of real-time monitoring of the rotation speed and temperature of the rotating device, the fuzzy logic control system is used to dynamically adjust the rotation speed and temperature gradient to optimize the crystal growth rate.

4. The method for preparing an internal zero-void wafer according to claim 3, characterized in that: After step S24, the following steps are also included: Step S25, during the single crystal growth process, using thermocouples and optical sensors to monitor the temperature distribution of the growth environment and the crystal surface morphology in real time, and inputting the data into the fuzzy logic control system for analysis and adjustment; Step S26, coordinating atmosphere control through a fuzzy logic control system, the atmosphere control process includes adjusting the inert gas flow and pressure; Step S27, after the single crystal growth is completed, the temperature of the growth chamber is lowered to room temperature, and a gradual cooling technique is used to reduce the stress inside the crystal and prevent the generation of thermal cracks to obtain a single crystal.

5. The method for preparing an internal zero-void wafer according to claim 1, characterized in that: The step S3 specifically includes: Step S31, fixing the single crystal ingot on a cutting device, using a diamond wire saw to cut the wafer, and controlling the cutting rate to 20 to 30 mm per minute; Step S32, performing preliminary grinding on the cut wafers, using a grinding wheel grinder at a speed of 500 to 700 revolutions per minute; Step S33, cleaning the wafer after preliminary grinding, using deionized water and ultrasonic cleaning technology, and the cleaning time is 10 minutes to remove the abrasive and particles remaining in the grinding process; Step S34, implement chemical mechanical polishing process to further polish the wafer surface. During the polishing process, a polishing slurry containing aluminum oxide particles is used, the polishing liquid flow rate is controlled at 100 to 150 ml / min, the polishing pressure is maintained at 5 to 10N, and the polishing disk speed is set at 50 to 100 rpm.

6. The method for preparing an internal zero-void wafer according to claim 5, characterized in that: After step S34, the following steps are also included: Step S35, dynamically adjusting the pressure, speed and chemical solution concentration of the polishing pad by a fuzzy logic control system; specifically, the fuzzy logic control system adjusts the pressure applied by the polishing pad to a range of 5 to 10 Newtons, the rotation speed of the polishing disk to a range of 50 to 100 revolutions per minute, and the concentration of aluminum oxide particles in the chemical slurry to a range of 5% to 15% according to the real-time monitored surface roughness data of the wafer; Step S36, after the chemical mechanical polishing is completed, the surface morphology is detected, the surface of the wafer is detected using an optical scanning device, and the detection data is recorded; Step S37, based on the surface morphology detection result, feedback is given to the fuzzy logic control system. If it is detected that the surface roughness does not meet the standard, the polishing parameters are adjusted and the polishing process is performed again until the wafer surface reaches the predetermined surface roughness standard.

7. The method for preparing an internal zero-void wafer according to claim 1, characterized in that: The step S4 specifically includes: Step S41, placing the wafer that has undergone chemical mechanical polishing in a high-temperature diffusion furnace, and introducing a dopant of a predetermined concentration by a diffusion process; Step S42, inputting key control parameters of dopant concentration, diffusion temperature gradient and diffusion time through a fuzzy logic control system, real-time monitoring and dynamic adjustment of temperature distribution and dopant concentration during the diffusion process; Step S43, during the diffusion process, temperature gradient control technology is used to make the temperature of the wafer in the diffusion furnace increase or decrease linearly in the vertical direction, and the temperature gradient range is controlled within a range of 50 to 200°C / cm.

8. The method for preparing an internal zero-void wafer according to claim 7, characterized in that: After step S43, the following steps are further included: Step S44, using a fuzzy logic control system to automatically adjust the heating power and cooling rate of the diffusion furnace according to the real-time feedback data of the doping concentration distribution and the temperature gradient change, so as to optimize the diffusion environment; Step S45, after the diffusion is completed, slowly cooling the wafer to room temperature, using a gradual cooling technique to reduce thermal stress and crystal defects inside the wafer; Step S46, performing doping uniformity detection on the diffused wafer, using ion detection technology to measure the doping concentration distribution, and confirming that the doping concentration is within a preset range.

9. The method for preparing an internal zero-void wafer according to claim 1, characterized in that: After step S5, the following steps are also included: Step S6, performing quality inspection on the finished wafer product, evaluating the wafer quality based on the inspection data, and feeding back to the fuzzy logic control system to adjust the logic preference of its process parameters to optimize the wafer preparation process.

10. An internal zero-void wafer, characterized in that: The method for preparing an internal zero-void wafer according to any one of claims 1 to 9 is used, wherein the internal zero-void wafer specifically comprises: A single crystal substrate is formed by a crystal growth process using a selected optimal seed crystal; Uniformly doped layers, formed by uniform dopant distribution introduced by doping and diffusion processes optimized by a fuzzy logic control system; A surface layer, wherein the surface layer is etched with a preset pattern and the surface layer is subjected to chemical mechanical polishing; and a main layer with low void ratio.

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