High-speed clock duty ratio stabilizing circuit
By designing a high-speed clock duty cycle stabilization circuit, using components such as inverter, NAND gate, voltage-controlled delay circuit, Schmitt trigger circuit and integrator, the low jitter and 50% duty cycle adjustment of the clock signal in a high-speed ADC are achieved, solving the problem that external clock sources cannot provide low jitter clock signals and improving ADC performance.
Patent Information
- Application Number
- CN202411661425.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-02-28
AI Technical Summary
In high-speed ADC, the external clock source cannot provide a low jitter clock signal, which cannot meet the low jitter requirements of the high-speed ADC for the sampled clock signal.
A high-speed clock duty cycle stabilization circuit is designed, including a first inverter, a second inverter, a NAND gate, a voltage-controlled delay circuit, a Schmitt trigger circuit, an integrator and a current mirror module. Through the cooperation of these components, the duty cycle adjustment of the clock signal is realized.
It realizes the duty cycle of the input high-speed clock signal to 50% in a short time, which meets the low jitter requirements of high-speed ADCs for sampling clock signals and improves ADC performance.
Smart Images
Figure CN119543895A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of CMOS digital-analog hybrid integrated circuits, and in particular to a clock duty cycle adjustment technology for a high-speed analog-to-digital converter (ADC) circuit system. Background Art
[0002] In high-speed and high-precision ADCs, in order to ensure that the external clock source has a small enough impact on system performance, a low-jitter clock signal must be provided for the sampling circuit. Usually, since the external crystal oscillator can only generate a relatively accurate clock signal when it is less than 50MHz, it cannot meet the low-jitter requirements of the high-speed ADC for the sampling clock signal. It is necessary to provide a low-jitter clock duty cycle stabilization circuit inside the ADC to stabilize the duty cycle of the external high-speed clock signal before use. Summary of the invention
[0003] The present invention provides a clock duty cycle adjustment circuit, which adjusts the duty cycle of an input high-speed clock signal to 50% in a relatively short time, and aims to accurately adjust a clock signal with a duty cycle of 20% to 80%.
[0004] The present invention adopts the following technical solution: a high-speed clock duty cycle stabilization circuit, comprising: a first inverter, a second inverter, a first NAND gate, a second NAND gate, a third NAND gate, a voltage-controlled delay circuit, a Schmitt trigger circuit, an integrator and a current mirror module,
[0005] The first inverter has an input end for inputting a clock signal, and an output end connected to a first input terminal of the first NAND gate and a first input terminal of the third NAND gate;
[0006] The second inverter has an input end connected to the Schmitt trigger circuit and an output end connected to the second input end of the second NAND gate; the first input end of the second NAND gate is connected to the output end of the third NAND gate, the second input end of the third NAND gate is connected to the output end of the second NAND gate, and the output end of the second NAND gate is used as a clock signal output end and is also connected to the second input end of the first NAND gate and the input end of the integrator;
[0007] The output end of the first NAND gate is connected to the first input end of the voltage-controlled delay circuit; the output end of the integrator is connected to the second input end of the voltage-controlled delay circuit;
[0008] The output end of the voltage-controlled delay circuit is connected to the input end of the Schmitt trigger circuit and the current mirror module, and the output end of the Schmitt trigger circuit outputs a feedback signal to the input end of the second inverter.
[0009] The voltage-controlled delay circuit includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first capacitor;
[0010] The first PMOS transistor gate is connected to the first NMOS transistor gate and serves as the first input terminal of the voltage-controlled delay circuit and is connected to the output terminal of the first NAND gate;
[0011] The source of the first PMOS tube is connected to the power supply; the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and serves as the output end of the voltage-controlled delay circuit, and is connected to the input end of the Schmitt trigger circuit and the current source module;
[0012] The source of the first NMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is grounded; a first capacitor is connected between the source of the second NMOS tube and the drain of the first NMOS tube; the gate of the second NMOS tube serves as the second input end of the voltage-controlled delay circuit and is connected to the output end of the integrator.
[0013] The integrator includes a first resistor, a second capacitor, a third capacitor and an operational amplifier;
[0014] One end of the first resistor is used as the input end of the integrator and is connected to the clock signal output end, and the other end of the first resistor is connected to the reverse input end of the operational amplifier; the positive input end of the operational amplifier is connected to the reference voltage;
[0015] The output end of the operational amplifier serves as the output end of the integrator and is grounded via the second capacitor; a third capacitor is connected between the output end and the reverse input end of the operational amplifier.
[0016] The Schmitt trigger circuit includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, and a fifth NMOS tube;
[0017] The gate of the second PMOS tube is connected to the gate of the third PMOS tube, the gate of the third NMOS tube, and the gate of the fourth NMOS tube, and serves as the input end of the Schmitt trigger circuit; the source of the second PMOS tube is connected to the power supply, and the drain of the second PMOS tube is connected to the source of the third PMOS tube and the source of the fourth PMOS tube; the drain of the third PMOS tube is connected to the drain of the third NMOS tube, the gate of the fourth PMOS tube, and the gate of the fifth NMOS tube, and serves as the output end of the Schmitt trigger circuit; the drain of the fourth PMOS tube is grounded; the source of the third NMOS tube is connected to the source of the fifth NMOS tube and the drain of the fourth NMOS tube; the drain of the fifth NMOS tube is connected to the power supply; and the source of the fourth NMOS tube is connected to the ground.
[0018] The current mirror module includes two NMOS tubes;
[0019] The gates of the two NMOS tubes are connected to each other and the sources are grounded; the drain of one NMOS tube is connected to the current source, and the drain of the other NMOS tube serves as the output end of the current mirror module and is connected to the output end of the voltage-controlled delay circuit.
[0020] A high-speed clock duty cycle stable output method comprises the following steps:
[0021] The input end of the first inverter receives the clock signal CLKIN, and the input end of the second inverter receives the feedback signal of the Schmitt trigger circuit. The rising edges of the two input signals are detected through the second NAND gate and the third NAND gate, and the phase difference between the two input signals is represented by the pulse width of the output signal CLKOUT.
[0022] During the adjustment process, the rising edge of the output signal CLKOUT is always aligned with the rising edge of the clock signal CLKIN, and the duty cycle of the output signal is adjusted only by changing the triggering time of its falling edge.
[0023] In the adjustment process, the rising edge of the output signal CLKOUT is always aligned with the rising edge of the clock signal CLKIN, and the duty cycle of the output signal is adjusted only by changing the trigger time of the falling edge thereof, including the following steps:
[0024] If the duty cycle of the output signal CLKOUT is less than 50%, the integrator output voltage A increases, causing the gate control voltage of the second NMOS transistor in the voltage-controlled delay circuit to decrease, and the discharge current of the first capacitor through the first NMOS transistor and the second NMOS transistor to decrease, and the discharge time is prolonged. The rising edge of the feedback signal after passing through the Schmitt trigger circuit is delayed, and the duty cycle of the output signal CLKOUT increases until it reaches 50%;
[0025] If the duty cycle of the output signal CLKOUT is greater than 50%, the integrator output voltage A decreases, causing the control voltage of the voltage-controlled delay circuit to increase, and the discharge current of the first capacitor through the first NMOS tube and the second NMOS tube increases, the discharge time is shortened, and the rising edge of the feedback signal passing through the Schmitt trigger circuit is advanced, and the duty cycle of the output signal CLKOUT decreases until it reaches 50%.
[0026] The present invention produces the following beneficial effects and advantages:
[0027] 1. In a high-speed ADC, when the input signal frequency is greater than 40MHz, the clock duty cycle generated by the external oscillator may not be stable at 50%, and the ADC's requirements for the sampling clock cannot be met, resulting in a decrease in ADC performance. The present invention implements a high-speed clock duty cycle stabilization circuit system by using an integrator, a voltage-controlled delay circuit, a Schmitt trigger circuit, a voltage-controlled delay circuit, a NAND gate 1, a NAND gate 2, a NAND gate 3, an inverter 1, and an inverter 2. The system comprises a phase detector composed of a NAND gate 2 and a NAND gate 3, which compares the input clock signal with the clock signal generated by the integrator, the voltage-controlled delay circuit, and the Schmitt trigger circuit, and then outputs the phase difference between the two clock signals, which is a clock signal with a duty cycle of 50%.
[0028] 2. Compared with the prior art, the present invention does not use a charge pump, a delay unit and a filter, has a stable structure, and is not affected by the process, voltage and temperature. At the same time, a negative feedback structure is used to make the result more accurate.
[0029] 3. The duty cycle adjustment circuit described in the present invention has the advantages of simple filter circuit structure, fast locking speed, good anti-clock jitter performance, flexible implementation method, and smaller phase jitter. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 The figure is a schematic diagram of the circuit structure principle of the high-speed clock duty cycle stabilization circuit of the present invention.
[0031] Figure 2 This is the circuit diagram of the operational amplifier in the integrator.
[0032] Figure 3 The figure is a simulation result diagram of the clock input signal CLKIN, the clock output signal CLKOUT and the integrator output voltage A after the circuit is locked.
[0033] Figure 4 This is the simulation result diagram of the integrator output voltage A. DETAILED DESCRIPTION
[0034] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.
[0035] A high-speed clock duty cycle stabilization circuit, which can reach a clock duty cycle stabilization circuit of more than 40MHz, comprises an integrator, a voltage-controlled delay circuit connected to the integrator, a Schmitt trigger circuit connected to the voltage-controlled delay unit, a second inverter connected to the Schmitt trigger circuit, a second NAND gate connected to the second inverter, a clock signal output end connected to the second NAND gate, a clock signal input end, a first inverter connected to the clock signal input end, a first NAND gate connected to the first inverter, a third NAND gate connected to the first inverter and a current mirror module connected to the voltage-controlled delay circuit, a current source connected to the current mirror module, and a common-mode signal input end, wherein the clock signal output end is connected between the first inverter, the integrator and the third inverter, the third NAND gate is connected to the second NAND gate, the first NAND gate is connected to the voltage-controlled delay circuit, and the common-mode signal input end is connected to the integrator.
[0036] The input end of the first inverter is connected to the clock signal input end; the output end of the first inverter is connected to one input end of the first NAND gate and the third NAND gate.
[0037] The other input of the first NAND gate is connected to the clock signal output, the output of the second NAND gate, the other input of the third NAND gate and the input of the integrator, and the output is connected to the first input of the voltage-controlled delay circuit.
[0038] An output terminal of the third NAND gate is connected to an input terminal of the second NAND gate.
[0039] The voltage-controlled delay circuit includes a first PMOS tube, a first NMOS tube, a second NMOS tube and a first capacitor, wherein the first PMOS tube and the first NMOS tube gates are connected to each other and to the first input end of the voltage-controlled delay circuit; the first PMOS tube source is connected to a power supply; the first PMOS tube drain is connected to the first NMOS tube drain, the first stage of the first capacitor and the output end of the voltage-controlled delay circuit, and the output end of the voltage-controlled delay circuit is connected to the Schmitt trigger circuit input end and the output end of the current source module; the first NMOS tube source is connected to the second NMOS tube drain, and the second NMOS tube source and the other end of the first capacitor are connected to the ground; the second NMOS tube gate is connected to the second input end of the voltage-controlled delay circuit and to the output end of the integrator.
[0040] The integrator includes a first resistor, a second capacitor, a third capacitor and an operational amplifier. One end of the first resistor is connected to the first input end of the integrator, the other end of the first resistor is connected to the reverse input end of the operational amplifier and one end of the third capacitor, the positive input end of the operational amplifier is connected to the second input end of the integrator, the output of the operational amplifier is connected to the other end of the third capacitor and one end of the second capacitor and connected to the output end of the integrator; the other end of the second capacitor is connected to the ground.
[0041] The Schmitt trigger circuit includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, and a fifth NMOS tube.
[0042] The gate of the second PMOS tube is connected to the gates of the third PMOS tube, the third NMOS tube and the fourth NMOS tube, and is connected to the input end of the Schmitt trigger circuit; the source of the second PMOS tube is connected to a power supply; the drain of the second PMOS tube is connected to the source of the third PMOS tube and is connected to the source of the fourth PMOS tube; the drain of the third PMOS tube is connected to the drain of the third NMOS tube, the gate of the fourth PMOS tube, and the gate of the fifth NMOS tube, and is connected to the output end of the Schmitt trigger circuit; the drain of the fourth PMOS tube is connected to ground; the source of the third NMOS tube is connected to the source of the fifth NMOS tube and the drain of the fourth NMOS tube; the drain of the fifth NMOS tube is connected to the power supply; the source of the fourth NMOS tube is connected to ground.
[0043] The input end of the second inverter is connected to the output end of the Schmitt trigger circuit, and the output end of the second inverter is connected to the other input end of the second NAND gate.
[0044] The current mirror module includes a zeroth NMOS tube and a sixth NMOS tube. The drain of the zeroth NMOS tube is connected to the current source and to the gates of the zeroth and sixth NMOS tubes; the source of the zeroth NMOS tube is connected to the source of the sixth NMOS tube and to the ground; the drain of the sixth NMOS tube is connected to the output end of the current mirror module.
[0045] like Figure 1 As shown, the present invention discloses a high-speed clock duty cycle stabilization circuit, which includes the first and second inverters and the first, second and third NAND gates, an integrator, a voltage-controlled delay circuit, a Schmitt trigger circuit and a current mirror module.
[0046] The first, second and third NAND gates nand1, nand2 and nand3 constitute an SR latch, and the SR latch and the first and second inverters inv1 and inv2 together constitute a phase detector circuit. The phase detector circuit has a linear phase detection range of -π to +π. One input terminal of the phase detector is connected to the input clock signal CLKIN, and the other input terminal is the feedback signal of the Schmitt trigger circuit. The SR latch detects the rising edges of the two input signals and represents the phase difference of the two input signals with the pulse width of the output signal CLKOUT; during the adjustment process, the rising edge of the output signal CLKOUT is always aligned with the rising edge of the reference clock signal, and the duty cycle of the output signal is adjusted only by changing the trigger time of its falling edge. When the phase difference between the input clock signal CLKIN and the feedback signal of the Schmitt trigger circuit is nπ (n is an odd number), an output clock signal CLKOUT with a duty cycle of 50% can be obtained.
[0047] The positive input terminal of the integrator is connected to a reference voltage of VCM, and the negative input terminal is connected to the clock signal output terminal through the first resistor R1. When the clock signal output terminal is at a low level, the third capacitor C3 is charged, and the output voltage of the integrator rises linearly; when the clock signal output terminal is at a high level, the third capacitor C3 is discharged, and the output voltage of the integrator decreases linearly; regardless of the capacitor charging or discharging state, the rising slope and the falling slope of the integrator output voltage A are equal, and the output of the integrator is approximately a triangular wave. When the duty cycle of the clock signal CLKOUT is 50%, since the rising time and the falling time are equal, the integrator output signal is a triangular wave that fluctuates around a certain DC voltage; when the clock signal CLKOUT duty cycle is less than 50%, the rising time is greater than the falling time, and the integrator output signal is a gradually rising triangular wave; when the clock signal CLKOUT duty cycle is greater than 50%, the rising time is less than the falling time, and the integrator output signal is a gradually falling triangular wave. It can be seen that only when the duty cycle of the clock signal CLKOUT is 50%, the output voltage of the integrator will remain constant. At this time, the loop is stable and the system locks the duty cycle of CLKOUT.
[0048] like Figure 2As shown, it is an operational amplifier circuit in the integrator circuit, and the operational amplifier includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and the fourth capacitor. Among them, the source of the fifth PMOS tube is connected to the source of the sixth PMOS tube and is connected to the power supply VDD; the gate of the fifth PMOS tube is connected to the sixth PMOS tube and is connected to Vb; the drain of the fifth PMOS tube is connected to the sources of the seventh and eighth PMOS tubes; the gate of the seventh PMOS tube is connected to Vin+; the source of the seventh PMOS tube is connected to the drain and gate of the seventh NMOS tube and is connected to the gate of the eighth NMOS tube; the source of the seventh NMOS tube is connected to the sources of the eighth and ninth NMOS tubes and is connected to the ground GND; the drain of the eighth NMOS tube is connected to the source of the eighth PMOS tube and is connected to one end of the fourth capacitor and the gate of the ninth NMOS tube; the gate of the eighth PMOS tube is connected to Vin-; the other end of the fourth capacitor is connected to the drain of the sixth PMOS tube, connected to the drain of the ninth NMOS tube, and connected to the output end Vout.
[0049] The output signal of the voltage-controlled delay circuit is not an ideal square wave signal and needs to be shaped by a Schmitt trigger circuit, and its output signal is fed back to the phase detector. The output signal from the voltage-controlled delay circuit charges the first capacitor C1 at a fixed time. When the input signal of the voltage-controlled delay circuit, i.e., the output signal of the first NAND gate, is at a low level, the first PMOS tube Mp1 is turned on, the first NMOS tube Mn1 is turned off, and the first capacitor C1 is quickly charged through the first PMOS tube Mp1; otherwise, the first NMOS tube Mn1 is turned on, the first PMOS tube Mp1 is turned off, and the first capacitor C1 is discharged through the first PMOS tube Mp1. Since the second NMOS tube Mn2 works in the saturation region, the magnitude of the discharge current depends on the gate voltage of the second NMOS tube Mn2, that is, the output voltage of the integrator. When the gate voltage of the second NMOS tube Mn2 decreases, the discharge current of the first capacitor C1 decreases. It can be seen from Q=I×t that Q is the charge and I is the current. The discharge time t will be extended, the rising edge of the feedback signal of the Schmitt trigger circuit will be delayed, and the duty cycle of the phase detector output signal will increase. Since the first capacitor C1 is always charged at a fixed time, the rising edge of the feedback signal of the Schmitt trigger circuit is always triggered at a fixed time, and the phenomenon of the rising edge and the falling edge coinciding will not occur during the adjustment process. When the gate voltage of the second NMOS tube Mn2 increases, the discharge current of the first capacitor C1 increases, the discharge time is shortened, the rising edge of the feedback signal of the Schmitt trigger circuit will be advanced, and the duty cycle of the phase detector output signal is reduced. The current mirror module generates a constant current to discharge the first capacitor C1, speeding up the settling time.
[0050] The principle of the high-speed duty cycle stabilization circuit is: when the system is locked, a square wave signal CLKOUT with a duty cycle of 50% can be generated. If the duty cycle of the output signal CLKOUT is less than 50%, the integrator output voltage A increases, causing the gate control voltage of the second NMOS tube Mn2 in the voltage-controlled delay circuit to decrease, the discharge current of the first capacitor C1 through the first NMOS tube Mn1 and the second NMOS tube Mn2 to decrease, the discharge time to extend, the rising edge of the feedback signal after passing through the Schmitt trigger circuit is delayed, and the duty cycle of the output signal CLKOUT increases until it reaches 50%. On the contrary, if the duty cycle of the output signal CLKOUT is greater than 50%, the integrator output voltage A decreases, causing the control voltage of the voltage-controlled delay circuit to increase, the discharge current of the first capacitor through the first NMOS Mn1 tube and the second NMOS tube Mn2 to increase, the discharge time to shorten, the rising edge of the feedback signal after passing through the Schmitt trigger circuit to advance, and the duty cycle of the output signal CLKOUT decreases until it reaches 50%.
[0051] refer to Figure 3 In the timing diagram, CLKIN is the input clock signal waveform with a duty cycle of 80%, and CLKOUT is the output clock signal with a duty cycle of 50% after passing through the duty cycle stabilization circuit.
[0052] refer to Figure 4 , A is the output waveform of the integrator. After several cycles, the system is locked and the integrator output voltage A tends to be stable.
[0053] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A high-speed clock duty cycle stabilization circuit, characterized in that: include: a first inverter, a second inverter, a first NAND gate, a second NAND gate, a third NAND gate, a voltage-controlled delay circuit, a Schmitt trigger circuit, an integrator, and a current mirror module, The first inverter has an input end for inputting a clock signal, and an output end connected to a first input terminal of the first NAND gate and a first input terminal of the third NAND gate; The second inverter has an input end connected to the Schmitt trigger circuit and an output end connected to the second input end of the second NAND gate; The first input terminal of the second NAND gate is connected to the output terminal of the third NAND gate, the second input terminal of the third NAND gate is connected to the output terminal of the second NAND gate, and the output terminal of the second NAND gate is used as a clock signal output terminal and is also connected to the second input terminal of the first NAND gate and the input terminal of the integrator; The output end of the first NAND gate is connected to the first input end of the voltage-controlled delay circuit; the output end of the integrator is connected to the second input end of the voltage-controlled delay circuit; The output end of the voltage-controlled delay circuit is connected to the input end of the Schmitt trigger circuit and the current mirror module, and the output end of the Schmitt trigger circuit outputs a feedback signal to the input end of the second inverter.
2. A high-speed clock duty cycle stabilization circuit as claimed in claim 1, characterized in that: The voltage-controlled delay circuit includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first capacitor; The first PMOS transistor gate is connected to the first NMOS transistor gate and serves as the first input terminal of the voltage-controlled delay circuit and is connected to the output terminal of the first NAND gate; The source of the first PMOS tube is connected to the power supply; the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and serves as the output end of the voltage-controlled delay circuit, and is connected to the input end of the Schmitt trigger circuit and the current source module; The source of the first NMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is grounded; a first capacitor is connected between the source of the second NMOS tube and the drain of the first NMOS tube; the gate of the second NMOS tube serves as the second input end of the voltage-controlled delay circuit and is connected to the output end of the integrator.
3. A high-speed clock duty cycle stabilization circuit as claimed in claim 1, characterized in that: The integrator includes a first resistor, a second capacitor, a third capacitor and an operational amplifier; One end of the first resistor is used as the input end of the integrator and is connected to the clock signal output end, and the other end of the first resistor is connected to the reverse input end of the operational amplifier; the positive input end of the operational amplifier is connected to the reference voltage; The output end of the operational amplifier serves as the output end of the integrator and is grounded via the second capacitor; a third capacitor is connected between the output end and the reverse input end of the operational amplifier.
4. A high-speed clock duty cycle stabilization circuit as claimed in claim 1, characterized in that: The Schmitt trigger circuit includes a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, and a fifth NMOS tube; The gate of the second PMOS tube is connected to the gate of the third PMOS tube, the gate of the third NMOS tube, and the gate of the fourth NMOS tube, and serves as the input end of the Schmitt trigger circuit; the source of the second PMOS tube is connected to the power supply, and the drain of the second PMOS tube is connected to the source of the third PMOS tube and the source of the fourth PMOS tube; the drain of the third PMOS tube is connected to the drain of the third NMOS tube, the gate of the fourth PMOS tube, and the gate of the fifth NMOS tube, and serves as the output end of the Schmitt trigger circuit; the drain of the fourth PMOS tube is grounded; the source of the third NMOS tube is connected to the source of the fifth NMOS tube and the drain of the fourth NMOS tube; the drain of the fifth NMOS tube is connected to the power supply; and the source of the fourth NMOS tube is connected to the ground.
5. A high-speed clock duty cycle stabilization circuit as claimed in claim 1, characterized in that: The current mirror module includes two NMOS tubes; The gates of the two NMOS tubes are connected to each other and the sources are grounded; the drain of one NMOS tube is connected to the current source, and the drain of the other NMOS tube serves as the output end of the current mirror module and is connected to the output end of the voltage-controlled delay circuit.
6. A high-speed clock duty cycle stable output method, characterized in that: The following steps are involved: The input end of the first inverter receives the clock signal CLKIN, and the input end of the second inverter receives the feedback signal of the Schmitt trigger circuit. The rising edges of the two input signals are detected through the second NAND gate and the third NAND gate, and the phase difference between the two input signals is represented by the pulse width of the output signal CLKOUT. During the adjustment process, the rising edge of the output signal CLKOUT is always aligned with the rising edge of the clock signal CLKIN, and the duty cycle of the output signal is adjusted only by changing the triggering time of its falling edge.
7. A high-speed clock duty cycle stable output method according to claim 6, characterized in that: In the adjustment process, the rising edge of the output signal CLKOUT is always aligned with the rising edge of the clock signal CLKIN, and the duty cycle of the output signal is adjusted only by changing the trigger time of the falling edge thereof, including the following steps: If the duty cycle of the output signal CLKOUT is less than 50%, the integrator output voltage A increases, causing the gate control voltage of the second NMOS transistor in the voltage-controlled delay circuit to decrease, and the discharge current of the first capacitor through the first NMOS transistor and the second NMOS transistor to decrease, and the discharge time is prolonged. The rising edge of the feedback signal after passing through the Schmitt trigger circuit is delayed, and the duty cycle of the output signal CLKOUT increases until it reaches 50%; If the duty cycle of the output signal CLKOUT is greater than 50%, the integrator output voltage A decreases, causing the control voltage of the voltage-controlled delay circuit to increase, and the discharge current of the first capacitor through the first NMOS tube and the second NMOS tube increases, the discharge time is shortened, and the rising edge of the feedback signal passing through the Schmitt trigger circuit is advanced, and the duty cycle of the output signal CLKOUT decreases until it reaches 50%.