Continuous progressive analog-to-digital converter and operation method thereof

Abstract

The invention provides a successive progressive analog-to-digital converter. The successive progressive analog-to-digital converter comprises an array of digital-to-analog converters (DAC) receiving an input signal and successive progressive (SAR) logic. The DAC array comprises three DACs and three comparators. The three DACs sample input signals. The three comparators are respectively coupled in series with the three DACs to generate comparison results. The SAR logic is coupled to the DAC array, and generates the nth bit of the conversion result according to the comparison result in the nth comparison stage. In the nth comparison stage, the SAR logic selects the first comparator according to the comparison result of the (n-1) th comparison stage, and compares the sampling result of the first DAC with the voltage level corresponding to the first (n-1) bits of the conversion result to generate a comparison result, and adjusting the sampling results of the second DAC and the third DAC corresponding to the second comparator and the third comparator to the voltage level corresponding to the nth bit of the conversion result being 0 and 1, wherein n is a positive integer greater than 1.

Description

Technical Field

[0001] The present invention relates to a continuous progressive analog-to-digital converter and an operating method thereof, and in particular to a continuous progressive analog-to-digital converter using three digital-to-analog converters for sampling and an operating method thereof. Background Art

[0002] Successive Approximation Register (SAR) analog-to-digital converter (ADC) can convert analog signals into multi-bit digital signals through a gradual approximation method. Due to its high resolution, it is widely used in various fields.

[0003] However, after the comparator in the SAR ADC completes a comparison and determines one bit of the digital signal, it must wait for the SAR ADC's digital-to-analog converter (DAC) to switch circuit structures before it can perform the next comparison and determine the next bit. In other words, the more bits of the digital signal that need to be converted, the longer it takes to switch the DAC circuit structure. Therefore, for high-resolution SAR ADCs, the DAC switching time will cause the SAR ADC's conversion efficiency to decrease. How to improve the impact of DAC switching on the SAR ADC's conversion efficiency has become a topic in this field. Summary of the Invention

[0004] The present invention provides a continuous incremental analog-to-digital converter (SAR ADC) for receiving an input signal, comprising a digital-to-analog converter (DAC) array and a continuous incremental logic circuit. The DAC array is configured to receive the input signal and includes three DACs and three comparators. The three DACs are configured to sample the input signal. The three comparators are coupled in series to the three DACs, each configured to generate a comparison result. The continuous incremental logic circuit is coupled to the DAC array and configured to generate the nth bit of a conversion result based on the comparison result in an nth comparison phase. In the nth comparison phase, the continuous incremental logic circuit is configured to select a first comparator of the three comparators to compare the sampling result of the first DAC of the three DACs with the voltage level corresponding to the first (n-1) bits of the conversion result based on the comparison result in the (n-1)th comparison phase to generate the comparison result. The continuous incremental logic circuit is also configured to adjust the sampling results of the second DAC and the third DAC of the three DACs corresponding to the second comparator and the third comparator of the three comparators to the voltage level corresponding to the nth bit of the conversion result being 0 and 1, respectively, where n is a positive integer greater than 1.

[0005] The present invention provides an operating method for operating a successive incremental analog-to-digital converter (SAR ADC), wherein the SAR ADC is configured to receive an input signal and includes a digital-to-analog converter (DAC) array and a successive incremental logic circuit. The operating method comprises: (a) in an nth comparison phase, the successive incremental logic circuit selects a first comparator of three comparators in the DAC array to compare a sampling result of a first DAC of three DACs in the DAC array with a voltage level corresponding to the first (n-1) bits of a conversion result to generate a comparison result based on a comparison result in an (n-1)th comparison phase, and adjusts the second sampling results of the second DAC and the third DAC of the three DACs corresponding to the second comparator and the third comparator of the three comparators to voltage levels corresponding to a 0 and a 1, respectively, corresponding to the nth bit of the conversion result; (b) the first comparator compares the input signal with the voltage levels corresponding to the first (n-1) bits of the conversion result to generate a comparison result; (c) the successive incremental logic circuit generates the nth bit of the conversion result based on the comparison result; and (d) repeatedly performing steps (a) to (c). The DAC array is coupled between the input signal and the sequential progressive logic circuit, and the three comparators are respectively coupled in series to the three DACs, wherein n is a positive integer greater than 1.

[0006] The SAR ADC and its operating method of the present invention can save the waiting time for switching the internal DAC in different comparison phases of the SAR ADC, thereby improving the efficiency of the SAR ADC in converting analog signals into digital signals while maintaining resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0008] Figure 1 is a circuit diagram of a SAR ADC according to some embodiments of the present invention;

[0009] Figure 2A is a circuit diagram of a SAR ADC in a time period P1 according to some embodiments of the present invention;

[0010] Figure 2B is a circuit diagram of a SAR ADC in period P2 according to some embodiments of the present invention;

[0011] Figure 2C is a circuit diagram of a SAR ADC in period P3 according to some embodiments of the present invention;

[0012] Figure 2D is a circuit diagram of a SAR ADC in period P4 according to some embodiments of the present invention;

[0013] Figure 2E is a circuit diagram of a SAR ADC in a time period P5 according to some embodiments of the present invention;

[0014] Figure 3 A timing diagram of a sampling signal and a channel selection signal according to some embodiments of the present invention; and

[0015] Figure 4 FIG. 4 is a flow chart of an operating method of a SAR ADC according to some embodiments of the present invention.

[0016] Description of reference numerals:

[0017] Vi: Input signal 100: SAR ADC

[0018] Vin, Vip: Sub-input signal 110: Digital-to-analog converter (DAC) array

[0019] Vref: reference voltage 113a, 113b, 113c: comparators

[0020] 112a, 112b, 112c: DAC 111a, 111b, 111c: Sampling switch circuit

[0021] 400: Operation method 410, 420, 430, 440: Steps 450, 460, 470: Steps P1, P2, P3, P4, P5: Time period

[0022] GND: Ground voltage C1p, C2p, C3p, C4p, C5p: First capacitor switch circuit SAM: sampling signal C1n, C2n, C3n, C4n, C5n: second capacitor switching circuit 120: Continuous progressive logic circuit S1p, S2p, S3p, S4p: control signal

[0023] RE: comparison result S1n, S2n, S3n, S4n: control signal

[0024] OUT: conversion result clk1, clk2, clk3: channel selection signal DETAILED DESCRIPTION

[0025] The following will illustrate embodiments of the present invention with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.

[0026] In the present invention, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate the coordinated operation or interaction between two or more elements. Unless the context specifically limits the articles, "one" and "the" may refer to a single or multiple elements. It will be further understood that the words "include", "including", "have" and similar words used herein indicate the features, regions, integers, steps, operations, elements and / or components described therein, but do not exclude the one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof described therein or in addition thereto.

[0027] Figure 1 FIG2 is a circuit diagram of a SAR ADC 100 according to some embodiments of the present invention. In some embodiments, the SAR ADC 100 is configured to receive an input signal Vi and a reference voltage Vref, and includes a DAC array 110 and a sequential logic circuit 120 for generating a conversion result OUT based on the voltage level of the input signal Vi.

[0028] In some embodiments, the conversion result OUT is an array including multiple bits. For example, the conversion result OUT may be a binary array including 4 bits.

[0029] In some embodiments, the SAR ADC 100 operates in a top-plate sampling mode. For further information on the configuration and operation of the top-plate sampling mode, please refer to the following paragraphs and Figure 1 、 2A ~2E.

[0030] In some embodiments, a DAC array 110 is configured to receive an input signal Vi and includes sampling switch circuits 111a, 111b, and 111c, DACs 112a, 112b, and 112c, and comparators 113a, 113b, and 113c. The sampling switch circuit 111a, DAC 112a, and comparator 113a are connected in parallel with the sampling switch circuit 111b, DAC 112b, and comparator 113b, and are also connected in parallel with the sampling switch circuit 111c, DAC 112c, and comparator 113c.

[0031] Sampling switch circuit 111a is coupled between input signal Vi and DAC 112a, sampling switch circuit 111b is coupled between input signal Vi and DAC 112b, and sampling switch circuit 111c is coupled between input signal Vi and DAC 112c. In some embodiments, sampling switch circuits 111a, 111b, and 111c are configured to receive a sampling signal S AM and be simultaneously turned on or off based on the sampling signal S AM, thereby enabling DACs 112a, 112b, and 112c to sample input signal Vi.

[0032] DAC 112a is coupled between sampling switch circuit 111a and comparator 113a, DAC 112b is coupled between sampling switch circuit 111b and comparator 113b, and DAC 112c is coupled between sampling switch circuit 111c and comparator 113c. In some embodiments, DACs 112a, 112b, and 112c each include first capacitive switch circuits C1p-C5p. The first capacitive switch circuits C1p-C5p each have one terminal coupled to an input terminal of the corresponding comparator and another terminal for receiving a reference voltage Vref or ground voltage GND. The first capacitive switch circuits C1p-C5p are coupled in parallel with one another. For example, the first capacitive switch circuits C1p-C5p of DAC 112a are coupled to the non-inverting input terminal of comparator 113a, the first capacitive switch circuits C1p-C5p of DAC 112b are coupled to the non-inverting input terminal of comparator 113b, and so on.

[0033] In some embodiments, the DACs 112a, 112b, and 112c are configured to receive control signals S1p-S4p and control the first capacitive switch circuits C1p-C4p to receive the ground voltage GND or the reference voltage Vref according to the control signals S1p-S4p, thereby adjusting the sampling results of the DACs 112a, 112b, and 112c.

[0034] In some embodiments, DACs 112a, 112b, and 112c each further include second capacitive switching circuits C1n-C5n. The second capacitive switching circuits C1n-C5n each have one terminal coupled to the other input terminal of the corresponding comparator and another terminal receiving a reference voltage Vref or a ground voltage GND. The second capacitive switching circuits C1n-C5n are coupled in parallel to one another. For example, the second capacitive switching circuits C1n-C5n of DAC 112a are coupled to the inverting input terminal of comparator 113a, the second capacitive switching circuits C1n-C5n of DAC 112b are coupled to the inverting input terminal of comparator 113b, and so on.

[0035] In this embodiment, DACs 112a, 112b, and 112c are further configured to receive control signals S1n-S4n and, based on the control signals S1n-S4n, control the second capacitive switching circuits C1n-C4n to receive the ground voltage GND or the reference voltage Vref, thereby adjusting the sampling results of DACs 112a, 112b, and 112c. Furthermore, the input signal Vi includes sub-input signals Vip and Vin, which are differential signals, i.e., sub-input signals Vip and Vin are inverted. Sub-input signal Vip is coupled to the first capacitive switching circuits C1p-C5p of each of DACs 112a, 112b, and 112c via sampling switch circuits 111a, 111b, and 111c. Sub-input signal Vin is coupled to the second capacitive switching circuits C1n-C5n of each of DACs 112a, 112b, and 112c via sampling switch circuits 111a, 111b, and 111c.

[0036] By using the first capacitor switch circuit C1p-C5p and the second capacitor switch circuit C1n-C5n, the SAR ADC 100 can sample and compare the differential input signal Vi. Therefore, compared with the conventional SAR ADC that only uses one set of capacitor switch circuits and cannot sample differential signals, Figure 1 The SAR ADC 100 can obtain a more accurate conversion result OUT.

[0037] In some embodiments, the capacitance values ​​of the first capacitive switching circuits C1p-C4p form a geometric progression, the capacitance values ​​of the second capacitive switching circuits C1n-C4n also form a geometric progression, the capacitance value of the first capacitive switching circuit C5p is equal to the capacitance value of the first capacitive switching circuit C4p, and the capacitance value of the second capacitive switching circuit C5n is equal to the capacitance value of the second capacitive switching circuit C4n. For example, the capacitance values ​​of the first capacitive switching circuits C1p-C5p can be 8 farads, 4 farads, 2 farads, 1 farad, and 1 farad, respectively.

[0038] For example, when the first capacitor switch circuits C1p-C4p all receive the ground voltage GND and the second capacitor switch circuits C1n-C4n all receive the reference voltage Vref, the sampling result of the DAC represents the conversion result OUT as a binary array of "1111." When the first capacitor switch circuits C1p-C4p all receive the reference voltage Vref and the second capacitor switch circuits C1n-C4n all receive the ground voltage GND, the sampling result of the DAC represents the conversion result OUT as a binary array of "0000." In some embodiments, larger numbers in the array of the conversion result OUT represent larger voltage levels corresponding to the DAC sampling result.

[0039] Comparator 113a is coupled between DAC 112a and the sequential incremental logic circuit 120, comparator 113b is coupled between DAC 112b and the sequential incremental logic circuit 120, and comparator 113c is coupled between DAC 112c and the sequential incremental logic circuit 120. Comparators 113a, 113b, and 113c are respectively configured to receive channel selection signals clk1-clk3 from the sequential incremental logic circuit 120. The channel selection signals clk1-clk3 are configured to enable one of the comparators 113a, 113b, and 113c (e.g., comparator 113a) to compare the sampling result of the corresponding DAC (e.g., DAC 112a), and to disable (i.e., not perform a comparison operation) the other two of the comparators 113a, 113b, and 113c, so that the enabled comparator (e.g., comparator 113a) generates a comparison result RE.

[0040] The sequential progressive logic circuit 120 is coupled to the DAC array 110 and is configured to generate control signals S1p-S4p and S1n-S4n based on the comparison result RE. The control signals S1p-S4p are transmitted to the switches coupled to each set of first capacitor switch circuits C1p-C4p, and the control signals S1n-S4n are transmitted to the switches coupled to each set of second capacitor switch circuits C1n-C4n, thereby adjusting the sampling results of the DACs 112a, 112b, and 112c. The sequential progressive logic circuit 120 is further configured to generate channel selection signals clk1-clk3 to determine which comparator to enable, and to generate a conversion result OUT based on the comparison result RE output by the enabled comparator.

[0041] For details on the operation of the SAR ADC 100, please refer to Figures 2A to 2E and Figure 3 . Figures 2A to 2E The SAR ADC 100 according to some embodiments is respectively Figure 3 Circuit diagram of time period P1 to P5. Figure 3 1 is a timing diagram of the sampling signal SAM and the channel selection signals clk1 - clk3 according to some embodiments, including a period P1 representing a sampling phase and periods P2 - P5 representing different comparison phases.

[0042] First, please refer to Figure 2A , in period P1 (shown in Figure 3), the SAR ADC 100 enters the sampling phase and begins sampling the input signal Vi. At this time, the sampling signal SAM is switched to the enable level (i.e., logic high), so the sampling switch circuits 111a, 111b, and 111c are turned on. On the other hand, the channel selection signals clk1-clk3 are at the disable level (i.e., logic high), so the comparators 113a, 113b, and 113c do not perform comparisons. In addition, the first capacitor switch circuits C1p-C4p and the second capacitor switch circuits C1n-C4n are switched to receive the reference voltage Vref to complete the initialization of the DACs 112a, 112b, and 112c.

[0043] Please refer to Figure 2B and Figure 3 In the period P2, the SAR ADC 100 enters the first comparison phase and starts to compare the input signal Vi.

[0044] by Figure 2B and Figure 3 For example, since the period P2 is the first comparison stage, the sequential progressive logic circuit 120 randomly selects (or fixedly selects) the comparator 113a for comparison, and thus changes the channel selection signal clk1 to the enable level.

[0045] In addition, the continuous progressive logic circuit 120 adjusts the circuit structures of the DACs 112b and 112c corresponding to the unselected comparators 113b and 113c through the control signals S1p-S4p and S1n-S4n, so that the sampling results of the DACs 112b and 112c correspond to the voltage levels corresponding to the two cases where the first bit (i.e., the Most Significant Bit, MSB) of the conversion result OUT is 0 and 1, respectively. Figure 2B , the second capacitor switch circuit C1n of DAC 112b is switched to receive the ground voltage GND, so the sampling result of DAC 112b corresponds to the voltage level corresponding to the first bit of the conversion result OUT being 0; the first capacitor switch circuit C1p of DAC 112c is switched to receive the ground voltage GND, so the sampling result of DAC 112c corresponds to the voltage level corresponding to the first bit of the conversion result OUT being 1.

[0046] In the first comparison phase, comparator 113a compares the sampling result of DAC 112a with 0 to determine whether the sampling result of DAC 112a is greater than 0 or less than 0. In this example, since the voltage level of input signal Vi is less than 0, the sequential incremental logic circuit 120 records the first bit of conversion result OUT as 0 based on the comparison result RE transmitted by comparator 113a. Next, since the first bit of conversion result OUT is recorded as 0, corresponding to the sampling result of DAC 112b (i.e., the voltage level corresponding to the first bit of conversion result OUT being "0"), the sequential incremental logic circuit 120 selects the comparator 113b corresponding to DAC 112b as the comparator for the next comparison, adjusts the levels of channel selection signals clk1-clk3, and then adjusts control signals S1p-S4p and S1n-S4n to synchronously adjust the sampling results of DACs 112a and 112c to the voltage level corresponding to the first bit of conversion result OUT being 0, thus completing the first comparison.

[0047] In other examples not shown, when the voltage level of the input signal Vi sampled by the DAC 112a (i.e., the sampling result of the DAC 112a) is greater than 0, the sequential progressive logic circuit 120 records the first bit of the conversion result OUT as 1 based on the comparison result RE transmitted by the comparator 113a. Since the first bit of the conversion result OUT is recorded as 1, corresponding to the sampling result of the DAC 112c (i.e., corresponding to the voltage level corresponding to the first bit of the conversion result OUT being "1"), the sequential progressive logic circuit 120 selects the comparator 113c corresponding to the DAC 112c as the comparator for the next comparison, and synchronously adjusts the sampling results of the DACs 112a and 112b to the voltage level corresponding to the first bit of the conversion result OUT being 1, thereby completing the first comparison.

[0048] Next, please refer to Figure 2C and Figure 3 In the period P3, the SAR ADC 100 enters the second comparison phase and continues to compare the input signal Vi.

[0049] by Figure 2C and Figure 3 For example, at the end of the period P2, the sequential incremental logic circuit 120 selects the comparator 113b as the comparator for the next comparison, so the channel selection signal clk2 is changed to the enable level and the channel selection signal clk1 is changed to the disable level.

[0050] In addition, the continuous progressive logic circuit 120 adjusts the circuit structures of the DACs 112a and 112c corresponding to the unselected comparators 113a and 113c through the control signals S1p-S4p and S1n-S4n, so that the sampling results of the DACs 112a and 112c correspond to the voltage levels corresponding to the two cases where the first two bits of the conversion result OUT are "00" and "01", respectively. Figure 2C , the second capacitor switch circuit C2n of DAC 112a is switched to receive the ground voltage GND, so the sampling result of DAC 112a corresponds to the voltage level corresponding to the first two bits of the conversion result OUT being "00"; the first capacitor switch circuit C2p of DAC 112c is switched to receive the ground voltage GND, so the sampling result of DAC 112c corresponds to the voltage level corresponding to the first two bits of the conversion result OUT being "01".

[0051] Next, comparator 113b compares the sampling result of DAC 112b with the voltage level corresponding to the previous bit of conversion result OUT being "0." In this example, because the voltage level of input signal Vi is lower than the voltage level corresponding to the previous bit of conversion result OUT being "0," sequential logic circuit 120 records the second bit of conversion result OUT as 0 based on comparison result RE transmitted by comparator 113b. Next, since the second bit of the recorded conversion result OUT is 0, which corresponds to the sampling result of DAC 112a (i.e., the voltage level corresponding to the first two bits of the conversion result OUT being "00"), the sequential logic circuit 120 selects the comparator 113a corresponding to DAC 112a as the comparator for the next comparison, adjusts the levels of the channel selection signals clk1-clk3, and further adjusts the control signals S1p-S4p and S1n-S4n to synchronously adjust the sampling results of DACs 112b and 112c to the voltage level corresponding to the first two bits of the conversion result OUT being "00", thereby completing the second comparison.

[0052] In other examples not shown, when the sampling result of the DAC 112 b is greater than the voltage level corresponding to the previous bit of the conversion result OUT being “0”, the sequential logic circuit 120 records the second bit of the conversion result OUT as being “1” and selects the comparator 113 c corresponding to the DAC 112 c as the comparator for the next comparison. Detailed description is omitted here.

[0053] Next, please refer to Figure 2D and Figure 3 In period P4, the SAR ADC 100 enters the third comparison phase and continues to compare the input signal Vi.

[0054] by Figure 2D and Figure 3 For example, at the end of the period P3, the sequential incremental logic circuit 120 selects the comparator 113a as the comparator for the next comparison, so the channel selection signal clk1 is changed to the enable level and the channel selection signal clk2 is changed to the disable level.

[0055] In addition, the continuous progressive logic circuit 120 adjusts the circuit structures of the DACs 112b and 112c corresponding to the unselected comparators 113b and 113c through the control signals S1p-S4p and S1n-S4n, so that the sampling results of the DACs 112b and 112c correspond to the voltage levels corresponding to the two cases where the first three bits of the conversion result OUT are "000" and "001", respectively. Figure 2D , the second capacitor switch circuit C3n of DAC 112b is switched to receive the ground voltage GND, so the sampling result of DAC 112b corresponds to the voltage level corresponding to the first three bits of the conversion result OUT being "000"; the first capacitor switch circuit C3p of DAC 112c is switched to receive the ground voltage GND, so the sampling result of DAC 112c corresponds to the voltage level corresponding to the first three bits of the conversion result OUT being "001".

[0056] Next, comparator 113a compares the sampling result of DAC 112a with the voltage level corresponding to the first two bits of conversion result OUT being "00." In this example, because the voltage level of input signal Vi is greater than the voltage level corresponding to the first two bits of conversion result OUT being "00," sequential incremental logic circuit 120 records the third bit of conversion result OUT as 1 based on comparison result RE transmitted by comparator 113a. Next, because the third bit of conversion result OUT being 1 corresponds to the sampling result of DAC 112c, sequential incremental logic circuit 120 selects comparator 113c corresponding to DAC 112c as the next comparator for comparison. It then adjusts the levels of channel select signals clk1-clk3, and further adjusts control signals S1p-S4p and S1n-S4n, synchronously adjusting the sampling results of DACs 112a and 112b to the voltage level corresponding to the first three bits of conversion result OUT being "001," completing the third comparison.

[0057] In other examples not shown, when the sampling result of the DAC 112 a is lower than the voltage level corresponding to the first two bits of the conversion result OUT being “00”, the sequential progressive logic circuit 120 records that the third bit of the conversion result OUT is 0 and selects the comparator 113 b corresponding to the DAC 112 b as the comparator for the next comparison. Detailed description is omitted here.

[0058] Next, please refer to Figure 2E and Figure 3 In the period P5, the SAR ADC 100 enters the fourth comparison phase and continues to compare the input signal Vi.

[0059] by Figure 2E and Figure 3 For example, at the end of the period P4, the sequential incremental logic circuit 120 selects the comparator 113c as the comparator for the next comparison, so the channel selection signal clk3 is changed to the enable level and the channel selection signal clk1 is changed to the disable level.

[0060] In addition, the continuous progressive logic circuit 120 adjusts the circuit structures of the DACs 112a and 112b corresponding to the unselected comparators 113a and 113b through the control signals S1p-S4p and S1n-S4n, so that the sampling results of the DACs 112a and 112b correspond to the voltage levels corresponding to the four bits of the conversion result OUT being "0010" and "0011", respectively. Figure 2E , the second capacitor switch circuit C4n of the DAC 112a is switched to receive the ground voltage GND, so the sampling result of the DAC 112a corresponds to the voltage level corresponding to the four bits of the conversion result OUT being "0010"; the first capacitor switch circuit C4p of the DAC 112b is switched to receive the ground voltage GND, so the sampling result of the DAC 112b corresponds to the voltage level corresponding to the four bits of the conversion result OUT being "0011".

[0061] Next, the comparator 113 c compares the sampling result of the DAC 112 c with the voltage level corresponding to the first three bits of the conversion result OUT being "001." In this example, because the voltage level of the input signal Vi is greater than the voltage level corresponding to the first three bits of the conversion result OUT being "001," the sequential logic circuit 120 records the fourth bit of the conversion result OUT as 1 based on the comparison result RE transmitted by the comparator 113 c.

[0062] Finally, through the four comparison results RE generated in the four comparison stages, the SAR ADC 100 can determine that the four bits in the conversion result OUT are "0011" according to the four comparison results RE, and then convert the analog signal input signal Vi into a digital signal (i.e., array) conversion result OUT.

[0063] In summary, in the nth comparison phase (n is a positive integer), the continuous progressive logic circuit 120 selects a comparator based on the comparison result RE of the (n-1)th comparison phase (a comparator is randomly (or fixedly) selected in the first comparison phase). It then changes the channel select signal transmitted to the selected comparator to an enable level, enabling comparison with that comparator. Next, the continuous progressive logic circuit 120 adjusts the circuit structures of the DACs corresponding to the other two unselected comparators via control signals S1p-S4p and S1n-S4n, so that the sampling results of these two DACs correspond to the voltage levels corresponding to the cases where the nth bit of the conversion result OUT is 0 and 1, respectively. Finally, the selected comparator compares the sampling result of its corresponding DAC with the voltage levels corresponding to the first (n-1) bits of the conversion result OUT and generates a corresponding comparison result RE. Based on the comparison result RE, the continuous progressive logic circuit 120 synchronizes the circuit structures of the three DACs using control signals and adjusts the comparator used for comparison in the next comparison phase using the channel select signal.

[0064] Furthermore, in each comparison phase, before the comparator performs comparison, the sequential progressive logic circuit 120 has already adjusted the sampling results of the unselected DACs to voltage levels corresponding to the two cases where the bits corresponding to the current comparison phase are 0 and 1. Therefore, after the comparison is completed, the SAR DAC 100 can directly switch channels to perform the next comparison, thereby saving the time required to wait for the DAC to switch circuit structures.

[0065] It should be noted that the number of first and second capacitor switch circuits in DACs 112a, 112b, and 112c of the present invention is merely exemplary and not intended to limit the present invention. Any other number is within the scope of the present invention. In some embodiments, DACs 112a, 112b, and 112c include fewer than five first and second capacitor switch circuits to achieve faster conversion speeds. In some embodiments, DACs 112a, 112b, and 112c include more than five first and second capacitor switch circuits to achieve higher resolution.

[0066] Figure 4FIG. 4 is a flow chart of a method 400 of operating the SAR ADC 100 according to some embodiments. In some embodiments, the method 400 includes steps 410 , 420 , 430 , 440 , 450 , 460 , and 470 .

[0067] In step 410, the SAR ADC 100 enters a sampling phase. The sampling signal SAM is switched to an enable level to turn on the sampling switch circuits 111a, 111b, and 111c. The first capacitive switch circuits C1p-C4p and the second capacitive switch circuits C1n-C4n are switched to receive the reference voltage Vref, thereby completing the initialization of the DACs 112a, 112b, and 112c.

[0068] In step 420 , the sequential logic circuit 120 randomly selects a comparator for comparison and adjusts the sampling results of the DACs corresponding to the other two unselected comparators to the voltage levels corresponding to the first bits of the conversion result OUT being 0 and 1.

[0069] In step 430, the selected comparator performs the nth comparison, comparing the input signal Vi with the voltage levels corresponding to the first (n-1) characters of the conversion result OUT, where n is a positive integer. If the voltage level of the input signal Vi is greater than or equal to the voltage level corresponding to the first (n-1) characters of the conversion result OUT, step 440 is executed. If the voltage level of the input signal Vi is less than the voltage level corresponding to the first (n-1) characters of the conversion result OUT, step 450 is executed.

[0070] In step 440, the selected comparator generates a comparison result RE to the sequential logic circuit 120. The sequential logic circuit 120 selects the comparator whose DAC sampling result corresponds to the n-th bit of the conversion result OUT being 1 as the comparator to be used for the next comparison (i.e., the (n+1)th comparison), and adjusts the DAC sampling results corresponding to the remaining two comparators to the voltage levels corresponding to the (n+1)-th bits of the conversion result OUT being 0 and 1, respectively.

[0071] In step 450, the selected comparator generates a comparison result RE to the sequential logic circuit 120. The sequential logic circuit 120 selects the comparator whose DAC sampling result corresponds to the n-th bit of the conversion result OUT being 0 as the comparator to be used for the next comparison (i.e., the (n+1)th comparison), and adjusts the DAC sampling results corresponding to the remaining two comparators to the voltage levels corresponding to the (n+1)-th bits of the conversion result OUT being 0 and 1, respectively.

[0072] In step 460, the sequential logic circuit 120 determines whether it has received the same number of comparison results RE as the first capacitor switch circuit in the DAC (i.e., it has completed the determination of all bits of the conversion result OUT). If the DAC array 110 has received the same number of comparison results RE as the first capacitor switch circuit in the DAC, step 470 is executed. If the DAC array 110 has not received the same number of comparison results RE as the first capacitor switch circuit in the DAC, step 430 is repeated.

[0073] In step 470 , the sequential logic circuit 120 generates a conversion result OUT according to the received comparison results RE.

[0074] It should be noted that the number and order of the steps in the operating method 400 of the present invention are only examples and are not intended to limit the present invention. Other numbers and orders of steps are within the scope of protection of the present invention. In some embodiments, step 460 can be omitted.

[0075] The SAR ADC 100 and its operating method 400 of the present invention can utilize multiple DACs and multiple comparators within the SAR ADC 100 to perform comparisons in rotation, thereby saving time waiting for the DAC's internal circuit structure to switch. This improves the efficiency of the SAR ADC 100 in converting analog signals into digital signals while maintaining its resolution.

[0076] The above are only preferred embodiments of the present invention. Without departing from the scope or spirit of the present invention, the structure of the present invention can be modified and equivalently varied. In summary, all modifications and equivalent variations made to the present invention within the scope of protection of the claims of the present invention are within the scope of the present invention.

Claims

1. A continuous progressive analog-to-digital converter for receiving an input signal, characterized in that: include: A digital-to-analog converter array, for receiving the input signal, comprising: three digital-to-analog converters for sampling the input signal; and three comparators, respectively coupled in series to the three digital-to-analog converters, and each used to generate a comparison result; and a sequential progressive logic circuit coupled to the digital-to-analog converter array and configured to generate an nth bit of a conversion result according to the comparison result in an nth comparison stage, Wherein, in the nth comparison stage, the continuous progressive logic circuit is used to select a first comparator of the three comparators to compare the sampling result of a first digital-to-analog converter of the three digital-to-analog converters with the voltage level corresponding to the first (n-1) bits of the conversion result according to the comparison result in the (n-1)th comparison stage to generate a comparison result, and the continuous progressive logic circuit is used to adjust the two sampling results of a second digital-to-analog converter and a third digital-to-analog converter of the three digital-to-analog converters corresponding to a second comparator and a third comparator of the three comparators to the voltage level corresponding to the nth bit of the conversion result being 0 and the voltage level corresponding to being 1, respectively, wherein n is a positive integer greater than 1.

2. The continuous progressive analog-to-digital converter according to claim 1, characterized in that: The digital-to-analog converter array also includes three sampling switch circuits, which are respectively coupled between the input signal and the three digital-to-analog converters, and are used to be turned on according to a sampling signal in a sampling phase so that the digital-to-analog converter array samples the input signal, and to be turned off according to the sampling signal in the multiple comparison phases.

3. The continuous incremental analog-to-digital converter according to claim 1, characterized in that: The three digital-to-analog converters each include a plurality of first capacitor switching circuits. The plurality of first capacitor switching circuits of each digital-to-analog converter are coupled in parallel to each other and to an input terminal of the corresponding comparator, and are used to couple to a reference voltage or a ground voltage according to the plurality of control signals.

4. The continuous incremental analog-to-digital converter according to claim 3, characterized in that: Each of the three digital-to-analog converters also includes a plurality of second capacitor switching circuits, the number of the plurality of second capacitor switching circuits being equal to the number of the plurality of first capacitor switching circuits, the plurality of second capacitor switching circuits of each digital-to-analog converter being coupled in parallel to each other and coupled to another input terminal of the corresponding comparator, for being coupled to the reference voltage or the ground voltage respectively according to the plurality of control signals.

5. The continuous incremental analog-to-digital converter according to claim 3, characterized in that: The number of the comparison stages is equal to the number of the first capacitive switch circuits of each digital-to-analog converter, and is also equal to the number of the comparison results.

6. The continuous incremental analog-to-digital converter according to claim 1, characterized in that: When the input signal is greater than or equal to the voltage level corresponding to the first (n-1) bits of the conversion result, the continuous progressive logic circuit selects the third comparator corresponding to the third digital-to-analog converter to perform comparison in an (n+1)th comparison stage, and synchronously adjusts the two sampling results of the first digital-to-analog converter and the second digital-to-analog converter to the voltage level corresponding to the nth bit of the conversion result being 1.

7. The continuous incremental analog-to-digital converter according to claim 6, characterized in that: When the input signal is less than the voltage level corresponding to the first (n-1) bits of the conversion result, the continuous progressive logic circuit selects the second comparator corresponding to the second digital-to-analog converter to perform comparison in an (n+1)th comparison stage, and synchronously adjusts the two sampling results of the first digital-to-analog converter and the third digital-to-analog converter to the voltage level corresponding to the nth bit of the conversion result being 0.

8. The continuous incremental analog-to-digital converter according to claim 1, characterized in that: The conversion result is an array including a plurality of bits, and each comparison result corresponds to each bit.

9. A method for operating a continuous-time analog-to-digital converter, characterized in that: The continuous progressive analog-to-digital converter is used to receive an input signal and includes a digital-to-analog converter array and a continuous progressive logic circuit. The operation method includes: (a) in an n-th comparison stage, the continuous progressive logic circuit selects a first comparator of the three comparators of the digital-to-analog converter array to compare the sampling result of a first digital-to-analog converter of the three digital-to-analog converters of the digital-to-analog converter array with the voltage level corresponding to the first (n-1) bits of a conversion result to generate a comparison result, and adjusts the two sampling results of a second digital-to-analog converter and a third digital-to-analog converter of the three digital-to-analog converters corresponding to a second comparator and a third comparator of the three comparators to the voltage level corresponding to the n-th bit of the conversion result being 0 and the voltage level corresponding to being 1, respectively; (b) the first comparator compares the input signal with the voltage levels corresponding to the first (n-1) bits of the conversion result to generate the comparison result; (c) the sequential progressive logic circuit generates the nth bit of the conversion result according to the comparison result; and (d) Repeat steps (a) to (c), The digital-to-analog converter array is coupled between the input signal and the sequential progressive logic circuit, and the three comparators are respectively coupled in series to the three digital-to-analog converters, wherein n is a positive integer greater than 1.

10. The operating method according to claim 9, characterized in that: Also includes: (e) in a sampling phase, turning on three sampling switch circuits of the digital-to-analog converter array according to a sampling signal so that the digital-to-analog converter array samples the input signal, and turning off the three sampling switch circuits according to the sampling signal in the comparison phase, The three sampling switch circuits are respectively coupled between the input signal and the three digital-to-analog converters.

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