Quantum bit assembly, preparation method, quantum chip and chip preparation system

Abstract

The invention relates to a quantum bit assembly, a preparation method, a quantum chip and a chip preparation system, and relates to the technical field of micro-nano processing. The quantum bit component comprises a bottom layer circuit and a quantum bit, the surface of the bottom circuit is provided with a nitride passivation layer. The quantum bit assembly preparation method comprises the following steps: preparing a bottom film of a quantum bit assembly on a substrate; preparing an underlying circuit based on the underlying film, wherein the surface of the underlying circuit is provided with a nitride passivation layer; and preparing a quantum bit connected with the bottom layer circuit on the substrate to obtain the quantum bit assembly. According to the scheme, the nitride passivation layer can be prepared on the surface of the bottom layer circuit, oxidation of the film surface can be effectively avoided, generation of TLS loss is reduced, the coherence time of the quantum chip is prolonged, and then the method is used for preparing the superconducting quantum chip with long coherence and back coherence.

Description

Technical Field

[0001] The present application relates to the field of micro-nano processing technology, and in particular to a quantum bit component, a preparation method, a quantum chip, and a chip preparation system. Background Art

[0002] How to prolong the coherence of a quantum system is an important issue for quantum computers. The impact of superconducting materials on coherence is mainly the TLS loss of the material itself, and the TLS loss mainly comes from the oxide layer on the surface of the material.

[0003] In related technologies, the commonly used aluminum film can be replaced with a niobium or tantalum film with a thinner oxide layer, or the oxide layer can be removed with hydrofluoric acid and then placed in a refrigerator for vacuum cooling as soon as possible to reduce TLS loss.

[0004] However, after replacing the aluminum film with a niobium film or a tantalum film, the coherence time can be greatly improved, but the niobium film or the tantalum film still has an oxide layer; using hydrofluoric acid to clean the oxide layer and then cooling it down as quickly as possible requires strict experimental conditions, and oxidation cannot be avoided. Summary of the invention

[0005] The embodiments of the present application provide a quantum bit component, a preparation method, a quantum chip, and a chip preparation system, which can improve the coherence of quantum bits. The technical solution is as follows.

[0006] In one aspect, a qubit assembly is provided, the qubit assembly comprising:

[0007] The underlying circuits and quantum bits;

[0008] The bottom circuit surface has a nitride passivation layer.

[0009] In another aspect, a method for preparing a quantum bit component is provided, the method comprising:

[0010] Preparing a bottom film of a quantum bit component on a substrate;

[0011] Prepare a bottom layer circuit based on the bottom layer film, wherein the bottom layer circuit has a nitride passivation layer on its surface;

[0012] A quantum bit connected to the underlying circuit is prepared on the substrate to obtain the quantum bit assembly.

[0013] On the other hand, a quantum chip is provided, wherein the quantum chip comprises the quantum bit component as described above.

[0014] On the other hand, a chip preparation system is provided, the system comprising: an evaporation machine, a glue coating machine, a photolithography machine and an etching machine;

[0015] The evaporator is used to prepare the bottom film of the quantum bit component on the substrate;

[0016] The glue coating machine, the photolithography machine and the etching machine are used to prepare a bottom layer circuit based on the bottom layer film, and the bottom layer circuit surface has a nitride passivation layer;

[0017] The evaporator, the glue coater, the photolithography machine and the etching machine are also used to prepare quantum bits connected to the underlying circuit on the substrate to obtain the quantum bit assembly.

[0018] In some embodiments, the system further includes a nitridation treatment device for performing a nitridation treatment to obtain the underlying circuit after the coating machine and the photolithography machine have exposed and etched the underlying film according to the pattern of the underlying circuit.

[0019] In some embodiments, the nitridation processing equipment includes a nitridation chamber for placing a first product obtained after exposing and etching the bottom film in a nitrogen environment and heating it to a first temperature.

[0020] In some embodiments, the first temperature is 800 degrees Celsius.

[0021] In some embodiments, the nitridation processing equipment includes a plasma cleaner or a plasma etcher, and the plasma cleaner or the plasma etcher is used to place the first product obtained after exposing and etching the underlying film in a nitrogen plasma injection environment and heat it to a second temperature and maintain it for a specified period of time.

[0022] In some embodiments, the second temperature is 300 degrees Celsius and the specified time period is 10 minutes.

[0023] In some embodiments, the nitridation processing equipment includes an evaporator for evaporating a nitride passivation layer on the first product obtained after exposing and etching the underlying film.

[0024] In some embodiments, the system further comprises:

[0025] A cleaning machine is used to rinse the surface of the first product to remove the oxide layer on the surface of the first product.

[0026] In some embodiments, the system further comprises a nitridation treatment device for performing a nitridation treatment on the bottom film;

[0027] The glue coating machine, the photolithography machine and the etching machine are used to expose and etch the bottom film after nitridation treatment according to the pattern of the bottom circuit to obtain the bottom circuit.

[0028] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0029] In the process of preparing quantum bit components, a nitride passivation layer is prepared on the surface of the underlying circuit, which can effectively avoid oxidation of the film surface, reduce the generation of TLS loss, and extend the coherence time of the quantum chip, and then be used to prepare superconducting quantum chips with long decoherence.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0032] Figure 1 This is a preparation flow chart of a superconducting quantum chip involved in this application;

[0033] Figure 2 It is a schematic diagram of the structure of a quantum bit component involved in an embodiment of the present application;

[0034] Figure 3 is a schematic structural diagram of another quantum bit component involved in an embodiment of the present application;

[0035] Figure 4 is a schematic diagram of the structure of a quantum chip involved in an embodiment of the present application;

[0036] Figure 5 is a flow chart of a method for preparing a quantum bit component provided by an exemplary embodiment of the present application;

[0037] Figure 6 is a flow chart of a method for preparing a quantum bit component provided in an embodiment of the present application;

[0038] Figure 7 It is a schematic diagram of plating a nitride passivation layer on a bottom film involved in the present application;

[0039] Figure 8 It is a schematic diagram of an etched groove sidewall oxide layer involved in the present application;

[0040] Fig. 9 is a flow chart of a method for preparing a quantum bit component provided in an embodiment of the present application;

[0041] Fig.10 is a schematic diagram of nitrogen ion implantation shown in an exemplary embodiment of the present application;

[0042] Fig.11is a flow chart of a method for preparing a quantum bit component according to an exemplary embodiment of the present application;

[0043] Fig.12 yes Fig.11 A flowchart of the preparation of a quantum bit assembly according to the embodiment shown;

[0044] Fig.13 is a schematic diagram of a chip preparation system shown in an exemplary embodiment of the present application;

[0045] Fig.14 It is a schematic diagram of an application scenario of a solution provided by an embodiment of the present application. DETAILED DESCRIPTION

[0046] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0047] Quantum bit (Qubit): In quantum information science, it is the unit of measurement of quantum information. Unlike classical bits, which can only be in one of the states of 0 or 1, qubits can be in both the 0 and 1 states at the same time, that is, the quantum superposition state of 0 and 1.

[0048] Josephson Junction: Also known as superconducting tunnel junction. It is generally a structure composed of two superconductors sandwiched by a very thin barrier layer (thickness ≤ the coherence length of Cooper electron pairs), such as S (superconductor)-I (semiconductor or insulator)-S (superconductor) structure, referred to as SIS. In the Josephson junction, superconducting electrons can pass through the semiconductor or insulator film from one side to the other side through the tunnel effect.

[0049] One preparation process of a Josephson junction is as follows: a structural pattern containing an undercut (also known as a Dolan bridge structure) is made on a double-layer electron beam photoresist on the surface of a substrate using an electron beam exposure method, and then a double-tilt evaporation method is used to prepare the junction region by first obliquely depositing a superconducting metal film, oxidizing it to form an oxide insulating layer, and then vertically depositing a superconducting metal film.

[0050] TLS loss: refers to the two-level system (TLS) in the superconducting quantum chip material. Due to the interaction with the microwaves in the quantum chip, it will shorten the coherence time of the quantum bit.

[0051] Exposure: A micro-nano processing technology that mainly involves ultraviolet lithography, which is to apply photoresist on the surface of the substrate sample, and then irradiate ultraviolet light through the mask to the substrate surface, use photochemical reaction to change the properties of the photoresist exposed to light, and then dissolve the area that reacts with light into a specific solution to achieve the purpose of making a specific pattern on the substrate.

[0052] Etching: A micromachining process that uses dry (other) and wet (liquid) methods to corrode metal or other materials to form the required structure.

[0053] Undercut: In the double-layer resist process, a window is opened by exposing and developing the photoresist of the upper layer. The bottom layer of resist continues to corrode in the developer and expands laterally, forming a structure that is narrow at the top and wide at the bottom.

[0054] Stripping solution: An organic solvent that can remove residual photoresist that has not reacted with light after the sample has been exposed and developed.

[0055] Quantum computers have attracted increasing attention due to their more powerful computing capabilities than traditional computers. Among them, quantum computing solutions based on superconducting systems are more eye-catching due to their good scalability and compatibility with existing semiconductor technologies.

[0056] The strong computing power of quantum computing is mainly due to the quantum superposition state. However, the superposition state based on quantum mechanics is easily disturbed by the environment and depolarized to the classical state. The time taken for depolarization is called relaxation time. The length of relaxation time directly affects the computing power of quantum computers. Therefore, how to prolong the coherence of quantum systems has become an important issue for quantum computers.

[0057] The influence of superconducting materials on coherence is mainly the TLS loss of the material itself. The TLS loss mainly comes from the oxide layer on the surface of the material. In order to reduce the TLS loss, some solutions are usually adopted, such as replacing the commonly used aluminum film with a niobium or tantalum film with a thinner oxide layer, or using hydrofluoric acid to remove the oxide layer and then placing it in a refrigerator to evacuate and cool it down as soon as possible.

[0058] The method for growing high-purity tantalum film in the above scheme can be summarized as follows:

[0059] 1. After replacing the aluminum film with a niobium film or a tantalum film, the coherence time can be greatly improved, but the niobium film or the tantalum film still has an oxide layer.

[0060] 2. Cooling down as quickly as possible after cleaning the oxide layer with hydrofluoric acid requires strict experimental conditions, and oxidation cannot be avoided.

[0061] Superconducting quantum chips are one of the important carriers that can be used to study quantum computing. They are generally composed of a substrate, a waveguide film layer (also commonly known as a large circuit structure), a quantum bit structure, and other structures.

[0062] Please refer to Figure 1 , which shows a preparation flow chart of a superconducting quantum chip involved in this application. Figure 1 As shown, the method may include the following steps:

[0063] Step 101, cleaning the substrate.

[0064] Among them, the substrate is mainly sapphire or silicon wafer, and the purpose of cleaning is mainly to remove organic impurities on the surface of the substrate. In addition, the step of cleaning the silicon wafer is also to remove the natural oxide layer on the surface of the silicon wafer.

[0065] Step 102, growing a bottom film of quantum bits on a substrate.

[0066] Among them, the bottom film can be selected as aluminum film, niobium film or tantalum film. The bottom film is mainly used to prepare the transmission lines, resonant cavities, capacitors and other large-sized structures of quantum chips;

[0067] Among them, the resonant cavity and capacitor have become the main sources of TLS loss because they are distributed with more microwave fields.

[0068] Step 103, exposing the bottom film to prepare transmission lines, resonant cavities, capacitors, etc.

[0069] Step 104, using an angled coating method to prepare a Josephson junction to form a quantum bit.

[0070] Step 105, measuring the quantum bit at low temperature.

[0071] It should be noted that in the steps of preparing quantum chips, since the bottom layer coating in step 102 needs to be followed by subsequent steps such as exposure, the bottom layer film will be oxidized in the air, resulting in TLS loss of the material itself, which in turn affects the coherence of the quantum bit.

[0072] Please refer to Figure 2 , which shows a schematic diagram of the structure of a quantum bit component involved in an embodiment of the present application. Figure 2 As shown, Figure 2 Part (a) is a top view of the quantum bit assembly. Figure 2 Part (b) in FIG. 1 is a cross-sectional view of a quantum bit assembly, which includes the following parts:

[0073] The underlying circuit 201 , and the quantum bit 202 .

[0074] The surface of the bottom circuit 201 has a nitride passivation layer 201 a.

[0075] That is, the quantum bit component includes an underlying circuit 201 and a quantum bit 202 , and the surface of the underlying circuit 201 has a layered structure of a nitride passivation layer 201 a .

[0076] The nitride passivation layer 201 a may correspond to the material of the bottom circuit 201 . For example, the material of the bottom circuit 201 is metal niobium, and the nitride passivation layer 201 a is a niobium nitride passivation layer.

[0077] Among them, the nitride passivation layer 201a may not correspond to the material of the underlying circuit 201, and the nitride passivation layer 201a can be evaporated by coating. For example, the material of the underlying circuit 201 is metal aluminum, and then a nitride passivation layer 201a of niobium nitride or tantalum nitride is evaporated on the underlying circuit 201.

[0078] To summarize, the quantum bit assembly shown in the embodiment of the present application includes an underlying circuit 201 and a quantum bit 202, and the surface of the underlying circuit 201 has a nitride passivation layer 201a, which can prevent oxidation of the underlying circuit surface 201, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0079] Based on the above Figure 2 For the examples shown, please refer to Figure 3 , which shows a schematic diagram of the structure of another quantum bit component involved in an embodiment of the present application. Figure 3 As shown, Figure 3 Part (a) is a top view of the quantum bit assembly. Figure 3 Part (b) in FIG. 1 is a cross-sectional view of a quantum bit assembly, which includes the following parts:

[0080] The underlying circuit 201 , and the quantum bit 202 .

[0081] The surface of the bottom circuit 201 has a nitride passivation layer 201 a.

[0082] like Figure 3 As shown, in a possible implementation, the side surface of the etching groove 203 of the bottom circuit has a nitride passivation layer 203a.

[0083] After the bottom film is exposed and etched according to the pattern of the bottom circuit, the inner wall of the etching groove 203 is still oxidized because it is not covered by the passivation layer. Therefore, the nitride passivation layer on the inner wall of the etching groove 203 can further prevent the oxidation of the side wall of the etching groove.

[0084] In this regard, the embodiments of the present application are based on the above Figure 2 In the illustrated embodiment, the side surface of the etching groove 203 of the bottom circuit also has a layered structure of a nitride passivation layer 203a.

[0085] That is, the quantum bit component includes an underlying circuit 201 and a quantum bit 202, and the surface of the underlying circuit 201 has a layered structure of a nitride passivation layer 201a, and the side of the etching groove 203 of the underlying circuit has a layered structure of a nitride passivation layer 203a.

[0086] The nitride passivation layer 203a may correspond to the material of the bottom circuit 203. For example, the material of the bottom circuit 203 is metal tantalum, and the nitride passivation layer 201a is a tantalum nitride passivation layer.

[0087] Among them, the nitride passivation layer 203a may not correspond to the material of the underlying circuit 201, and the nitride passivation layer 203a can be evaporated by coating. For example, the material of the underlying circuit 201 is metal aluminum, and then a nitride passivation layer 203a of niobium nitride or tantalum nitride is evaporated on the side of the etching groove 203.

[0088] The quantum bit component shown in the embodiment of the present application includes an underlying circuit 201 and a quantum bit 202, and the surface of the underlying circuit 201 has a nitride passivation layer 201a, and the inner wall of the etching groove 203 has a nitride passivation layer 203a. The nitride passivation layer 201a and the nitride passivation layer 203a can avoid oxidation of the surface of the underlying circuit 201 and the inner wall of the etching groove 203, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0089] In a possible implementation, the material of the bottom circuit is metal niobium, metal tantalum or metal aluminum, and the nitride passivation layer is a niobium nitride passivation layer, a tantalum nitride passivation layer or an aluminum nitride passivation layer.

[0090] In an embodiment of the present application, the material of the underlying circuit may be a superconducting material that can be nitrided, for example, the material of the underlying circuit is metal aluminum, metal niobium or metal tantalum, and accordingly, the above-mentioned nitride passivation layer may be an aluminum nitride passivation layer, a niobium nitride passivation layer or a tantalum nitride passivation layer.

[0091] The underlying circuit can be made of superconducting materials that can be nitrided, such as metal aluminum, metal niobium or metal tantalum. This not only facilitates the formation of a nitride passivation layer on the surface of the underlying circuit or the inner wall of the etching groove, but the nitride passivation layer can also inhibit the oxidation of the surface of the underlying circuit or the inner wall of the etching groove, reduce the generation of TLS loss, and extend the coherence time of the quantum bit; it can also improve the universality of the present technical solution and can be widely used in superconducting thin films such as aluminum film, niobium film or tantalum film.

[0092] In a possible implementation manner, the bottom layer circuit includes at least one of the following structures: a resonant cavity, a capacitor, and a transmission line.

[0093] Among them, in quantum bit components, the resonant cavity and capacitor have become the main sources of TLS loss because they are distributed with more microwave fields; in addition, the transmission line is also a large structure, which will also bring certain TLS loss.

[0094] In this regard, in an embodiment of the present application, in an underlying circuit including at least one structure of a resonant cavity, a capacitor, and a transmission line, the surface of the underlying circuit is covered with a nitride passivation layer to inhibit the formation of an oxide layer on the surface of the structure such as the resonant cavity, the capacitor, and the transmission line, thereby effectively reducing the generation of TLS and extending the coherence time of the quantum bit.

[0095] In a possible implementation, the thickness of the nitride passivation layer is 5-10 nanometers.

[0096] In the embodiment of the present application, the thickness of the nitride passivation layer on the bottom circuit surface and the side of the etching groove can be controlled to be 5-10 nanometers. On the one hand, the oxidation phenomenon on the bottom circuit surface and the side of the etching groove can be suppressed; on the other hand, the thickness of the nitride passivation layer can be prevented from being too large and affecting the performance of the quantum bit component.

[0097] Please refer to Figure 4 , which shows a schematic diagram of the structure of a quantum chip involved in an embodiment of the present application, such as Figure 4 As shown, the quantum chip provided in the embodiment of the present application includes one or more quantum bit components 401, and the quantum bit component 401 can be the above Figure 2 or Figure 3 quantum bit components.

[0098] Please refer to Figure 5 , which shows a flow chart of a method for preparing a quantum bit component provided by an exemplary embodiment of the present application. The method can prepare Figure 2 or Figure 3 The quantum bit components shown; Figure 5 As shown, the method may include the following steps:

[0099] Step 510: Prepare a bottom film of the quantum bit component on a substrate.

[0100] In the embodiment of the present application, a bottom film layer may be prepared on the substrate first, for example, by evaporating a superconducting material on the substrate through an evaporator, thereby preparing / growing a bottom film layer on the substrate.

[0101] Among them, the bottom film can be made of superconducting materials that can be nitrided, such as aluminum film, niobium film or tantalum film, to facilitate the subsequent formation of a nitride passivation layer on the surface of the bottom circuit to inhibit the oxidation of the bottom circuit surface or the inner wall of the etching groove, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0102] Before preparing the bottom film of the quantum bit component on the substrate, the substrate can be cleaned to remove organic impurities and oxide layers on the substrate.

[0103] Step 520: Prepare a bottom layer circuit based on the bottom layer film, wherein the surface of the bottom layer circuit has a nitride passivation layer.

[0104] In an embodiment of the present application, the steps of photoresist spin coating, exposure, photoresist cleaning, and bottom film etching can be performed on the bottom film according to the pattern / mask of the bottom circuit to prepare the bottom circuit on the substrate. In this process, the bottom film will also be nitrided so that the surface of the bottom circuit can have a nitride passivation layer. The nitride passivation layer can avoid oxidation of the surface of the bottom circuit, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0105] The nitride passivation layer may be selected from a niobium nitride passivation layer, a tantalum nitride passivation layer or an aluminum nitride passivation layer.

[0106] Step 530: Prepare quantum bits connected to the underlying circuit on the substrate to obtain a quantum bit assembly.

[0107] After preparing the underlying circuit with a nitride passivation layer, quantum bits connected to the underlying circuit can be further prepared. Since the surface of the underlying circuit has a nitride passivation layer, the oxidation phenomenon on the surface of the underlying circuit will be suppressed in the subsequent preparation process, and the final quantum bit component will have better coherence.

[0108] To summarize, in the scheme shown in the embodiment of the present application, in the prepared quantum bit component, the surface of the underlying circuit has a nitride passivation layer, and the nitride passivation layer can prevent oxidation of the surface of the underlying circuit, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0109] based on Figure 5 For the examples shown, please refer to Figure 6 , which shows a flow chart of a method for preparing a quantum bit component provided in an embodiment of the present application. Figure 6 As shown, Figure 5 Step 520 in the illustrated embodiment may be implemented as step 520a and step 520b.

[0110] Step 520a: Perform nitridation treatment on the bottom film.

[0111] In a possible implementation, the nitriding method shown in the embodiment of the present application may include the following steps:

[0112] First, the bottom film is grown on the substrate.

[0113] The bottom film may be an aluminum film, a niobium film or a tantalum film, the coating thickness may be 100-200 nm, and magnetron sputtering may be a preferred coating method.

[0114] Afterwards, a nitride passivation layer can be grown in situ on the underlying film.

[0115] Among them, since aluminum nitride has a piezoelectric effect, which affects the subsequent sample measurement, the passivation layer can be selected as niobium nitride or tantalum nitride, and the thickness of the passivation layer is 5-10nm.

[0116] In a possible implementation, the nitriding method shown in the embodiment of the present application may also include:

[0117] 1) The bottom film is placed in a nitrogen environment and heated to a first temperature.

[0118] That is, a nitridation treatment method is to place the bottom film in a nitrogen environment and apply a first temperature to the bottom film so that the nitrogen and the bottom film react to generate nitride, thereby forming a nitride passivation layer to prevent oxidation.

[0119] In a possible implementation, the first temperature is 800 degrees Celsius.

[0120] Optionally, the temperature applied to the bottom film is generally above 800 degrees Celsius, and 800 degrees Celsius can be selected in the embodiment of the present application.

[0121] 2) The bottom film is placed in a nitrogen plasma implantation environment and heated to a second temperature and maintained for a specified period of time.

[0122] Optionally, in order to increase the reaction efficiency, another method of nitridation treatment is to directly use nitrogen plasma, and the equipment can be selected as a plasma stripper or a plasma etcher.

[0123] In order to improve the injection efficiency, a certain temperature can be appropriately applied to the underlying film, at which time a few nanometers of nitride can be generated to form a nitride passivation layer to prevent oxidation.

[0124] In a possible implementation, the second temperature is 300 degrees Celsius, and the specified time is 10 minutes.

[0125] Optionally, the temperature applied to the bottom film can be heated to 300° C., and the injection time of the nitrogen plasma can be 10 minutes.

[0126] In summary, in the solution shown in the embodiment of the present application, since the TLS loss of nitride is smaller than that of oxide, the oxidation of the underlying film can be prevented after the nitride is grown, and the TLS loss can be reduced.

[0127] Step 520b: According to the pattern of the bottom layer circuit, the bottom layer thin film after nitridation is exposed and etched to obtain the bottom layer circuit.

[0128] In an embodiment of the present application, after the bottom film is nitrided based on step 520a, the bottom film can be subjected to the steps of photoresist spin coating, exposure, photoresist cleaning, bottom film etching, etc. according to the pattern / mask of the bottom circuit to prepare the bottom circuit on the substrate.

[0129] Since the bottom film is nitrided during the preparation of the bottom circuit, the surface of the bottom circuit can have a nitride passivation layer, the oxidation phenomenon on the surface of the bottom circuit will be suppressed, and the final quantum bit component can have better coherence.

[0130] The solution shown in the embodiment of the present application can be the quantum bit component obtained in the end. Figure 2 The quantum bit components, such as Figure 2 As shown, the surface of the bottom circuit 201 has a nitride passivation layer 201a, which can prevent oxidation of the surface of the bottom circuit, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0131] Please refer to Figure 7 , which shows a schematic diagram of plating a nitride passivation layer on a bottom film involved in the present application. Figure 7 As shown in FIG. 1 , after the bottom superconducting film is plated, a passivation layer can be introduced on the film surface to prevent the film from being oxidized. The method of growing the nitride passivation layer is relatively simple. However, in the subsequent steps, it is necessary to perform photoresist spin coating, exposure, photoresist cleaning, bottom film etching, etc. on the bottom film. At this time, the sidewalls of the etched grooves will still be oxidized because they are not covered by the passivation layer. Please refer to Figure 8 , which shows a schematic diagram of an etched groove sidewall oxide layer involved in the present application.

[0132] based on Figure 5 For the examples shown, please refer to Fig. 9 , which shows a flow chart of a method for preparing a quantum bit component provided in an embodiment of the present application. Fig. 9 As shown, Figure 5 Step 520 in the illustrated embodiment may be implemented as step 520c.

[0133] Step 520c: After exposing and etching the bottom film according to the pattern of the bottom circuit, perform nitridation treatment to obtain the bottom circuit.

[0134] After the bottom film is exposed and etched according to the bottom circuit pattern, the inner wall of the etching groove is not covered by the passivation layer and may still be oxidized. Figure 8 Schematic diagram of the oxide layer on the sidewall of the etched groove.

[0135] Therefore, after the steps of photoresist spin coating, exposure, photoresist cleaning, and etching of the underlying film, the surface of the underlying film and the side walls of the etching groove can be nitrided to obtain an underlying circuit with a nitride passivation layer on the surface, thereby avoiding oxidation of the underlying film and the side walls of the etching groove, reducing the generation of TLS, extending the coherence time of the quantum bit, and improving the coherence of the quantum bit.

[0136] In a possible implementation, the nitriding treatment includes:

[0137] The first product obtained after exposing and etching the bottom film is placed in a nitrogen environment and heated to a first temperature.

[0138] That is to say, one method of nitridation treatment is to place the product obtained after performing steps such as photoresist spin coating, exposure, photoresist cleaning, and bottom film etching on the bottom film according to the pattern of the bottom circuit into a nitrogen environment, and apply a first temperature to the film so that the nitrogen and the film react to generate nitride, thereby forming a nitride passivation layer to prevent oxidation.

[0139] The nitride passivation layer can prevent oxidation of the underlying film and the side walls of the etched groove, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0140] In a possible implementation, the first temperature is 800 degrees Celsius. Optionally, the first temperature may be lower than 800 degrees Celsius, or higher than 800 degrees Celsius. For example, the first temperature may be between 700 degrees Celsius and 900 degrees Celsius.

[0141] The temperature applied to the film is generally above 800 degrees Celsius, and this application embodiment selects 800 degrees Celsius. On the one hand, it can provide a suitable ambient temperature for nitrogen to react with the underlying film to generate nitride; on the other hand, it can prevent the ambient temperature from being too low to affect the anti-oxidation performance of the nitride or the nitride passivation layer.

[0142] In a possible implementation, the nitriding treatment includes:

[0143] The first product obtained after exposing and etching the bottom film is placed in a nitrogen plasma injection environment and heated to a second temperature and maintained for a specified period of time.

[0144] Among them, in order to increase the reaction efficiency, another method of nitridation treatment is to directly use nitrogen plasma, and the equipment can be selected as a plasma stripper or a plasma etcher.

[0145] That is to say, another method of nitridation treatment is to place the product obtained after the steps of photoresist spin coating, exposure, photoresist cleaning, and bottom film etching according to the pattern of the bottom circuit into a nitrogen plasma injection environment, so that the nitrogen and the bottom film react to generate nitride, forming a nitride passivation layer to prevent oxidation.

[0146] The nitride passivation layer can prevent oxidation of the underlying film and the side walls of the etched groove, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0147] Among them, the equipment can be a plasma degumming machine or a plasma etcher.

[0148] In order to improve the injection efficiency, a certain temperature can be applied to the film appropriately, at which time a few nanometers of nitride can be generated to form a nitride passivation layer to prevent oxidation.

[0149] In a possible implementation, the second temperature is 300 degrees Celsius, and the specified time is 10 minutes. Optionally, the second temperature may be lower than 300 degrees Celsius, or higher than 300 degrees Celsius; for example, the second temperature may be between 250 degrees Celsius and 350 degrees Celsius. Optionally, the specified time may be higher than 10 minutes, or lower than 10 minutes; for example, the specified time may be between 15 minutes and 25 minutes.

[0150] Among them, in the embodiment of the present application, the temperature applied to the film can be heated to about 300°C, and the injection time of nitrogen plasma can be about 10 minutes. On the one hand, it can provide a suitable ambient temperature and reaction time for the nitrogen and the underlying film to react to form nitrides; on the other hand, it can avoid the environmental temperature being too high or too low, the reaction time being too short or too long, and affecting the anti-oxidation performance of the nitride or nitride passivation layer.

[0151] In a possible implementation, the nitriding treatment includes:

[0152] A nitride passivation layer is evaporated on the first product obtained after exposing and etching the bottom film.

[0153] For example, the nitride passivation layer can be obtained by evaporating the nitride in situ coating manner.

[0154] For example, the following process can be performed in situ: a first product is obtained after exposing and etching the bottom film, the photoresist is cleaned, and a nitride passivation layer is grown on the first product. The bottom film can be selected as an aluminum film, a niobium film, or a tantalum film. Since aluminum nitride has a piezoelectric effect, which affects subsequent sample measurements, the nitride passivation layer can be selected as a niobium nitride or tantalum nitride passivation layer.

[0155] Alternatively, after the first product is obtained by exposing and etching the underlying thin film, the natural oxide layer on the surface of the first product may be cleaned before the nitride passivation layer is evaporated.

[0156] Since the TLS loss of nitride is less than that of oxide, the oxidation of the underlying film can be prevented after the nitride passivation layer is grown, and the TLS loss can be reduced. The embodiment of the present application can improve the universality of the technical solution and can be widely used in superconducting films such as aluminum film, niobium film or tantalum film.

[0157] In a possible implementation, before the nitriding treatment, the method further includes:

[0158] The surface of the first product is rinsed to remove an oxide layer on the surface of the first product.

[0159] That is to say, the etched sample needs to be rinsed first and then nitrided.

[0160] Among them, hydrofluoric acid can be used for rinsing, and the purpose of rinsing is to remove the surface oxide layer.

[0161] Since nitride is directly generated on the surface of the bottom film, the bottom film at this time may be a niobium film or a tantalum film. The specific implementation steps of the above embodiment may be:

[0162] First, the etched sample is rinsed with hydrofluoric acid to remove the surface oxide layer;

[0163] Then put it in a nitrogen environment and apply temperature to the film, which is generally above 800°C, so that the nitrogen and the film react to form nitride;

[0164] In order to increase the reaction efficiency, nitrogen plasma can also be used directly, and the equipment can be selected as a plasma stripper or a plasma etcher. In order to improve the injection efficiency, the film can also be properly heated, such as heating to 300°C, and the injection time of nitrogen plasma is 10 minutes.

[0165] At this time, several nanometers of nitride can be generated, which can provide good protection for the surface of the film and the side walls of the etching groove.

[0166] Based on the scheme shown in the embodiment of the present application, an improved method is provided, in which nitrogen ions are implanted after etching, wherein the injection direction of the nitrogen ions is at a certain angle, and the sample below needs to be rotated while being injected so that the sidewalls of the etched groove can be injected with nitrogen ions. Please refer to Fig.10 , which shows a schematic diagram of nitrogen ion implantation according to an exemplary embodiment of the present application. Fig.10 As shown, Fig.10 Part (a) is a schematic diagram of the nitrogen ion implantation process. Fig.10 Part (b) is a schematic diagram of the formation of a nitride passivation layer after nitridation treatment.

[0167] The solution shown in the embodiment of the present application can be the quantum bit component obtained in the end. Figure 3 The quantum bit components, such as Figure 3 As shown, it includes an underlying circuit 201 and a quantum bit 202, and the surface of the underlying circuit 201 has a nitride passivation layer 201a, and the inner wall of the etching groove 203 has a nitride passivation layer 203a. The nitride passivation layer 201a and the nitride passivation layer 203a can prevent oxidation of the surface of the underlying circuit, reduce the generation of TLS loss, and extend the coherence time of the quantum bit.

[0168] based on Figure 5 For the examples shown, please refer to Fig.11 , which shows a flow chart of a method for preparing a quantum bit component provided in an embodiment of the present application. Fig.11 As shown, Figure 5 Step 530 in the illustrated embodiment may be implemented as step 530a, step 530b, step 530c, step 530d, and step 530e.

[0169] Step 530a: Prepare a quantum bit structure that is not connected to the underlying circuit through a Dolan bridge photoresist structure; the quantum bit structure includes a three-layer structure, the three-layer structure includes a first superconducting part and a second superconducting part that intersect each other, and an insulating layer between the first superconducting part and the second superconducting part.

[0170] The quantum bit structure is located in the extension direction of the bottom layer circuit, that is, there is an exposed substrate between the bottom layer circuit and the quantum bit structure.

[0171] In the embodiment of the present application, the quantum bit structure is a Josephson junction, that is, the quantum bit structure is a superconductor-insulator-superconductor structure, and the first superconducting part and the second superconducting part are isolated by an insulating layer. The quantum bit structure can be prepared by a Dolan bridge photoresist structure.

[0172] Among them, the Dolan bridge photoresist structure is a photoresist structure used to prepare a Josephson junction.

[0173] In a possible implementation, step 530a may include the following steps:

[0174] 1) Applying a first photoresist on the sample of step 520 and performing a first bake, wherein the first photoresist defines a quantum bit structure;

[0175] The first photoresist may be a positive photoresist, a negative photoresist, or a combination of multiple layers of photoresist.

[0176] The first baking temperature is the soft baking temperature of the first photoresist.

[0177] For example, polymethylmethacrylate (PMMA) photoresist may be coated on the sample obtained in step 520 and baked at 160 degrees Celsius for 10 minutes.

[0178] 2) performing exposure, development, and fixing treatment on the sample to obtain a Dolan bridge photoresist structure. Different from the traditional structure, the Dolan bridge photoresist structure in the embodiment of the present application does not include a portion where the quantum bit structure is connected to the external circuit waveguide;

[0179] The exposure method may be electron beam exposure.

[0180] The developer may be methyl isobutyl ketone (MIBK) or a mixture of MIBK and isopropyl alcohol (IPA).

[0181] The fixing solution may be IPA.

[0182] For example, in this step, the sample can be placed in an electron beam exposure machine, exposed at a certain dose, then taken out and placed in a developer with a ratio of MIBK:IPA of 1:3 for development, and then placed in IPA for fixing to obtain a Dolan bridge structure.

[0183] 3) Double-angle evaporation of the sample:

[0184] ①Vertically evaporate the first superconducting material;

[0185] ②Preparing the insulating layer;

[0186] ③ Vapor-deposit the first superconducting material at a certain inclination angle.

[0187] Among them, the evaporation methods include electron beam evaporation, magnetron sputtering, or thermal evaporation, and the equipment used may include a dual-tilt multi-chamber coating machine.

[0188] The insulating layer may be an oxide layer.

[0189] The method for preparing the insulating layer may include dynamic oxygen oxidation or static constant pressure oxygen oxidation in a vacuum chamber.

[0190] The inclination angle of the inclined evaporation is 20°-70°.

[0191] The first superconducting material may be aluminum, tantalum, niobium or the like.

[0192] For example, in this step, the sample can be placed in a dual-tilt multi-chamber evaporation coating machine, first vertically evaporate 30nm thick aluminum, then use static oxidation to form an oxide insulating layer on the aluminum surface, and then tilt evaporate 30nm thick aluminum to form a Josephson junction structure.

[0193] Step 530b: Use a degumming solution to clean the sample of step 530a to obtain a structure containing a quantum bit structure that is not connected to the underlying circuit.

[0194] In a possible implementation, the debonding solution may include acetone, N-Methylpyrrolidone (NMP), or Remover PG (an NMP-based special debonding agent), etc.

[0195] For example, in this step, the sample obtained in step 530a can be placed in NMP for debonding and stripping.

[0196] Step 530c: removing the insulating layer in the first target region on the upper surface of the first superconducting portion and the insulating layer in the second target region on the upper surface of the second superconducting portion.

[0197] The first target area is the entire or partial area on the upper surface of the first superconducting part outside the area corresponding to the second superconducting part; correspondingly, the second target area is the entire or partial area on the upper surface of the second superconducting part outside the area corresponding to the first superconducting part.

[0198] In the embodiment of the present application, since the first superconducting portion and the second superconducting portion intersect each other, a portion of the upper surface of the first superconducting portion is blocked by the second superconducting portion, while the rest is exposed. In this regard, in the scheme shown in the embodiment of the present application, the insulating layer of a portion of the exposed area on the upper surface of the first superconducting portion (i.e., the above-mentioned first target area) is removed, so that the position of the first superconducting portion corresponding to the above-mentioned first target area is not covered by the insulating layer. Correspondingly, the scheme shown in the embodiment of the present application also removes the insulating layer of a portion of the upper surface of the second superconducting portion (i.e., the above-mentioned second target area).

[0199] In a possible implementation, step 530c may include the following steps:

[0200] 1) A second photoresist is coated on the sample in step 530b and a second bake is performed. The photoresist defines the portion where the quantum bit structure is connected to the underlying circuit.

[0201] The second photoresist may be a positive photoresist, or a negative photoresist, or a combination of multiple layers of photoresist, or may be a photoresist of the same type as the first photoresist.

[0202] The second baking temperature is the soft baking temperature of the second photoresist.

[0203] For example, in this step, AZ6112 photoresist may be coated on the surface of the sample obtained in step 530b and then baked at 100 degrees Celsius for a period of time.

[0204] 2) Perform photolithography, development and fixing to obtain a corresponding defined pattern, and then use an etching method to remove the exposed portion of the insulating layer produced in step 530a.

[0205] The above-mentioned photolithography method may include ultraviolet exposure or laser direct writing.

[0206] The developer may be tetramethylammonium hydroxide (TMAH) or a TMAH dilution.

[0207] The above etching methods include physical and / or reactive etching, and the etching equipment may include an ion beam etcher, a dry etcher, and the like.

[0208] For example, in this step, the sample can be placed in a laser direct writing device to engrave a pattern, then placed in a 2.38% concentration TMAH developer for development, and then fixed in deionized water to obtain the pattern of the connection area. The sample is then placed in an ion beam etcher to perform argon ion physical etching to remove the approximately 5 nm thick oxide insulating layer on the surface of the connection area that is exposed by the two layers of aluminum evaporated in step 530a.

[0209] Step 530d: evaporate a connection layer on the underlying circuit, the quantum bit structure, and the substrate between the underlying circuit and the quantum bit structure, wherein the connection layer is used to connect the first superconducting part and the second superconducting part to the underlying circuit in different regions, respectively.

[0210] In a possible implementation, a second superconducting material (or other superconducting materials other than the second superconducting material) may be evaporated on the sample in step 530c to connect the quantum bit structure with the underlying circuit.

[0211] Among them, the above-mentioned evaporation method may include electron beam evaporation, magnetron sputtering, thermal evaporation, etc.

[0212] For example, in this step, the sample obtained in step 530c can be placed in an electron beam evaporation coating machine to evaporate aluminum with a thickness of 100 nm to connect the Josephson junction to the underlying circuit.

[0213] Step 530e: Use a degumming solution to clean the sample in step 530d to obtain a quantum bit component containing a quantum bit structure connected to an underlying circuit.

[0214] In a possible implementation, the degumming solution may include acetone, NMP, Remover PG, etc.

[0215] For example, in this step, the sample obtained in step 530d can be immersed in NMP for peeling, and finally a quantum bit component containing a quantum bit structure connected to an underlying circuit is obtained.

[0216] Please refer to Fig.12 , which shows Fig.11 The preparation flow chart of the quantum bit assembly involved in the embodiment shown; Fig.12 As shown, after the above step 530a, the surface of the quantum bit structure will still be oxidized because it is not covered by the passivation layer. Therefore, the sample obtained in step 530a can be nitrided to inhibit the oxidation of the surface of the quantum bit structure and avoid affecting the characteristics of subsequent quantum bit components.

[0217] In a possible implementation, before step 530b, the step further includes: performing nitriding treatment on the sample in step 530a.

[0218] In a possible implementation, the nitridation treatment includes: placing the sample in step 530a in a nitrogen environment and heating it to a third temperature.

[0219] In a possible implementation, the third temperature is 800 degrees Celsius.

[0220] That is, a nitridation treatment method is to place the sample obtained after steps such as preparing a quantum bit structure that is not connected to the underlying circuit through a Dolan bridge photoresist structure in a nitrogen environment and heat it to 800 degrees Celsius, so that the nitrogen reacts with the surface of the quantum bit structure to generate nitride, forming a nitride passivation layer that prevents oxidation. The nitride passivation layer can prevent oxidation of the surface of the quantum bit structure, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0221] In a possible implementation, the nitridation treatment includes: placing the sample in step 530a in a nitrogen plasma injection environment, heating it to a fourth temperature, and maintaining it for a specified period of time.

[0222] In order to increase the reaction efficiency, nitrogen plasma can be used directly, and the equipment can be selected as a plasma stripper or a plasma etcher.

[0223] In a possible implementation, the fourth temperature is 300 degrees Celsius, and the specified time is 10 minutes.

[0224] That is to say, another method of nitridation treatment is to place the sample obtained after steps such as preparing a quantum bit structure that is not connected to the underlying circuit through a Dolan bridge photoresist structure in a nitrogen plasma injection environment, heat it to 300 degrees Celsius, and maintain it for 10 minutes, so that the nitrogen reacts with the surface of the quantum bit structure to generate nitride, forming a nitride passivation layer to prevent oxidation. The nitride passivation layer can avoid oxidation of the surface of the quantum bit structure, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0225] In a possible implementation, the nitridation treatment includes: evaporating a nitride passivation layer on the sample in step 530a.

[0226] That is to say, the nitride passivation layer can be obtained by evaporating the nitride in a coating manner.

[0227] For example, a nitride passivation layer is grown in situ on the surface of the quantum bit structure, and the nitride passivation layer can be selected as a niobium nitride or tantalum nitride passivation layer. Since the TLS loss of nitride is less than that of oxide, after the nitride passivation layer is grown, the oxidation of the surface of the quantum bit structure can be prevented and the TLS loss can be reduced.

[0228] After preparing a quantum bit structure with a nitride passivation layer on the surface, a connection layer connecting the quantum bit structure and the underlying circuit can be further prepared. Since the underlying circuit surface and the quantum bit structure surface have a nitride passivation layer, the oxidation phenomenon on the underlying circuit surface and the quantum bit structure surface will be suppressed in the subsequent preparation process, and the final quantum bit component will have better coherence.

[0229] like Fig.12 As shown, after the above step 530d, the surface of the connecting layer will still be oxidized because it is not covered by the passivation layer. Therefore, the sample obtained in step 530d can be nitrided to inhibit the oxidation of the surface of the connecting layer and avoid affecting the characteristics of subsequent quantum bit components.

[0230] In a possible implementation, before step 530e, the step further includes: performing nitriding treatment on the sample of step 530d.

[0231] In a possible implementation, the nitridation treatment includes: placing the sample in step 530d in a nitrogen environment and heating it to a fifth temperature.

[0232] In a possible implementation, the fifth temperature is 800 degrees Celsius.

[0233] That is, a nitridation treatment method is to place the sample obtained after evaporating the connection layer on the substrate between the bottom circuit, the quantum bit structure, and the bottom circuit and the quantum bit structure in a nitrogen environment and heat it to 800 degrees Celsius, so that the nitrogen reacts with the surface of the connection layer to form a nitride, forming a nitride passivation layer to prevent oxidation. The nitride passivation layer can avoid oxidation of the surface of the connection layer, reduce the generation of TLS loss, extend the coherence time of the quantum bit, and improve the coherence of the quantum bit.

[0234] In a possible implementation, the nitridation treatment includes: placing the sample in step 530d in a nitrogen plasma injection environment, heating it to a sixth temperature, and maintaining it for a specified period of time.

[0235] Among them, in order to increase the reaction efficiency, another method of nitridation treatment is to directly use nitrogen plasma, and the equipment can be selected as a plasma stripper or a plasma etcher.

[0236] In a possible implementation, the sixth temperature is 300 degrees Celsius, and the specified time is 10 minutes.

[0237] That is to say, another method of nitridation treatment is to place the sample obtained after evaporating the connection layer on the substrate between the underlying circuit, the qubit structure, and the underlying circuit and the qubit structure, in a nitrogen plasma injection environment, heated to 300 degrees Celsius, and maintained for 10 minutes, so that the nitrogen reacts with the surface of the connection layer to form a nitride, forming a nitride passivation layer to prevent oxidation. The nitride passivation layer can avoid oxidation of the connection layer surface, reduce the generation of TLS loss, extend the coherence time of the qubit, and improve the coherence of the qubit.

[0238] In a possible implementation, the nitridation treatment includes: evaporating a nitride passivation layer on the sample in step 530d.

[0239] That is to say, the nitride passivation layer can be obtained by evaporating the nitride in a coating manner.

[0240] For example, a nitride passivation layer is grown on the surface of the sample obtained after in-situ evaporation of the connection layer on the substrate between the bottom circuit, the qubit structure, and the bottom circuit and the qubit structure. The nitride passivation layer can be selected as a niobium nitride or tantalum nitride passivation layer. Since the TLS loss of nitride is less than that of oxide, after the nitride passivation layer is grown, the oxidation of the connection layer surface can be prevented and the TLS loss can be reduced.

[0241] After preparing a connecting layer with a nitride passivation layer on the surface, a quantum bit component in which the quantum bit structure is connected to the underlying circuit can be further prepared. Since the surface of the underlying circuit, the surface of the quantum bit structure and the surface of the connecting layer all have a nitride passivation layer, the oxidation phenomenon of the surface of the underlying circuit, the surface of the quantum bit structure and the surface of the connecting layer will be suppressed in the subsequent preparation process, and the final quantum bit component will have better coherence.

[0242] Fig.13 FIG. 1 shows a schematic diagram of a chip preparation system shown in an exemplary embodiment of the present application, and the chip preparation system can be implemented as a production line device; Fig.13 As shown, the chip preparation system includes:

[0243] Evaporation machine 1301, glue coating machine 1302, photolithography machine 1303 and etching machine 1304;

[0244] The evaporator 1301 is used to prepare the bottom film of the quantum bit component on the substrate;

[0245] The glue coating machine 1302, the photolithography machine 1303 and the etching machine 1304 are used to prepare the bottom circuit based on the bottom film, and the surface of the bottom circuit has a nitride passivation layer;

[0246] The vapor deposition machine 1301, the glue coating machine 1302, the photolithography machine 1303 and the etching machine 1304 are also used to prepare quantum bits connected to the underlying circuit on the substrate to obtain quantum bit components.

[0247] In a possible implementation, the system further includes a nitridation treatment device for performing a nitridation treatment to obtain the bottom layer circuit after the coater 1302 and the photolithography machine 1303 expose and etch the bottom layer film according to the pattern of the bottom layer circuit.

[0248] In a possible implementation, the nitridation treatment equipment includes a nitridation chamber 1306 for placing a first product obtained after exposing and etching the bottom film in a nitrogen environment and heating it to a first temperature.

[0249] In a possible implementation, the first temperature is 800 degrees Celsius.

[0250] In one possible implementation, the nitridation processing equipment includes a plasma cleaner or a plasma etcher, which is used to place the first product obtained after exposing and etching the underlying film in a nitrogen plasma injection environment, heat it to a second temperature, and maintain it for a specified period of time.

[0251] In a possible implementation, the second temperature is 300 degrees Celsius, and the specified time is 10 minutes.

[0252] In a possible implementation, the nitridation treatment equipment includes an evaporator 1301, which is used to evaporate a nitride passivation layer on the first product obtained after exposing and etching the underlying film.

[0253] In a possible implementation, the system further includes:

[0254] The cleaning machine 1305 is used to rinse the surface of the first product to remove the oxide layer on the surface of the first product.

[0255] In a possible implementation, the system further includes a nitridation treatment device for performing a nitridation treatment on the bottom film;

[0256] The glue coating machine 1302, the photolithography machine 1303 and the etcher 1304 are used to expose and etch the bottom film after nitridation treatment according to the pattern of the bottom circuit to obtain the bottom circuit.

[0257] Optionally, the production line equipment also includes a power supply to supply power to electrical equipment such as a processor, an etcher 1304 , a photolithography machine 1303 , and a vapor deposition machine 1301 .

[0258] Optionally, the machines are spatially connected via a conveyor belt, or the movement of the prepared products between the machines is accomplished by a robotic arm.

[0259] Optionally, the production line equipment also includes a memory, which can be used to store at least one computer instruction, and the processor executes the at least one computer instruction so that the production line equipment executes the above-mentioned quantum bit component preparation method.

[0260] Please refer to Fig.14 , which shows a schematic diagram of an application scenario of a solution provided by an embodiment of the present application. Fig.14 As shown, the application scenario may be a superconducting quantum computing platform, which includes: a quantum computing device 1401 , a dilution refrigerator 1402 , a control device 1403 and a computer 1404 .

[0261] The quantum computing device 1401 is a circuit that acts on a physical quantum bit. The quantum computing device 1401 can be realized as a quantum chip, such as a superconducting quantum chip near absolute zero. The quantum chip can be prepared by the scheme shown in the above embodiment of the present application. The dilution refrigerator 1402 is used to provide an absolute zero environment for the superconducting quantum chip.

[0262] The control device 1403 is used to control the quantum computing device 1401, and the computer 1404 is used to control the control device 1403. For example, the written quantum program is compiled into instructions by the software in the computer 1404 and sent to the control device 1403 (such as an electronic / microwave control system). The control device 1403 converts the above instructions into electronic / microwave control signals and inputs them into the dilution refrigerator 1402 to control the superconducting quantum bits at a temperature less than 10mK. The reading process is the opposite, and the reading waveform is transmitted to the quantum computing device 1401.

[0263] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

[0264] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A quantum bit component, characterized in that: The quantum bit assembly comprises: The underlying circuits and quantum bits; The bottom circuit surface has a nitride passivation layer.

2. The quantum bit assembly according to claim 1, characterized in that The side surfaces of the etching grooves of the bottom circuit are provided with a nitride passivation layer.

3. The quantum bit assembly according to claim 1 or 2, characterized in that: The material of the bottom circuit is metal niobium, metal tantalum or metal aluminum, and the nitride passivation layer is a niobium nitride passivation layer, a tantalum nitride passivation layer or an aluminum nitride passivation layer.

4. The quantum bit assembly according to claim 1 or 2, characterized in that: The bottom layer circuit includes at least one of the following structures: Resonant cavity, capacitor and transmission line.

5. The quantum bit assembly according to claim 1 or 2, characterized in that: The thickness of the nitride passivation layer is 5-10 nanometers.

6. A method for preparing a quantum bit component, characterized in that: The method comprises: Preparing a bottom film of a quantum bit component on a substrate; Preparing a bottom layer circuit based on the bottom layer film, wherein the surface of the bottom layer circuit has a nitride passivation layer; A quantum bit connected to the underlying circuit is prepared on the substrate to obtain the quantum bit assembly.

7. The method according to claim 6, characterized in that The method of preparing a bottom layer circuit based on the bottom layer film comprises: After the bottom layer film is exposed and etched according to the pattern of the bottom layer circuit, a nitridation treatment is performed to obtain the bottom layer circuit.

8. The method according to claim 7, characterized in that The nitriding treatment comprises: The first product obtained by exposing and etching the bottom film is placed in a nitrogen environment and heated to a first temperature.

9. The method according to claim 8, characterized in that The first temperature is 800 degrees Celsius.

10. The method according to claim 7, characterized in that The nitriding treatment comprises: The first product obtained after exposing and etching the bottom film is placed in a nitrogen plasma injection environment and heated to a second temperature, and maintained for a specified period of time.

11. The method according to claim 7, characterized in that The nitriding treatment comprises: A nitride passivation layer is evaporated on the first product obtained after exposing and etching the bottom film.

12. The method according to claim 8, 10 or 11, characterized in that: Before the nitriding treatment, the method further comprises: The surface of the first product is rinsed to remove an oxide layer on the surface of the first product.

13. The method according to claim 6, characterized in that The method of preparing a bottom layer circuit based on the bottom layer film comprises: Performing nitridation treatment on the bottom film; According to the pattern of the bottom layer circuit, the bottom layer thin film after nitridation is exposed and etched to obtain the bottom layer circuit.

14. A quantum chip, characterized in that: The quantum chip comprises the quantum bit component as described in any one of claims 1 to 5.

15. A chip preparation system, characterized in that: The system includes: an evaporation machine, a glue coating machine, a photolithography machine and an etching machine; The evaporator is used to prepare the bottom film of the quantum bit component on the substrate; The glue coating machine, the photolithography machine and the etching machine are used to prepare a bottom layer circuit based on the bottom layer film, and the bottom layer circuit surface has a nitride passivation layer; The evaporator, the glue coater, the photolithography machine and the etching machine are also used to prepare quantum bits connected to the underlying circuit on the substrate to obtain the quantum bit assembly.

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