Field effect transistor and manufacturing method thereof

Abstract

According to the field effect transistor and the manufacturing method thereof provided by the invention, a cantilever beam is directly formed on a silicon substrate by adopting a lateral etching process, a space below the cantilever beam is filled with a dielectric layer to form a silicon-on-insulator structure, and at least one part of a drain electrode and / or a channel is formed on the cantilever beam. According to the manufacturing method, an additional substrate does not need to be introduced, expensive silicon-on-insulator (SOI) forming technologies such as oxygen ion implantation segmentation and silicon bonding are avoided, and the field effect transistor manufactured and formed through the manufacturing method is high in integration level, low in power consumption and good in heat dissipation performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a field effect transistor and a manufacturing method thereof. Background Art

[0002] With the development of Moore's Law, the size of transistors is constantly shrinking, with the goal of pursuing the manufacture of higher performance and higher density transistors. As the size of transistors continues to shrink, the problems faced by transistors are becoming more and more serious. As the channel length of transistors continues to shrink, the short-channel effect leads to higher and higher leakage levels, so the doping concentration of the channel, especially the concentration of pocket ion implantation (Halo implantation), has to be increased. However, this will lead to two unfavorable factors. First, the increase in the concentration of Halo implantation will lead to an increase in the PN junction electric field formed by the drain and the channel. Such a high electric field is prone to gate-induced drain leakage. Second, the increase in doping concentration will lead to a deterioration in the uniformity of the transistor threshold voltage, which is caused by the random fluctuations of the ion implanted dopants. For this reason, the industry proposes the use of fully depleted and partially depleted active silicon on insulator technology (PD-SOI, full depletion-silicon on insulator or FD-SOI, partial depletion-silicon on insulator). Such technology causes the channel to be partially or completely depleted. This reduces leakage current and significantly reduces the doping concentration of the channel, reducing the impact of random fluctuations in dopants caused by ion implantation.

[0003] The difference between FD-SOI and PD-SOI is the depth of the channel, that is, the thickness of silicon. Generally speaking, the thickness of PD-SOI is greater than 0.15 um. However, both FD-SOI and PD-SOI require a substrate material such as SOI to prepare the corresponding transistors. Therefore, SOI substrate is the biggest challenge of this technology. The industry already has mature technologies, mainly separation by implantation of oxygen (SIMOX) technology and silicon bonding technology (Bondsilicon), but both technologies are costly and have a narrow range of applications. It is difficult to ensure that field-effect transistors such as FD-SOI or PD-SOI can meet basic requirements such as low power consumption while also taking into account low-cost requirements. Summary of the invention

[0004] Based on the above-described problems, the present invention proposes a field effect transistor and a manufacturing method thereof, which uses a lateral etching process to directly form a cantilever beam on a silicon substrate, fills a dielectric layer in the space below the cantilever beam to form a silicon-on-insulator (SOI) structure, and forms at least a portion of the drain and / or channel on the cantilever beam. The manufacturing method does not require the introduction of an additional substrate, avoids the use of expensive silicon-on-insulator (SOI) formation technologies such as oxygen ion implantation segmentation and silicon bonding, and the manufacturing method facilitates the compatibility of the manufacturing process of the field effect transistor with other device processes during chip manufacturing, saving manufacturing costs in many aspects; and the field effect transistor manufactured by the manufacturing method can have high integration, low power consumption, and good heat dissipation performance.

[0005] In a first aspect, an embodiment of the present invention provides a method for manufacturing a field effect transistor, the method comprising the steps of: S1: providing a silicon wafer as a substrate; S2: forming a cantilever beam in the substrate by using a lateral etching process; S3: filling a first dielectric layer in the space below the cantilever beam, wherein the first dielectric layer and the cantilever beam form a silicon-on-insulator structure; S4: At least a portion of the drain and / or at least a portion of the channel of the field effect transistor are formed on the cantilever beam.

[0006] In a specific embodiment, the field effect transistor includes a gate, a source, and a drain, and the gate, the source, and the drain are all formed on the cantilever beam.

[0007] In a specific embodiment, only the drain and / or a portion of the channel of the field effect transistor is formed on the cantilever beam.

[0008] In a specific embodiment, the cantilever beam is completely suspended relative to the substrate, and the cantilever beam is supported by the first dielectric layer.

[0009] In a specific embodiment, the cantilever beam is partially suspended relative to the substrate, and the cantilever beam is supported by the connecting portion and / or the first dielectric layer. The connecting portion can also be used for heat dissipation and carrier transport.

[0010] In a specific embodiment, the field effect transistor includes a source, and the connecting portion is located in a region corresponding to a projection of the source.

[0011] In a specific embodiment, the connecting portion is located at two end portions of the cantilever beam, and the directions of the two end portions are located in the length direction of the channel of the field effect transistor.

[0012] In a specific embodiment, the transistor includes a gate, which is formed on the cantilever beam, and the gate is formed to be located only at the top of the cantilever beam; or the gate is formed to be located not only at the top of the cantilever beam but also at both side surfaces of the cantilever beam; or the gate is formed to be located not only at the top of the cantilever beam but also at both side surfaces and the bottom outer surface of the cantilever beam.

[0013] In a specific embodiment, the step S2 specifically further includes the steps of: S21: preparing a hard mask template including a first through hole and a second through hole on the substrate by using a groove forming mask; S22: Etching downwards according to the positions of the first through hole and the second through hole, and increasing the lateral etching component to form the cantilever beam.

[0014] In a specific embodiment, the step S2 specifically further includes the steps of: S23: performing epitaxial growth on the outer side of the cantilever beam to form an epitaxial growth layer; S24: performing self-aligned etching on the epitaxial growth layer using the hard mask template, and etching the remaining epitaxial growth layer to form a part of the cantilever beam.

[0015] In a specific embodiment, the step S2 specifically further includes the steps of: S21: pre-forming a first groove and a second groove on the substrate; S22: Perform lateral etching so that the lower portion of the portion between the first groove and the second groove is at least partially etched away so that the upper portion is suspended to form a cantilever beam.

[0016] In a specific embodiment, the first trench and the second trench are arranged in a channel width direction or a length direction of the field effect transistor.

[0017] In a specific embodiment, the lateral etching is bidirectional etching performed simultaneously in the first trench and the second trench.

[0018] In a specific embodiment, the step 21 further includes the following steps: S211: forming a hard mask on the substrate by using a groove forming mask; S212: Etching the substrate using the hard mask to form the first trench and the second trench of a certain depth.

[0019] In a specific embodiment, after step 21 and before step 22, the method further includes the following steps: S2-1: depositing a second dielectric layer in the first trench and the second trench on the substrate; S2-2: Carve the second dielectric layer corresponding to the bottom of the first groove and the second groove, and continue etching downward to a certain depth to reserve sufficient side etching space.

[0020] In a specific embodiment, the step S2 specifically further includes the steps of: S23: baking the cantilever beam in a high-temperature hydrogen atmosphere.

[0021] In a specific embodiment, the step S4 further includes the step of forming a planar gate on the cantilever beam: S41: growing a gate oxide layer in a partial area of ​​the cantilever beam; S42: Covering the polysilicon, using the gate to form a mask, and forming a polysilicon gate on the gate oxide layer.

[0022] In a specific embodiment, the step S4 further includes the step of forming a three-dimensional gate on the cantilever beam: S41: using a transistor forming region definition mask and using the hard mask for self-aligned etching to open the first dielectric layer on both sides of the active region; S42: growing a gate oxide layer in a partial area of ​​the cantilever beam; S43: filling polysilicon, using the gate to form a mask, and forming a polysilicon gate on the gate oxide layer.

[0023] In a specific embodiment, the step S4 further includes the steps of: S44: performing a sidewall process on the polysilicon gate; S45: performing source-drain ion doping on the two side regions of the gate to form the source and drain.

[0024] In a specific embodiment, a fully depleted and / or partially depleted field effect transistor is formed by varying the thickness of the cantilever beam.

[0025] In a second aspect, the present invention further provides a field effect transistor, which is formed by the method for forming a field effect transistor described in any of the above embodiments.

[0026] The field effect transistor and the method for forming the same according to the embodiment of the present invention have the following beneficial effects compared with the prior art: (1) A cantilever beam is directly formed on a silicon substrate by a lateral etching process, and a silicon-on-insulator (SOI) structure is formed by filling a dielectric layer in the space below the cantilever beam. This manufacturing method does not require the introduction of an additional substrate, avoids the use of expensive technologies such as oxygen ion implantation segmentation and silicon bonding, and reduces the manufacturing cost of field effect transistors. This manufacturing method also facilitates the compatibility of the manufacturing process of field effect transistors with other device processes on the chip, which can simplify the chip manufacturing process. The simplified manufacturing process can also further reduce costs. In addition, the setting of the dielectric layer filled below the cantilever beam can greatly reduce or even avoid the parasitic capacitance generated by the device above the cantilever beam, thereby greatly reducing power consumption.

[0027] (2) In some application scenarios, the gate of the embodiment of the present invention is preferably a three-dimensional field effect transistor in the form of a three-dimensional gate structure. The three-dimensional gate structure can provide a channel size that meets the performance requirements, which is conducive to circuit integration and is also conducive to the implementation of the process of "forming a cantilever directly on a silicon substrate by a lateral etching process, and forming a silicon-on-insulator (SOI) structure by filling a dielectric layer in the space below the cantilever" in the present invention. Because, in order to ensure process accuracy, the depth of the lateral etching process cannot be unlimited, and the area size of the channel of the three-dimensional gate can be made much smaller than that of the horizontal gate, which can ensure the controllability of the lateral etching process and improve the yield of the manufactured field effect transistor.

[0028] (3) In some application scenarios, since the drain or channel is the most likely region to generate parasitic capacitance, in an embodiment of the present invention, at least a portion of the drain and / or channel is formed on the cantilever beam. The dielectric layer filled under the cantilever beam can avoid a large amount of parasitic capacitance generated by the drain and / or channel, thereby greatly reducing power consumption.

[0029] (4) In some application scenarios, the cantilever beam is completely suspended, and the source, drain, gate and other structures are all located on the cantilever beam. The parasitic capacitance generated by the source, drain and gate can be reduced or avoided. By using a mask etching compatible with other processes to make a fully suspended cantilever beam, the cantilever beam is completely isolated and supported from the silicon substrate by a dielectric layer. The parasitic capacitance of the field effect transistor can be further reduced without increasing the manufacturing cost, thereby reducing the power consumption of the field effect transistor.

[0030] (5) In some application scenarios, the side surfaces of the source and / or drain on the cantilever beam are exposed to the shallow trench isolation, which can increase the contact area between the source and / or drain and the dielectric layer, further reduce the parasitic capacitance of the field effect transistor, and thus reduce the power consumption of the field effect transistor.

[0031] (6) In some application scenarios, the cantilever beam is partially suspended. Since the drain or channel area is most likely to generate parasitic capacitance, and the heat generated by the field effect transistor cannot be ignored, the embodiment of the present invention partially suspends the cantilever beam. For example, in one embodiment of the present invention, a portion of the drain and / or channel is formed on the cantilever beam, and the other portion is not arranged on the cantilever beam. The dielectric layer filled under the cantilever beam can avoid the large amount of parasitic capacitance generated by the drain and / or channel, thereby greatly reducing power consumption. At the same time, at least the portion corresponding to the source is connected to the silicon substrate body. Since the heat dissipation performance of the silicon substrate material is better than that of the dielectric layer, the large amount of heat generated by the field effect transistor on the cantilever beam can be easily diffused through the portion connected to the silicon substrate, taking into account the heat dissipation requirements of the field effect transistor and greatly reducing the probability of thermal damage to the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings of the present invention constitute a part of this specification and are used to further understand the present invention. The drawings illustrate embodiments of the present invention and together with the description are used to explain the principle of the present invention.

[0033] Figure 1 The figure is a process flow diagram of a field effect transistor structure according to an embodiment of the present invention.

[0034] Figure 2-4b Schematic diagrams of three-dimensional structures of different embodiments of field effect transistors.

[0035] Figure 5a-5c BB' cross-sectional schematic diagrams of different embodiments of field effect transistors.

[0036] Figure 6 FIG. 4 is a process flow chart of a field effect transistor structure according to an embodiment of the present invention.

[0037] Figure 7 FIG. 4 is a process flow chart of a field effect transistor structure according to another embodiment. Implementation

[0038] The following detailed descriptions are all illustrative and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention.

[0040] In a first aspect, an embodiment of the present invention provides a method for manufacturing a field effect transistor, such as Figure 1As shown, a method for manufacturing a field effect transistor provided by an embodiment of the present invention is provided, wherein the method comprises a method for manufacturing a cantilever beam structure, and the method for manufacturing a cantilever beam structure comprises the following steps: S1: providing a silicon wafer as a substrate; S2: Forming a cantilever beam in the substrate using a lateral etching process.

[0041] S3: filling a first dielectric layer in the space below the cantilever beam, wherein the first dielectric layer and the cantilever beam form a silicon-on-insulator structure; S4: At least a portion of the drain and / or at least a portion of the channel of the field effect transistor are formed on the cantilever beam.

[0042] like Figure 2 As shown in FIG. 1 , an example of a three-dimensional structure of a field effect transistor manufactured by the method for manufacturing a field effect transistor in the above-mentioned embodiment is shown. The field effect transistor includes a gate, a source, and a drain. At least a portion of the drain and / or at least a portion of the channel are formed on the cantilever. It can be that only the drain and / or a portion of the channel of the field effect transistor are formed on the cantilever. It can also be that Figure 2 As shown in FIG. 1 , the gate, source, and drain are all formed on the cantilever beam. Figure 2 As shown, the field effect transistor is arranged on a silicon substrate 1, including a cantilever beam 1', and the cantilever beam manufacturing method of the cantilever beam 1' is to directly perform lateral etching on a silicon wafer, and a fully depleted and / or partially depleted field effect transistor can be formed according to the thickness of the cantilever beam. The field effect transistor also includes a source 3, a drain 4, a gate 2, and a gate oxide layer 6. Among them, a channel (not shown) is formed in the area between the source 3 and the drain 4, and a first dielectric layer 5 is filled under the cantilever beam 1'.

[0043] Among them, in the attached Figure 2 In the embodiment shown, the source 3, the drain 4 and the gate 2 are all formed on the suspension beam, and the suspension beam 1' is completely suspended above the substrate 1, that is, the suspension beam 1' is completely supported and insulated by the first dielectric layer 5. The source 3, the drain 4 and the gate 2 can greatly reduce or avoid the generation of parasitic capacitance by filling the first dielectric layer 5, thereby greatly reducing the power consumption of the field effect transistor. The completely suspended suspension beam 1' can make the parasitic capacitance of the source, drain, channel and other regions all be set on the suspension beam 1', so that the parasitic capacitance of these regions can be reduced or even avoided, so that the field effect transistor can be more suitable for high-speed and low-power circuits.

[0044] Attached Figure 2 The figure also shows that the gate 2 is formed as an "n" type three-dimensional gate, that is, the field effect transistor is formed as a fin field effect transistor. Figure 2 The three-dimensional grid can cover the top surface of the suspension beam 1' and the two side surfaces of the suspension beam 1' in the channel width direction, but the three-dimensional grid is not limited to the attached Figure 2As shown, the three-dimensional gate can also be a ring gate, that is, it is arranged around the circumference of the suspension beam 1' in the channel width direction (i.e., the A-A' direction), and is formed to be located not only on the top of the suspension beam but also on the two side surfaces and the bottom outer side surface of the suspension beam. The gate 2 is not limited to a three-dimensional gate, but can also be a horizontal gate, that is, the gate only includes the position located above the top of the suspension beam.

[0045] Compared with the horizontal gate, the preferred embodiment is the three-dimensional gate. Since the three-dimensional gate needs to occupy a much smaller plane size, when it is made into a three-dimensional gate to form a field effect transistor, the size requirements for the cantilever beam 1' will also be lower, and the required width and length dimensions will be smaller. The small cantilever beam size means that the process can be more precise and the error can be smaller during the lateral etching, which is more conducive to reducing the risk of etching damage, and thus it is more conducive to directly performing the lateral etching process on the silicon wafer to form the cantilever beam without epitaxy on the silicon wafer.

[0046] In a specific embodiment, the cantilever beam 1' is not limited to Figure 2 The complete suspension shown may also be partial suspension, for example Figure 3 As shown, the cantilever beam 1' and the substrate 1 are integrated, and the two end portions of the cantilever beam 1' are connected to the substrate 1 as a whole through the connecting portion 1". Alternatively, one of the end portions is connected to the substrate 1 as a whole through the connecting portion 1". The cantilever beam can be supported by the connecting portion and / or the first dielectric layer. In addition to providing support, the connecting portion can also be used for heat dissipation and carrier transport of semiconductor devices such as field effect transistors on the cantilever beam.

[0047] Among them, to form a completely suspended cantilever beam 1', it is necessary to reserve a connecting portion 1" of the cantilever beam in the lateral etching process step, and after the first dielectric layer 5 is filled into the space below the cantilever beam, the connecting portion 1" of the cantilever beam 1' can be removed through an additional etching step or a synchronous process with other structures to form a completely suspended cantilever beam 1'.

[0048] In a specific embodiment, at least the end of the drain electrode passes through the end of the suspension beam 1 ', such as Figure 4a-4b As shown in FIG. 1 , it is a schematic diagram of the ends of the source and drain electrodes penetrating the ends of the suspension beam, and the drain electrode 4 and / or the source electrode 3 are formed by penetrating the end of the suspension beam 1 '. In actual integrated circuit manufacturing, the advantage of such formation is that the outer end region of the drain electrode 4 and / or the source electrode 3 can contact the insulating dielectric layer filled in the shallow trench isolation, that is, the drain electrode 4 and / or the source electrode 3 are completely isolated by the insulating dielectric, so that the parasitic capacitance can be further reduced. Specifically, Figure 5a As shown, it is attached Figure 4aIn the cross-sectional diagram along the B-B' direction, in actual integrated circuit manufacturing, the area on the end side of the drain 4 and / or source 3 also includes an STI (shallow trench isolation) area 7. In this embodiment, the end of the drain 4 and / or source 3 is exposed in the shallow trench isolation trench, and the end of the drain 4 and / or source 3 can be covered and contacted by the insulating medium subsequently filled in the shallow trench isolation trench, so that the parasitic capacitance can be further reduced, reducing the power consumption of the field effect transistor. The situation where the drain 4 and / or source 3 passes through the end of the suspension beam 1' is not limited to a completely suspended suspension beam, and can also be applied to a partially suspended suspension beam in any form. For example, the attached Figure 4b As shown, the cantilever beam 1' and the substrate 1 are integrated through the connecting portion 1". Figure 4b The position of the connecting portion 1″ relative to the cantilever beam 1′ is only an example, and the present embodiment is not limited thereto.

[0049] In a specific embodiment, only the drain and / or part of the channel are located on the suspension beam, which also belongs to the scope of the present invention. Since the SOI device has the problem of heat dissipation, based on this, this embodiment considers that the gate (or channel), drain, source, etc. do not have to be all located on the suspension beam 1'. For example, optionally, part or all of the drain is located on the suspension beam 1', part or all of the channel is located on the suspension beam 1', part or all of the source is located on the suspension beam 1', part or all of the gate is located on the suspension beam 1', etc., taking into account the reduction of parasitic capacitance and the alleviation of heating conditions. The inventor found that the parasitic capacitance generated in the drain region of the field effect transistor is relatively significant, and the parasitic capacitance generated in the channel region is often not negligible. Based on this, a preferred embodiment is to set the drain and / or part of the channel on the suspension beam, and the other part is not set on the suspension beam, then the drain located above the suspension beam, or / and the part of the channel can be reduced by the first dielectric layer 5 set below the suspension beam 1'. In this way, the need to significantly reduce the parasitic capacitance and alleviate the heating condition of SOI can be taken into account.

[0050] In a specific embodiment, in order to form only a portion or all of the drain and / or the channel on the cantilever beam, the cantilever beam 1' may not be completely suspended above the substrate 1. Figure 5b , which is a schematic diagram of a drain and a channel formed on a cantilever beam, the cantilever beam 1' is not completely suspended relative to the substrate 1, the cantilever beam 1' is connected to the substrate 1 through a connecting portion 1'' to form an integral structure, and the cantilever beam 1' is supported by the first dielectric layer 5 and / or the connecting portion 1". Figure 5b As shown in the figure, the source region is located above the connecting portion 1 ″, and the drain and gate (channel) regions are located above the cantilever beam 1 ′.

[0051] Due to the setting of the connecting part 1'', the cantilever beam can be prevented from falling off when the cantilever beam is formed by lateral etching. Compared with the process of fully suspended cantilever beam 1', the connecting part is retained, so that the implementation process of partially suspended cantilever beam 1' is more selective. Among them, the appropriate etching direction can be selected according to the actual process accuracy, cost and other needs, and it can also be selected according to the process compatibility requirements whether to etch away the connecting part retained by lateral etching through subsequent processes, without being limited by the filling order of the first dielectric layer 5. Compared with the process of fully suspended, in which the first dielectric layer 5 must be filled before the connecting part can be removed, the process cost of partial suspension is lower.

[0052] In addition, it should be particularly mentioned that the suspension beam 1 is not completely suspended above the substrate 1, which is particularly beneficial to the heat dissipation during the operation of the field effect transistor, because the heat dissipation efficiency of the insulating medium is much lower than the heat dissipation efficiency of the silicon substrate material. When the suspension beam 1' is partially suspended by the connecting portion 1', the heat generated during the operation of the field effect transistor will be quickly dissipated through the suspension beam 1', the connecting portion 1'', and the substrate 1, thereby improving the heat dissipation of the field effect transistor. The connecting portion 1'' is also more conducive to carrier transportation. At the same time, the connecting portion 1'' is arranged below the source region, and the drain and / or the channel are filled with a first dielectric layer below, so that the parasitic capacitance of the drain and / or the channel, which is more likely to generate parasitic capacitance, can be reduced, and the heat on the suspension beam can be evacuated through the connecting portion. In addition, since only part or all of the drain and / or the channel need to be arranged on the suspension beam, this can reduce the size of the required suspension beam, so that the extended part of the suspension beam does not need to be too long. When it does not need to be too long, the suspension beam is not easy to collapse, thereby reducing the difficulty of the suspension beam manufacturing process.

[0053] In a specific embodiment, in order to further ensure the heat dissipation performance of the field effect transistor and the controllability requirements of the lateral etching process, as Figure 3 , Figure 4b , Figure 5c As shown, it is another example of partial suspension of the cantilever beam 1'. The cantilever beam 1' is arranged as a bridge across the first dielectric layer 5. Along the channel direction, the ends of the cantilever beam 1' are integrated with the substrate 1 through two connecting parts 1''. The formed field effect transistor cantilever beam 1' is supported by the first dielectric layer 5 and the connecting parts 1'' at both ends, and is more stable. The two connecting parts 1'' can prevent the cantilever beam 1' formed by lateral etching from collapsing before filling the first dielectric layer 5 due to various uncontrollable errors in the process, which can greatly reduce the process difficulty. Figure 4b and attached Figure 5c In the figure, it is shown that the source and drain are only partially located on the suspension beam 1'. Figure 2-3It is shown that the source, drain, gate, channel, etc. are all formed on the suspension beam. However, the embodiments of the present invention are not limited thereto. In actual settings, the proportion of the source, drain, and gate on the suspension beam can be reasonably arranged by designing the filling degree of the first dielectric layer to take into account the process and performance requirements of all parties.

[0054] In a specific embodiment, when the cantilever beam 1' is formed by side etching the silicon wafer, the cantilever beam 1' can be formed in the width direction of the channel (appearing Figure 2 Lateral etching is performed in the A-A' direction in the channel. Since the size of the cantilever beam in the channel width direction is much smaller than that in the length direction, it is preferred to perform lateral etching in the channel width direction to facilitate the controllability of the lateral etching process. On this basis, bidirectional simultaneous etching during lateral etching can further increase the lateral etching accuracy. In addition, for partially suspended cantilever beams, it is also possible to perform lateral etching in the channel length (attached Figure 2 The cantilever beam is formed by etching in the direction of B-B' in the figure. Since the entire area does not need to be etched through, it is beneficial to etch a space of a certain depth in the length direction of the channel only through the shallow trench isolation on one side while ensuring the controllable requirements of the lateral etching process. In addition, the grooves or through holes used for lateral etching to form the cantilever beam can be arranged in the width direction or the length direction of the channel.

[0055] The manufacturing process details of the field effect transistor provided by the present invention are described in detail below with reference to the accompanying drawings.

[0056] like Figure 6 FIG. 1 is a process flow chart of one embodiment of the method for manufacturing a field effect transistor provided by the present invention. It is a schematic diagram of the A-A' cross section based on the gate position. Figure 6 Figures (1)-(5) of FIG. 1 show part of the process of step S2, which includes the steps of: S21: Using a trench forming mask, a hard mask including a first through hole and a second through hole is prepared on the substrate. Figure 6 As shown in FIG. (1), a hard mask L2 is pre-formed on the substrate 1, and a trench forming mask L1 is formed on the hard mask L2. Figure 6 As shown in FIG. 2 , a first through hole H1 and a second through hole H2 are formed on a hard mask plate L2 using a trench forming mask L1 , and the surface of the silicon wafer is exposed through the first through hole H1 and the second through hole H2 .

[0057] S22: According to the positions of the first through hole and the second through hole, when etching downward, increase the lateral etching component to form the cantilever beam. Figure 6As shown in Figure (3), in the first through hole H1 and the second through hole H2, the exposed silicon wafer surface is tilted at a certain angle when etching downward, that is, the lateral etching component is increased to form a cantilever beam 1' on the silicon wafer, wherein the etching directions applied in the first through hole H1 and the second through hole H2 have an intersection below the cantilever beam 1', so the bottom of the cantilever beam 1' can be directly hollowed out by lateral etching.

[0058] In order to further improve the yield of the cantilever beam 1', the preferred step S2 specifically further includes the following steps: S23: performing epitaxial growth on the outer side of the cantilever beam to form an epitaxial growth layer. Figure 6 As shown in FIG. 4 , an epitaxial growth layer 11 is grown in the hollowed-out space using epitaxial growth technology.

[0059] S24: The epitaxial growth layer is self-alignedly etched using a hard mask template, and the remaining epitaxial growth layer on the cantilever beam is used to form a part of the cantilever beam. Specifically, the irregular part of the periphery of the epitaxial growth layer 11 can be removed using the pattern of the hard mask template L2, and the remaining part of the epitaxial growth layer 11 is used to form the cantilever beam 1', as shown in the attached figure. Figure 6 As shown in FIG. 5 , a regular cantilever beam 1 ′ is formed. By using this method, the size and shape of the cantilever beam can be easily controlled. The regular cantilever beam 1 ′ can improve the yield of semiconductor devices such as field effect transistors formed subsequently.

[0060] Attached Figure 6 Figures (6) to (9) of FIG. 1 show some of the process steps for forming a field effect transistor by combining a cantilever beam. Figure 6 Figure (6) shows step S3, in which the space below the suspension beam 1' is filled with a first dielectric layer 5, and the first dielectric layer 5 and the suspension beam 1' form a silicon-on-insulator structure. In order to complete step S4 to form a field effect transistor, preferably, step S4 also includes the step of forming a three-dimensional gate on the suspension beam 1': S41: Using a transistor forming region definition mask, and using a hard mask template for self-aligned etching, the first dielectric layer on both sides of the active area is etched open. Figure 6 As shown in FIG. 7 , the first dielectric layer 5 is cut open to expose the cantilever beam 1 ′.

[0061] S42: growing a gate oxide layer in a part of the cantilever beam. Figure 6 As shown in FIG. 8 , a gate oxide layer 6 is formed on the left and right sides and the top side of the suspension beam 1 ′. In order to form a three-dimensional gate, the gate oxide layer 6 is formed not only on the top side of the suspension beam, but also on the left and right side sides. Figure 6Figure (8) shows the required coverage position of the n-type gate. In addition, the three-dimensional gate can also be a ring gate, that is, in the circumferential direction of the suspension beam 1', the gate oxide layer 6 needs to surround the suspension beam 1', or the gate oxide layer 6 is formed not only on the top side of the suspension beam, but also on the left and right side surfaces and the bottom side surface.

[0062] S43: Fill polysilicon, use the gate to form a mask, and form a polysilicon gate on the gate oxide layer. Figure 6 As shown in FIG. 9 , an n-shaped three-dimensional gate 2 is formed on the gate oxide layer 6, that is, the gate 2 is formed not only on the top side of the suspension beam, but also on the left and right sides. When the ring gate is provided, the bottom side of the suspension beam needs to be wrapped (not shown in the figure).

[0063] In a specific embodiment, the gate formed in step S4 may also be a planar gate, and the steps of forming the planar gate on the suspension beam are: S41: growing a gate oxide layer on a part of the cantilever beam. Specifically, the hard mask L2 on the cantilever beam 1' is removed, and a gate oxide layer 6 is grown on the top side of the cantilever beam. The gate oxide layer 6 is only located on the top surface of the cantilever beam 1' (not shown in the drawings).

[0064] S42: Covering polysilicon, using the gate to form a mask, forming a polysilicon gate on the gate oxide layer. Specifically, growing the gate 2 on the gate oxide layer 6 on the top side of the suspension beam, the gate 2 is only located on the top surface of the suspension beam 1' (not shown in the figure).

[0065] like Figure 7 FIG. 1 is a process flow chart of another embodiment of a method for manufacturing a field effect transistor provided by the present invention. Figure 7 Figures (1)-(5) of FIG. 1 show part of the process of step S2, which is different from the following process. Figure 6 The corresponding process comprises the steps of: S21: A first trench and a second trench are pre-formed on the substrate. Specifically, a hard mask L2 is pre-formed on the substrate 1, and a trench forming mask L1 is formed on the hard mask L2. Figure 7 As shown in Figure (1), a first through hole H1 and a second through hole H2 are formed by etching in a substantially vertical direction on a hard mask template L2 using a groove forming mask L1, and the etching is further carried out into the silicon wafer, and a first groove and a second groove are formed in the substrate corresponding to the positions of the first through hole H1 and the second through hole H2.

[0066] S22: performing lateral etching so that the lower portion of the portion between the first groove and the second groove is at least partially etched away so that the upper portion is suspended to form a cantilever beam. Figure 7 As shown in Figures (3)-(4) in the figure, according to the positions of the first groove and the second groove, the substrate is etched laterally downward at a certain angle to form a cantilever beam 1'.

[0067] In a specific embodiment, after step 21 and before step 22, the method further includes the following steps: S2-1: Depositing a second dielectric layer in the first trench and the second trench on the substrate; see Attached Figure 7 As shown in FIG. 2 , a second dielectric layer L3 is deposited in the first trench and the second trench.

[0068] S2-2: Carve the second dielectric layer corresponding to the bottom of the first groove and the second groove, and continue to etch downward to a certain depth to reserve sufficient side etching space. Perform side etching at a certain angle to hollow out the part below the cantilever beam 1'. During side etching, the part of the cantilever beam covered by the second dielectric layer L3 can be protected to avoid etching, thereby forming a cantilever beam 1' of sufficient depth.

[0069] In a specific embodiment, step S2 specifically further includes the steps of: S23: baking the cantilever beam in a high-temperature hydrogen atmosphere. Figure 7 As shown in FIG. 4 , the etched surface of the cantilever beam 1′ formed by lateral etching is irregular. In order to improve the yield of the device and form a regular cantilever beam 1′, the cantilever beam is baked in a high-temperature hydrogen atmosphere (H2Bake), which can improve the tip of the cantilever beam 1′. Figure 7 As shown in FIG. 5 , after baking in a high-temperature hydrogen atmosphere, the bottom end of the cantilever beam 1 ′ becomes smooth and regular, which is beneficial to improving the yield of semiconductor devices such as field effect transistors formed thereon subsequently.

[0070] In a specific embodiment, the attached Figure 7 Figures (6)-(9) of FIG. 1 show some of the process steps for forming a field effect transistor by combining a cantilever beam. Figure 6 The above diagrams are similar to those in Figures (6)-(9) and will not be described again here.

[0071] In a specific embodiment, the field effect transistor further includes a sidewall. In order to complete step S4 to form the field effect transistor, preferably, step S4 further includes the steps of: S44: performing a sidewall spacer process on the polysilicon gate; the sidewall spacer of this embodiment can be manufactured by any conventional sidewall spacer process, and this embodiment is not limited thereto.

[0072] S45: performing source and drain ion doping on the two side regions of the gate to form a source electrode and a drain electrode. The source electrode and the drain electrode of this embodiment are applicable to any conventional source electrode and drain electrode manufacturing process, and this embodiment is not limited thereto.

[0073] In a specific embodiment, a fully depleted and / or partially depleted field effect transistor can be formed by controlling the thickness of the cantilever beam of any of the above embodiments.

[0074] In a second aspect, the present invention further provides a field effect transistor, which is formed by the method for forming a field effect transistor described in any of the above embodiments.

[0075] The field effect transistor and the method for forming the same according to the embodiment of the present invention have the following beneficial effects compared with the prior art: (1) A cantilever beam is directly formed on a silicon substrate by a lateral etching process, and a silicon-on-insulator (SOI) structure is formed by filling a dielectric layer in the space below the cantilever beam. This manufacturing method does not require the introduction of an additional substrate, avoids the use of expensive technologies such as oxygen ion implantation segmentation and silicon bonding, and reduces the manufacturing cost of field effect transistors. This manufacturing method also facilitates the compatibility of the manufacturing process of field effect transistors with other device processes on the chip, which can simplify the chip manufacturing process. The simplified manufacturing process can also further reduce costs. In addition, the setting of the dielectric layer filled below the cantilever beam can greatly reduce or even avoid the parasitic capacitance generated by the device above the cantilever beam, thereby greatly reducing power consumption.

[0076] (2) In some application scenarios, the gate of the embodiment of the present invention is preferably a three-dimensional field effect transistor in the form of a three-dimensional gate structure. The three-dimensional gate structure can provide a channel size that meets the performance requirements, which is conducive to circuit integration and is also conducive to the implementation of the process of "forming a cantilever directly on a silicon substrate by a lateral etching process, and forming a silicon-on-insulator (SOI) structure by filling a dielectric layer in the space below the cantilever" in the present invention. Because, in order to ensure process accuracy, the depth of the lateral etching process cannot be unlimited, and the area size of the channel of the three-dimensional gate can be made much smaller than that of the horizontal gate, which can ensure the controllability of the lateral etching process and improve the yield of the manufactured field effect transistor.

[0077] (3) In some application scenarios, since the drain or channel is the most likely region to generate parasitic capacitance, in an embodiment of the present invention, at least a portion of the drain and / or channel is formed on the cantilever beam. The dielectric layer filled under the cantilever beam can avoid a large amount of parasitic capacitance generated by the drain and / or channel, thereby greatly reducing power consumption.

[0078] (4) In some application scenarios, the cantilever beam is completely suspended, and the source, drain, gate and other structures are all located on the cantilever beam. The parasitic capacitance generated by the source, drain and gate can be reduced or avoided. By using a mask etching compatible with other processes to make a fully suspended cantilever beam, the cantilever beam is completely isolated and supported from the silicon substrate by a dielectric layer. The parasitic capacitance of the field effect transistor can be further reduced without increasing the manufacturing cost, thereby reducing the power consumption of the field effect transistor.

[0079] (5) In some application scenarios, the side surfaces of the source and / or drain on the cantilever beam are exposed to the shallow trench isolation, which can increase the contact area between the source and / or drain and the dielectric layer, further reduce the parasitic capacitance of the field effect transistor, and thus reduce the power consumption of the field effect transistor.

[0080] (6) In some application scenarios, the cantilever beam is partially suspended. Since the drain or channel area is most likely to generate parasitic capacitance, and the heat generated by the field effect transistor cannot be ignored, the embodiment of the present invention partially suspends the cantilever beam. For example, in one embodiment of the present invention, a portion of the drain and / or channel is formed on the cantilever beam, and the other portion is not arranged on the cantilever beam. The dielectric layer filled under the cantilever beam can avoid the large amount of parasitic capacitance generated by the drain and / or channel, thereby greatly reducing power consumption. At the same time, at least the portion corresponding to the source is connected to the silicon substrate body. Since the heat dissipation performance of the silicon substrate material is better than that of the dielectric layer, the large amount of heat generated by the field effect transistor on the cantilever beam can be easily diffused through the portion connected to the silicon substrate, taking into account the heat dissipation requirements of the field effect transistor and greatly reducing the probability of thermal damage to the field effect transistor.

[0081] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention.

[0082] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as examples and not limitations, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A method for manufacturing a field effect transistor, the method comprising the steps of: S1: providing a silicon wafer as a substrate; S2: forming a cantilever beam in the substrate by using a lateral etching process; S3: filling a first dielectric layer in the space below the cantilever beam, wherein the first dielectric layer and the cantilever beam form a silicon-on-insulator structure; S4: At least a portion of the drain and / or at least a portion of the channel of the field effect transistor are formed on the cantilever beam.

2. The method for forming a field effect transistor according to claim 1, characterized in that: The field effect transistor includes a gate, a source, and a drain, and the gate, the source, and the drain are all formed on the suspension beam.

3. The method for forming a field effect transistor according to claim 1, characterized in that: Only a drain and / or a portion of a channel of the field effect transistor is formed on the cantilever beam.

4. A method for forming a field effect transistor according to any one of claims 1 to 3, characterized in that: The cantilever beam is completely suspended relative to the substrate, and the cantilever beam is supported by the first dielectric layer.

5. A method for forming a field effect transistor according to any one of claims 1 to 3, characterized in that: The cantilever beam is partially suspended relative to the substrate, and the cantilever beam is supported by the connecting portion and / or the first dielectric layer. The connecting portion can also be used for heat dissipation and carrier transport.

6. The method for forming a field effect transistor according to claim 5, characterized in that: The field effect transistor comprises a source electrode, and the connecting portion is located in a region corresponding to a projection of the source electrode.

7. The method for forming a field effect transistor according to claim 5, characterized in that: The connecting parts are located at two end portions of the cantilever beam, and directions of the two end portions are located in the length direction of the channel of the field effect transistor.

8. The method for forming a field effect transistor according to claim 1, characterized in that: The transistor includes a gate, which is formed on the cantilever beam. The gate is formed to be located only at the top of the cantilever beam; or the gate is formed to be located not only at the top of the cantilever beam but also at both side surfaces of the cantilever beam; or the gate is formed to be located not only at the top of the cantilever beam but also at both side surfaces and the bottom outer surface of the cantilever beam.

9. The method for forming a field effect transistor according to claim 1, characterized in that: The step S2 specifically further comprises the steps of: S21: preparing a hard mask template including a first through hole and a second through hole on the substrate by using a groove forming mask; S22: Etching downwards according to the positions of the first through hole and the second through hole, and increasing the lateral etching component to form the cantilever beam.

10. The method for forming a field effect transistor according to claim 9, wherein step S2 further comprises the steps of: S23: performing epitaxial growth on the outer side of the cantilever beam to form an epitaxial growth layer; S24: performing self-aligned etching on the epitaxial growth layer using the hard mask template, and etching the remaining epitaxial growth layer to form a part of the cantilever beam.

11. The method for forming a field effect transistor according to claim 1, characterized in that: The step S2 specifically further comprises the steps of: S21: pre-forming a first groove and a second groove on the substrate; S22: Perform lateral etching so that the lower portion of the portion between the first groove and the second groove is at least partially etched away so that the upper portion is suspended to form a cantilever beam.

12. The method for forming a field effect transistor according to claim 9, characterized in that: The first trench and the second trench are arranged in a channel width direction or a length direction of the field effect transistor.

13. The method for forming a field effect transistor according to claim 9, characterized in that: The lateral etching is bidirectional etching performed simultaneously in the first trench and the second trench.

14. The method for forming a field effect transistor according to claim 9, characterized in that: The step 21 specifically further includes the steps of: S211: forming a hard mask on the substrate by using a groove forming mask; S212: Etching the substrate using the hard mask to form the first trench and the second trench of a certain depth.

15. The method for forming a field effect transistor according to claim 9, characterized in that: After step 21 and before step 22, the method further includes the following steps: S2-1: depositing a second dielectric layer in the first trench and the second trench on the substrate; S2-2: Carve the second dielectric layer corresponding to the bottom of the first groove and the second groove, and continue etching downward to a certain depth to reserve sufficient side etching space.

16. The method for forming a field effect transistor according to claim 9, characterized in that: The step S2 specifically further comprises the steps of: S23: baking the cantilever beam in a high-temperature hydrogen atmosphere.

17. The method for forming a field effect transistor according to claim 1, characterized in that: The step S4 further comprises the step of forming a planar gate on the cantilever beam: S41: growing a gate oxide layer in a partial area of ​​the cantilever beam; S42: Covering the polysilicon, using the gate to form a mask, and forming a polysilicon gate on the gate oxide layer.

18. The method for forming a field effect transistor according to claim 1, characterized in that: The step S4 further comprises the step of forming a three-dimensional gate on the suspension beam: S41: using a transistor forming region definition mask and using the hard mask for self-aligned etching to open the first dielectric layer on both sides of the active region; S42: growing a gate oxide layer in a partial area of ​​the cantilever beam; S43: filling polysilicon, using the gate to form a mask, and forming a polysilicon gate on the gate oxide layer.

19. A method for forming a field effect transistor according to claim 17 or 18, characterized in that: The step S4 further comprises the steps of: S44: performing a sidewall process on the polysilicon gate; S45: performing source-drain ion doping on the two side regions of the gate to form the source and drain.

20. The method for forming a field effect transistor according to any one of claim 1, characterized in that: Fully depleted and / or partially depleted field effect transistors are formed by different thicknesses of the cantilever beams.

21. A field effect transistor, characterized in that: It is formed by the method for forming a field effect transistor according to any one of claims 1 to 20.

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