Isolated switching converter and controller and control method thereof

Abstract

The invention discloses an isolated switching converter and a controller and a control method thereof. The switching converter comprises a transformer, a primary switching tube and a secondary synchronous switching tube, and the controller comprises an error amplifying circuit, a mode judging circuit and a grid driver. The error amplification circuit generates a compensation signal based on a difference between a feedback signal related to an output voltage of the switching converter and a reference voltage. The mode judgment circuit determines the driving mode of the gate driver based on the valley value of the voltage at the two ends of the secondary synchronous switch tube and the compensation signal. In the first driving mode, after current flowing through the secondary synchronous switch tube passes zero, the gate driver conducts the secondary synchronous switch tube for the second time; and in the second driving mode, the gate driver keeps the conduction state of the secondary synchronous switch tube, delays conduction of the secondary synchronous switch tube, and provides a primary conduction enable signal to control conduction of the primary switch tube when secondary conduction or delayed conduction of the secondary synchronous switch tube is finished.

Description

Technical Field

[0001] The invention relates to an electronic circuit, and in particular to an isolated switch converter with switching between a discontinuous current mode and a continuous current mode, a controller thereof and a control method thereof. Background Art

[0002] The secondary-side synchronous rectification solution usually refers to receiving the input voltage on the primary side of the transformer, and using a controllable switch tube instead of a diode on the secondary side of the transformer to convert the input voltage into the required output voltage. It is widely used because of its high conversion efficiency. When the isolated switching converter operates in the current discontinuous mode, it can achieve zero voltage conduction of the primary switch tube, thereby significantly reducing switching losses and improving working efficiency.

[0003] However, in situations where the load is large, such as when the paper rolling function of a printer is required, the isolated switching converter needs to operate in current continuous mode, and in this mode it is difficult for the primary switch tube to achieve zero voltage conduction. Summary of the invention

[0004] In view of one or more problems existing in the prior art, an object of the present invention is to provide a solution that can enable the primary switch tube of an isolated switching converter to achieve zero voltage conduction in both current continuous conduction mode and current discontinuous conduction mode, and the solution does not require any additional auxiliary switch.

[0005] According to an embodiment of the present invention, a controller for an isolated switching converter includes a transformer, a primary switch tube and a secondary synchronous switch tube. The controller includes: an error amplifier circuit, which generates a compensation signal based on a difference between a feedback signal related to an output voltage of the switching converter and a reference voltage; a mode judgment circuit, which provides a mode signal for determining a first drive mode or a second drive mode based on a valley value of a voltage across the secondary synchronous switch tube and the compensation signal, wherein the mode signal has a first level representing the first drive mode and a second level representing the second drive mode; and a gate driver, which provides a gate voltage to control the secondary synchronous switch tube, wherein when the gate driver operates in the first drive mode, after the current flowing through the secondary synchronous switch tube passes through zero, the secondary conduction A synchronous switch tube, and when the gate driver operates in the second driving mode, the conduction state of the secondary synchronous switch tube is maintained and the conduction of the secondary synchronous switch tube is delayed, and a primary turn-on enable signal is provided when the secondary synchronous switch tube is turned on for the second time or the delayed turn-on ends; an isolation circuit, having a first input terminal and a first output terminal, wherein the first input terminal receives the primary turn-on enable signal, and a first synchronization signal electrically isolated from the primary turn-on enable signal is provided at the first output terminal; a voltage zero-crossing detection circuit, detecting whether the voltage across the primary switch tube is zero-crossing, and providing a voltage zero-crossing detection signal; and a primary logic circuit, coupled to the first output terminal of the isolation circuit to receive the first synchronization signal, and providing a primary control signal based on the first synchronization signal and the voltage zero-crossing detection signal to control the primary switch tube.

[0006] An isolated switching converter according to an embodiment of the present invention includes: a transformer having a primary winding and a secondary winding; a primary switch tube coupled to the primary winding; a secondary synchronous switch tube coupled to the secondary winding; and the controller as described above.

[0007] According to an embodiment of the present invention, a control method for an isolated switching converter is provided. The switching converter includes a transformer having a primary winding and a secondary winding, a primary switch tube coupled to the primary winding, a secondary synchronous switch tube coupled to the secondary winding, and an isolation circuit. The control method includes: generating a compensation signal based on a difference between an output feedback signal representing an output signal of the switching converter and a reference voltage; providing a mode signal for determining a first driving mode or a second driving mode based on a valley value of a voltage across the secondary synchronous switch tube and the compensation signal; in response to the first driving mode, after a current flowing through the secondary synchronous switch tube passes through zero, the secondary synchronous switch tube is turned on for a second time; in response to the second driving mode, the on state of the secondary synchronous switch is maintained and the secondary synchronous switch tube is turned on with a delay; providing a primary turn-on enable signal when the secondary synchronous switch tube is turned on for a second time or the delayed turn-on ends; sending the primary turn-on enable signal to a first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the primary turn-on enable signal; detecting whether the voltage across the primary switch tube passes through zero and providing a voltage zero-crossing detection signal; and providing a primary control signal based on the first synchronization signal and the voltage zero-crossing detection signal.

[0008] In an embodiment of the present invention, the gate driver of the isolated switching converter can smoothly switch between the current continuous mode and the current discontinuous mode, providing power to the load while ensuring zero voltage conduction of the primary switch tube to reduce the loss of the converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a circuit block diagram of an isolated switching converter 100 according to an embodiment of the present invention;

[0010] Figure 2 is a circuit diagram of an error amplifier circuit 101 and a mode determination circuit 102 according to an embodiment of the present invention;

[0011] Figure 3 According to an embodiment of the present invention Figure 2 The working waveform of the circuit shown;

[0012] Figure 4 is a circuit diagram of a gate driver 103 according to an embodiment of the present invention;

[0013] Figure 5 is a working waveform diagram of the gate driver 103 according to an embodiment of the present invention;

[0014] Figure 6 is a working waveform diagram of the isolating switch converter 100 according to an embodiment of the present invention;

[0015] Figure 7 is a circuit schematic diagram of an isolated switching converter 100A according to yet another embodiment of the present invention;

[0016] Figure 8 A schematic diagram of a pulse signal generation principle according to an embodiment of the present invention;

[0017] Fig. 9 is a circuit schematic diagram of an isolated switching converter 100B according to yet another embodiment of the present invention;

[0018] Fig.10 According to an embodiment of the present invention Fig. 9 The operating waveform diagram of the isolated switching converter shown;

[0019] Fig.11 FIG. 2 is a flow chart of a control method 200 of an isolated switching converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be used to implement the present invention. In other examples, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0021] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. It should be understood that when an "element" is said to be "connected to" or "coupled" to another element, it may be directly connected or coupled to another element or there may be an intermediate element. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The same reference numerals indicate the same element. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0022] The present invention can be applied to any isolation converter. In the following detailed description, for the sake of brevity, only a flyback converter is used as an example to explain the specific working principle of the present invention.

[0023] Figure 1 FIG. 1 is a circuit block diagram of an isolated switching converter 100 according to an embodiment of the present invention. Figure 1 As shown, the isolated switching converter 100 includes a transformer T, a primary switch tube 10, a secondary synchronous switch tube 20, an error amplifier circuit 101, a mode judgment circuit 102, a gate driver 103, an isolation circuit 104, a voltage zero-crossing detection circuit 105, and a primary logic circuit 106. The transformer T has a primary winding, a secondary winding, and an auxiliary winding, wherein the primary winding, the secondary winding, and the auxiliary winding all have a first end and a second end, the first end of the primary winding receives an input voltage Vin, the first end of the secondary winding provides a DC output voltage Vo, and the second end is coupled to the secondary reference ground. The primary switch tube 10 is coupled between the second end of the primary winding and the primary reference ground. The secondary synchronous switch tube 20 is coupled between the second end of the secondary winding and the load. In some embodiments, the controller 30 and the secondary synchronous switch tube 20 are integrated in the same chip.

[0024] exist Figure 1 In the illustrated embodiment, the controller 30 of the isolated switching converter 100 operates in a current continuous conduction mode or a current discontinuous conduction mode. When the isolated switching converter 100 operates in the current discontinuous conduction mode, quasi-resonant control is adopted. When the current flowing through the energy storage element (transformer T) drops to zero, the parasitic capacitance of the energy storage element and the primary switch tube 10 begins to resonate, and a resonant voltage waveform is generated. After the current passes through zero, the secondary synchronous switch tube 20 is turned on for a second time for a conduction time, so that the primary switch tube 10 achieves zero voltage conduction, thereby reducing the switching loss and electromagnetic interference of the switching converter 100. When the isolated switching converter 100 operates in the current continuous conduction mode, the secondary synchronous switch tube 20 is delayed for a conduction time, which can also achieve zero voltage conduction of the primary switch tube 10 in some cases, and can output more power.

[0025] exist Figure 1 In the isolated switch converter 100 shown, the controller 30 has multiple pins, including an output feedback pin FB, a compensation pin COMP, a secondary reference ground SGND, a drain voltage detection pin SRD, a secondary drive pin SDrv, a voltage zero-crossing detection pin ZCD, a primary control pin PDrv and a primary reference ground PGND.

[0026] exist Figure 1In the illustrated embodiment, the error amplifier circuit 101 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the output feedback pin FB to receive an output feedback signal VFB related to the output signal (e.g., output voltage Vo) of the switching converter 100, the second input terminal receives a reference voltage VREF, and the output terminal is coupled to the compensation pin COMP. The error amplifier circuit 101 generates a compensation signal Vcomp at the output terminal based on the difference between the output feedback signal VFB and the reference voltage VREF.

[0027] The mode determination circuit 102 is coupled to the drain voltage detection pin SRD to receive the drain voltage V SRD , and is coupled to the output terminal of the error amplifier circuit 101 to receive the compensation signal Vcomp. In an embodiment of the present invention, the drain voltage VSRD of the secondary synchronous switch tube 20 can also represent the voltage across the secondary synchronous switch tube 20. Based on the valley value of the voltage across the secondary synchronous switch tube 20 and the compensation signal Vcomp, the mode determination circuit 102 provides a mode signal MD for determining the first driving mode or the second driving mode. The mode signal MD has a first level representing the first driving mode and a second level representing the second driving mode.

[0028] In one embodiment, when the valley value of the voltage across the secondary synchronous switch tube 20 is zero and the compensation signal Vcomp is greater than the first threshold value Vth1, the mode signal MD is switched from the first level to the second level. When the valley value of the voltage across the secondary synchronous switch tube 20 increases from 0 to 1, or the compensation signal is less than the second threshold value Vth2, the mode signal is switched from the second level to the first level, wherein the first threshold value Vth1 is greater than the second threshold value Vth2.

[0029] The gate driver 103 is configured to provide a gate voltage to control the secondary synchronous switch tube 20. The gate driver can smoothly switch between the first driving mode and the second driving mode. When the gate driver 103 operates in the first driving mode, the secondary synchronous switch tube 20 is turned on for the second time after the current flowing through the secondary synchronous switch tube 20 passes through zero; and when the gate driver 103 operates in the second driving mode, the secondary synchronous switch tube 20 is kept turned on and the secondary synchronous switch tube 20 is turned on with a delay, and a primary turn-on enable signal PRON is provided when the secondary synchronous switch tube 20 is turned on for the second time or the delayed turn-on ends.

[0030] The isolation circuit 104 has a first channel for transmitting the primary enable signal PRON. The isolation circuit 104 has a first input terminal and a second output terminal, wherein the first input terminal receives the primary enable signal PRON, and the first output terminal provides a first synchronization signal SYNC1 electrically isolated from the primary enable signal PRON.

[0031] The voltage zero-crossing detection circuit 105 is used to detect whether the voltage across the primary switch tube 10 crosses zero. Figure 1 In the illustrated embodiment, the isolated switching converter 100 further includes an auxiliary winding located on the primary side, which is coupled to the voltage zero crossing detection pin ZCD of the controller 30 via a resistor voltage divider circuit. The voltage zero crossing detection circuit 105 is coupled to the voltage zero crossing detection pin ZCD to receive the voltage zero crossing detection voltage VZCD. The voltage zero crossing detection circuit 105 compares the voltage zero crossing detection voltage VZCD with the zero crossing threshold voltage VZCD_TH, and outputs a voltage zero crossing detection signal ZCDS at the output terminal. In other embodiments, the voltage zero crossing detection circuit 105 may have other suitable circuit structures.

[0032] The primary logic circuit 106 is coupled to the first output terminal of the isolation circuit 104 to receive the first synchronization signal SYNC1 , and provides a primary control signal CTRLP to the primary control pin PDrv based on the first synchronization signal SYNC1 and the voltage zero-crossing detection signal ZCDS to control the primary switch tube 10 .

[0033] Figure 2 FIG. 1 is a circuit diagram of an error amplifier circuit 101 and a mode determination circuit 102 according to an embodiment of the present invention. Figure 2 In the embodiment shown, the error amplifier circuit 101 includes an error amplifier EA having a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the inverting input terminal receives an output feedback signal VFB, the non-inverting input terminal receives a reference voltage VREF, and the output terminal provides a compensation signal Vcomp.

[0034] like Figure 2 As shown, the mode judgment circuit 102 includes a first comparator COM1, a second comparator COM2, an AND gate circuit AND1, an OR gate circuit OR1 and a trigger FF1. Wherein ZVS1 indicates that the voltage valley value across the secondary synchronous switch tube 20 is 1, and ZVS0 indicates that the voltage valley value across the secondary synchronous switch tube 20 is 0. When the compensation signal Vcomp is greater than the first threshold Vth1 and the valley value of the voltage across the secondary synchronous switch tube is zero, the mode signal MD has a second level, and the gate driver 103 operates in the second driving mode. When the compensation signal Vcomp is less than the second threshold Vth2, or the valley value of the voltage across the secondary synchronous switch tube is 1, the mode signal MD has a first level, and the gate driver 103 operates in the first driving mode.

[0035] Figure 3 According to an embodiment of the present invention Figure 2 The working waveform diagram of the circuit shown in FIG. ZVS1 indicates that the voltage valley value across the secondary synchronous switch tube 20 is 1, and ZVS0 indicates that the voltage valley value across the secondary synchronous switch tube 20 is 0. Figure 3The voltage V across the secondary synchronous switch 20 is shown respectively. SRD and the waveform of the compensation signal Vcomp. When viewed from left to right, when the voltage valley value changes from ZVS1 to ZVS0 and the compensation signal Vcomp increases to the first threshold value Vth1, the mode signal MD changes from the first level to the second level, and the gate driver 103 switches to the second driving mode. When the voltage valley value changes from ZVS1 to ZVS0, or the compensation signal Vcomp decreases to the second threshold value Vth2, the mode signal MD changes from the second level to the first level, and the gate driver 103 switches to the first driving mode.

[0036] Figure 4 FIG. 1 is a circuit diagram of a gate driver 103 according to an embodiment of the present invention. Figure 4 In the illustrated implementation, the gate driver 103 includes a primary turn-off detection circuit 301 , a gate voltage adjustment circuit 302 , a conduction control circuit 303 , a conduction time adjustment circuit 304 , a current zero-crossing detection circuit 305 , a secondary logic circuit 306 , a drive circuit DRV and a discharge switch tube 1033 .

[0037] The primary shutdown detection circuit 301 is used to detect whether the primary switch tube 10 is turned off and generate a primary shutdown detection signal SR_ON. When it is detected that the primary switch tube 10 is turned off, the secondary synchronous switch tube 20 is turned on. Figure 4 In the embodiment shown, the primary shutdown detection circuit 301 is based on the drain voltage V SRD The primary shutdown detection circuit 301 includes a comparator COM3, whose inverting input terminal receives the drain voltage V of the secondary synchronous switch tube 20. SRD , the non-inverting input receives the turn-on threshold voltage V TH_ON , providing a primary shutdown detection signal SR_ON at the output end to turn on the secondary synchronous switch tube 20 when detecting that the primary switch tube 10 is turned off. In other embodiments, the primary shutdown detection circuit 301 determines whether the primary switch tube 10 is turned off based on electrical parameters such as the current flowing through the secondary synchronous switch tube 20 and the voltage across the secondary winding. The primary shutdown detection circuit 301 can also obtain a signal indicating whether the primary switch tube 10 is turned off from the primary side in other ways.

[0038] The gate voltage regulating circuit 302 is used to pull down the gate voltage VG of the secondary synchronous switch tube 20 in the first driving mode or the second driving stage of the second driving mode to increase its on-resistance. Figure 4 In the embodiment shown, the gate voltage regulating circuit 302 includes an amplifier AMP, whose inverting input terminal receives the drain voltage V of the secondary synchronous switch tube 20. SRD , the non-inverting input receives the regulation threshold V TH_REG, providing a gate voltage adjustment signal SR_REG at the output end.

[0039] The conduction control circuit 303 is used to control the secondary conduction or delayed conduction of the secondary synchronous switch tube 20 and provide a conduction control signal ZON. Figure 4 In the illustrated embodiment, the conduction control circuit 303 includes a timing circuit 1031, an AND gate circuit AND2, and an OR gate circuit OR2. The timing circuit 1031 is used to provide a preset duration TS. The AND gate circuit AND2 has a first input terminal coupled to the timing circuit 1031 and a second input terminal coupled to the mode judgment circuit 102, and provides a delayed conduction control signal ZON1 at the output terminal. When the timing duration of the timing circuit 1031 reaches the preset duration TS and the current of the secondary synchronous switch tube 20 has not yet passed zero, the delayed conduction control signal ZON1 is valid, and the secondary synchronous switch tube 20 is delayed to be turned on. In one embodiment, the conduction control circuit 303 further includes a quasi-resonant control circuit. The quasi-resonant control circuit is coupled to the secondary synchronous switch tube 20 to detect the resonant voltage of the switching converter, and generates a secondary conduction control signal ZON2 at the target valley of the resonant voltage. When the valley value at both ends of the secondary synchronous switch tube 20 reaches its target locked valley value, the secondary conduction control signal ZON2 is valid, and the secondary synchronous switch tube 20 is turned on for the second time. The OR gate circuit OR2 receives the delayed conduction control signal ZON1 and the secondary conduction control signal ZON2, and provides a conduction control signal ZON at the output terminal. Figure 4 In the illustrated embodiment, when the delayed on-control signal ZON1 is valid or the secondary on-control signal ZON2 is valid, the on-control signal ZON is valid.

[0040] The on-time adjustment circuit 304 receives the on-time control signal ZON and adjusts the on-time adjustment circuit 304 based on the drain voltage V SRD , the output voltage Vo of the switching converter and the resistance value of the resistor to adjust the conduction time of the delayed conduction or the secondary conduction, and provide a shutdown control signal ZOFF at the output end. The current zero-crossing detection circuit 305 detects whether the current flowing through the secondary synchronous switch tube 20 is zero-crossing, and provides a current zero-crossing detection signal ZCD0. Figure 4 In the illustrated embodiment, the current zero-crossing detection circuit 305 includes a comparator COM4, ​​whose inverting input terminal receives a threshold voltage VTH4, and whose non-inverting input terminal receives a current detection signal ISENS, wherein the current detection signal ISENS represents the current flowing through the secondary synchronous switch tube 20, and provides a current zero-crossing detection signal ZCD0 at the output terminal.

[0041] The secondary logic circuit 306 controls the on and off of the secondary synchronous switch tube 20 based on the primary off detection signal SR_ON, the on control signal ZON, the current zero-crossing detection signal ZCD0 and the off control signal ZOFF. Figure 4 In the embodiment shown, the secondary logic circuit 306 includes OR gate circuits OR3 and OR4 and a trigger FF2. When the primary shutdown detection signal SR_ON is valid, the secondary synchronous switch tube 20 is turned on, and the secondary synchronous switch tube drain voltage V SRD Increase to the regulation threshold V TH_REG When the on-state control signal ZON is valid, the secondary synchronous switch tube 20 is turned on twice or delayed, depending on the driving mode of the gate driver. When the off-state control signal ZOFF or the current zero-crossing detection signal ZCD0 is valid, the discharge switch tube 1033 is turned on, and the gate voltage VG of the secondary synchronous switch tube 20 is pulled down to zero, and the secondary synchronous switch tube 20 is turned off. And when the secondary synchronous switch tube 20 is turned on twice or delayed, the primary turn-on enable signal PRON is provided.

[0042] Figure 5 1 is a working waveform diagram of the gate driver 103 according to an embodiment of the present invention. Figure 5 As shown, before time t6, the gate driver 103 operates in the first driving mode, and after time t6, the gate driver 103A operates in the second driving mode.

[0043] Specifically, when the gate driver 103 operates in the first driving mode, in the first driving stage (t1-t2), the gate driver 103 controls the gate voltage VG of the secondary synchronous switch tube 20 to maintain the maximum value to keep the secondary synchronous switch tube 20 with the minimum on-resistance. In the second driving stage (t2-t3), the gate voltage VG of the secondary synchronous switch tube 20 is pulled down to increase the on-resistance of the secondary synchronous switch tube 20. In the third driving stage (t3-t4), the gate voltage VG of the secondary synchronous switch tube 20 is zero. In the fourth driving stage (t4-t5), the secondary synchronous switch tube reaches the target valuation when the valley value of the voltage across its two ends is 1, the secondary switch tube 20 is turned on for the second time, and the gate voltage VG of the secondary synchronous switch tube is pulled up to the maximum value. The duration of the fourth driving stage is controlled by the on-time adjustment circuit 304.

[0044] When the gate driver 103 works in the second driving mode, in the first driving stage (t7-t8), the gate driver 103 controls the gate voltage VG of the secondary synchronous switch tube 20 to maintain the maximum value to keep the secondary synchronous switch tube 20 with the minimum on-resistance. In the second driving stage (t8-t9), the gate voltage VG of the secondary synchronous switch tube 20 is pulled down to increase the on-resistance of the secondary synchronous switch tube. In the third driving stage (t9-t10), when the timing duration of the timing circuit 1031 reaches the preset duration TS, the secondary switch tube 20 is delayed to turn on, and the gate voltage VG of the secondary synchronous switch tube is pulled up to the maximum value. The duration of the third driving stage in the second driving mode is controlled by the on-time adjustment circuit 304.

[0045] In addition, when the secondary synchronous switch tube 20 is turned on for the second time or the delayed turn-on ends, a primary turn-on enable signal PRON is provided.

[0046] Figure 6 FIG. 1 is a working waveform diagram of the isolating switch converter 100 according to an embodiment of the present invention. Figure 6 As shown, when the secondary conduction or delayed conduction of the secondary synchronous switch tube 20 ends, the primary turn-on enable signal PRON is provided. When the rising edge of the primary turn-on enable signal PRON comes, almost at the same time, the isolation circuit 104 provides the first synchronous signal SYNC1 electrically isolated from the primary turn-on enable signal PRON at the first output terminal. For example, at time t A , the first synchronization signal SYNC1 becomes high level. At time t B , the voltage zero-crossing detection circuit 105 detects that the voltage VZCD on the auxiliary winding crosses zero. After a time delay, at time t C , the primary control signal CTRLP becomes high level, and the primary switch tube 10 is turned on by zero voltage.

[0047] Figure 7 FIG. 1 is a circuit diagram of an isolated switching converter 100A according to another embodiment of the present invention. Figure 1 Compared with the isolated switching converter 100 shown in FIG. Figure 7 The isolated switching converter 100A shown in the figure further includes a pulse signal generating circuit 107, a threshold generating circuit 108 and a second comparing circuit 109. The relevant operating waveforms are shown in FIG. Figure 8 shown.

[0048] exist Figure 7 In the embodiment shown, when the primary turn-on enable signal PRON is valid, the pulse signal generating circuit 107 generates a ramp signal RAMP which starts to rise from zero with a preset slope until it increases to the difference between the second reference voltage VREF2 and the compensation signal Vcomp, and then provides a pulse signal PL, such as Figure 8 shown. Figure 8 FIG. 4 is a schematic diagram of a pulse signal generation principle according to an embodiment of the present invention.

[0049] like Figure 7 As shown, the isolation circuit 104A transmits a second channel of the pulse signal PL. The isolation circuit 104A has a second input terminal and a second output terminal, wherein the second input terminal receives the pulse signal PL, and provides a second synchronization signal SYNC2 electrically isolated from the pulse signal PL at the second output terminal. The threshold generation circuit 108 is coupled to the second output terminal of the isolation circuit 104A to receive the second synchronization signal SYNC2, and based on the second synchronization signal SYNC2, provides a current threshold voltage VTH to control the current peak value flowing through the primary switch tube 10. The second comparison circuit 109 compares the current detection signal representing the current flowing through the primary switch tube with the current threshold voltage VTH, and generates a second comparison signal at the output terminal. The primary logic circuit 106A controls the shutdown of the primary switch tube 10 based on the second comparison signal.

[0050] Fig. 9 FIG. 1 is a circuit diagram of an isolated switching converter 100B according to another embodiment of the present invention. Figure 7 Compared to the embodiment shown, Fig. 9 The isolated switching converter 100B shown further includes a primary turn-on window setting circuit 110 .

[0051] The primary opening window setting circuit 110 is coupled to the first output terminal of the isolation circuit 104A to receive the first synchronization signal SYNC1 and sets an observation window t based on the first synchronization signal SYNC1. ZCD-VW The primary logic circuit 106A is based on the observation window t ZCD-VW , the voltage zero crossing detection signal ZCDS and the second comparison signal generate the primary control signal CTRLP. After the voltage across the primary switch tube is detected to be zero, that is, when the voltage zero crossing detection signal ZCDS is valid, a time delay t is provided. Delay If the delay time t Delay The end point of the observation window t ZCD-VW If the delay end point is within the observation window t ZCD-VW In addition, the primary switch tube 10 is turned on at the end point of the observation window.

[0052] Fig.10 According to an embodiment of the present invention Fig. 9 The operating waveform diagram of the isolated switching converter 100B is shown in FIG. Fig.10 As shown, at time ta, the voltage across the primary switch tube passes zero, and the voltage zero-crossing detection signal ZCDS is valid. Delay - Delay time t Delay After that, it reaches time tb. Since the delay end point tb is located in the observation window tZCD-VW The primary switch tube 10 is turned on at tb. Fig.10 As shown, at time tc, when the observation window t ZCD-VW When the end point of the delay is reached, the end point of the delay has not yet arrived, and the primary switch tube 10 is in the observation window t ZCD-VW At time td, since the voltage has not yet been detected to cross the zero point, the primary switch tube 10 is also in the observation window t ZCD-VW The end point of conduction.

[0053] Fig.11 The method flow chart of the control method 200 of the isolated switching converter according to an embodiment of the present invention is shown. The isolated switching converter includes a transformer having a primary winding and a secondary winding, a primary switch tube coupled to the primary winding, a secondary synchronous switch tube coupled to the secondary winding, and an isolation circuit. The control method includes steps 201 to 208.

[0054] In step 201 , a compensation signal is generated based on a difference between an output feedback signal representing an output signal of a switching converter and a reference voltage.

[0055] In step 202 , a mode signal for determining a first driving mode or a second driving mode is provided based on a valley value of a voltage across the secondary synchronous switch tube and a compensation signal.

[0056] In one embodiment, when the valley value of the voltage across the secondary synchronous switch tube is zero and the compensation signal is greater than a first threshold, the mode signal is switched from a first level to a second level; when the valley value of the voltage across the secondary synchronous switch tube increases from 0 to 1 or the compensation signal is less than the second threshold, the mode signal is switched from the second level to the first level, wherein the first threshold is greater than the second threshold.

[0057] In step 203, in response to the first driving mode, after the current flowing through the secondary synchronous switch tube passes through zero, the secondary synchronous switch tube is turned on for the second time. In the first driving mode: in the first driving stage, the gate voltage of the secondary synchronous switch tube is controlled to maintain a maximum value; in the second driving stage, the gate voltage of the secondary synchronous switch tube is pulled down; in the third driving stage, the gate voltage of the secondary synchronous switch tube is zero; and in the fourth driving stage, the secondary synchronous switch tube is turned on for the second time, and the gate voltage of the secondary synchronous switch tube is pulled up to the maximum value.

[0058] In step 204, in response to the second driving mode, the conduction state of the secondary synchronous switch tube is maintained and the secondary synchronous switch tube is turned on with a delay. In the second driving mode: in the first driving stage, the gate voltage of the secondary synchronous switch tube is controlled to maintain a maximum value; in the second driving stage, the gate voltage of the secondary synchronous switch tube is pulled down; and in the third driving stage, the secondary synchronous switch tube is turned on with a delay, and the gate voltage of the secondary synchronous switch tube is pulled up to a maximum value.

[0059] In step 205, when the secondary synchronous switch tube is turned on for the second time or the delayed turn-on ends, a primary turn-on enable signal is provided.

[0060] In step 206, the primary turn-on enable signal is sent to the first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the primary turn-on enable signal.

[0061] In step 207, it is detected whether the voltage across the primary switch tube passes through zero, and a voltage zero-crossing detection signal is provided.

[0062] In step 208 , a primary control signal is provided based on the first synchronization signal and the voltage zero-crossing detection signal to control the primary switch tube.

[0063] In one embodiment, the control method 200 further includes: starting timing when it is detected that the voltage valley value across the secondary synchronous switch tube is zero or the secondary synchronous switch tube is delayed to turn on, and when the timing time reaches a preset time and the current of the secondary synchronous switch tube has not passed zero, the secondary synchronous switch tube is delayed to turn on.

[0064] In another embodiment, the control method 200 further includes: setting an observation window based on the first synchronization signal; providing a time delay after detecting that the voltage across the primary switch tube passes through zero; if the end point of the time delay is within the observation window, turning on the primary switch tube at the end point of the time delay; and if the end point of the time delay is outside the observation window, turning on the primary switch tube at the end point of the observation window.

[0065] In one embodiment, a method for generating a current threshold voltage is also included, and the current threshold is used to control the peak value of the current flowing through the primary switch tube. The method includes: when the primary turn-on enable signal is valid, a ramp signal rises from zero at a preset slope; when the ramp signal increases to the difference between the second reference voltage and the compensation signal, a pulse signal is provided; the pulse signal is sent to the second channel of the isolation circuit, and a second synchronization signal electrically isolated from the pulse signal is provided; and based on the second synchronization signal, a current threshold voltage is provided.

[0066] In the specification, relative terms such as first and second, etc. may be used only to distinguish one entity or action from another entity or action, and do not necessarily or imply any entity such relationship or order between these entities or actions. Numerical sequences such as "first", "second", "third", etc. only refer to different individuals in a plurality, and do not imply any order or sequence, unless specifically defined by the claim language. The order of the text in any claim does not mean that the processing steps must be performed in a temporary or logical order according to such order, unless specifically provided by the claim language. Without departing from the scope of the present invention, these processing steps can be interchanged in any order, as long as such interchange does not contradict the claim language and does not appear logically absurd.

[0067] The above description and implementation are merely exemplary and are not intended to limit the scope of the present invention. It is possible to make changes and modifications to the disclosed embodiments, and other feasible optional embodiments and equivalent changes to the elements in the embodiments can be understood by those of ordinary skill in the art. Other changes and modifications to the embodiments disclosed by the present invention do not exceed the spirit and scope of protection of the present invention.

Claims

1. A controller for an isolated switching converter, the switching converter comprising a transformer, a primary switch tube and a secondary synchronous switch tube, the controller comprising: an error amplifier circuit, generating a compensation signal based on a difference between a feedback signal related to an output voltage of the switching converter and a reference voltage; A mode determination circuit provides a mode signal for determining a first driving mode or a second driving mode based on a valley value of a voltage across the secondary synchronous switch tube and a compensation signal, wherein the mode signal has a first level representing the first driving mode and a second level representing the second driving mode; A gate driver, providing a gate voltage to control the secondary synchronous switch tube, wherein when the gate driver operates in a first driving mode, after the current flowing through the secondary synchronous switch tube passes through zero, the secondary synchronous switch tube is turned on for the second time, and when the gate driver operates in a second driving mode, the secondary synchronous switch tube is kept turned on in a turned-on state and the secondary synchronous switch tube is turned on with a delay, and a primary turn-on enable signal is provided when the secondary synchronous switch tube is turned on for the second time or the delayed turn-on ends; An isolation circuit having a first input terminal and a first output terminal, wherein the first input terminal receives a primary turn-on enable signal, and provides a first synchronization signal electrically isolated from the primary turn-on enable signal at a first output terminal; The voltage zero-crossing detection circuit detects whether the voltage at both ends of the primary switch tube is zero-crossing and provides a voltage zero-crossing detection signal; as well as The primary logic circuit is coupled to the first output terminal of the isolation circuit to receive the first synchronization signal, and provides a primary control signal based on the first synchronization signal and the voltage zero-crossing detection signal to control the primary switch tube.

2. A controller as described in claim 1, wherein when the valley value of the voltage across the secondary synchronous switch tube is zero and the compensation signal is greater than a first threshold, the mode signal is switched from the first level to the second level, and when the valley value of the voltage across the secondary synchronous switch tube increases from 0 to 1 or the compensation signal is less than the second threshold, the mode signal is switched from the second level to the first level, wherein the first threshold is greater than the second threshold.

3. The controller as claimed in claim 1, wherein when the gate driver operates in the first driving mode: In the first driving stage, the gate voltage of the secondary synchronous switch tube is controlled to maintain a maximum value so as to maintain the secondary synchronous switch tube with a minimum on-resistance; In the second driving stage, the gate voltage of the secondary synchronous switch tube is pulled down to increase the on-resistance of the secondary synchronous switch tube; In the third driving stage, the gate voltage of the secondary synchronous switch tube is zero; and In the fourth driving stage, the secondary synchronous switch tube is turned on for the second time, and the gate voltage of the secondary synchronous switch tube is pulled up to the maximum value.

4. The controller as claimed in claim 1, wherein when the gate driver operates in the second driving mode: In the first driving stage, the gate voltage of the secondary synchronous switch tube is controlled to maintain a maximum value so as to maintain the secondary synchronous switch tube with a minimum on-resistance; In the second driving stage, the gate voltage of the secondary synchronous switch tube is pulled down to increase the on-resistance of the secondary synchronous switch tube; as well as In the third driving stage, the secondary synchronous switch tube is turned on with a delay, and the gate voltage of the secondary synchronous switch tube is pulled up to a maximum value.

5. The controller of claim 1 , wherein the gate driver comprises: The timing circuit starts timing when it detects that the valley value of the voltage across the secondary synchronous switch tube is zero or the secondary synchronous switch tube is delayed in turning on. When the timing time reaches a preset time and the current of the secondary synchronous switch tube has not passed zero, the secondary synchronous switch tube is delayed in turning on.

6. The controller of claim 1, further comprising: A primary opening window setting circuit is coupled to the first output terminal of the isolation circuit to receive the first synchronization signal and sets the observation window based on the first synchronization signal; A second comparison circuit compares a primary current detection signal representing a current flowing through the primary switch tube with a current threshold voltage, and generates a second comparison signal at an output end; as well as The primary logic circuit generates the primary control signal based on the observation window, the voltage zero-crossing detection signal and the second comparison signal.

7. The controller of claim 6, further comprising: A pulse signal generating circuit, when the primary opening enable signal is valid, a ramp signal starts to rise from zero at a preset slope until it increases to the difference between the second reference voltage and the compensation signal, and then provides a pulse signal; The isolation circuit also has a second input terminal and a second output terminal, wherein the second input terminal receives the pulse signal and provides a second synchronization signal electrically isolated from the pulse signal at the second output terminal; as well as The threshold generating circuit is coupled to the second output terminal of the isolation circuit to receive the second synchronization signal, and provides a current threshold voltage based on the second synchronization signal.

8. An isolated switching converter, comprising: a transformer having a primary winding and a secondary winding; A primary switch tube coupled to the primary winding; A secondary synchronous switch tube is coupled to the secondary winding; as well as A controller as claimed in any one of claims 1 to 7.

9. A control method for an isolated switching converter, the switching converter comprising a transformer having a primary winding and a secondary winding, a primary switch tube coupled to the primary winding, a secondary synchronous switch tube coupled to the secondary winding, and an isolation circuit, the control method comprising: generating a compensation signal based on a difference between an output feedback signal representing an output signal of the switching converter and a reference voltage; Based on the valley value of the voltage across the secondary synchronous switch tube and the compensation signal, providing a mode signal for determining the first driving mode or the second driving mode; In response to the first driving mode, after the current flowing through the secondary synchronous switch tube passes through zero, the secondary synchronous switch tube is turned on for the second time; In response to the second driving mode, maintaining the conduction state of the secondary synchronous switch tube and delaying the conduction of the secondary synchronous switch tube; When the secondary synchronous switch tube is turned on for the second time or the delayed turn-on ends, a primary turn-on enable signal is provided; Sending the primary opening enable signal to the first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the primary opening enable signal; Detect whether the voltage across the primary switch tube is zero-crossing and provide a voltage zero-crossing detection signal; as well as A primary control signal is provided based on the first synchronization signal and the voltage zero-crossing detection signal to control the primary switch tube.

10. The control method according to claim 9, wherein: When the valley value of the voltage across the secondary synchronous switch tube is zero and the compensation signal is greater than the first threshold, the mode signal is switched from the first level to the second level. When the valley value of the voltage across the secondary synchronous switch tube increases from 0 to 1 or the compensation signal is less than the second threshold, the mode signal is switched from the second level to the first level, wherein the first threshold is greater than the second threshold.

11. The control method according to claim 9, further comprising: The timing starts when it is detected that the valley value of the voltage across the secondary synchronous switch tube is zero or the secondary synchronous switch tube is delayed to turn on. When the timing time reaches a preset time and the current of the secondary synchronous switch tube has not passed zero, the secondary synchronous switch tube is delayed to turn on.

12. The control method according to claim 9, wherein in the first driving mode: In the first driving stage, the gate voltage of the secondary synchronous switch tube is controlled to maintain a maximum value; In the second driving stage, the gate voltage of the secondary synchronous switch is pulled down; In the third driving stage, the gate voltage of the secondary synchronous switch tube is zero; and In the fourth driving stage, the secondary synchronous switch tube is turned on for the second time, and the gate voltage is pulled up to the maximum value.

13. The control method according to claim 9, in the second driving mode: In the first driving stage, the gate voltage of the secondary synchronous switch tube is controlled to maintain a maximum value; In the second driving stage, the gate voltage of the secondary synchronous switch is pulled low; and In the third driving stage, the secondary synchronous switch is turned on with a delay, and the gate voltage is pulled up to the maximum value.

14. The control method according to claim 9, further comprising Setting an observation window based on the first synchronization signal; After detecting that the voltage across the primary switch tube passes zero, a time delay is provided; If the time delay end point is within the observation window, turning on the primary switch tube at the time delay end point; and If the end point of the time delay is outside the observation window, the primary switch tube is turned on at the end point of the primary turn-on observation window.

15. The control method according to claim 9, further comprising When the primary opening enable signal is valid, a ramp signal starts to rise from zero at a preset slope; When the ramp signal increases to a difference between the second reference voltage and the compensation signal, a pulse signal is provided; Sending the pulse signal to the second channel of the isolation circuit to provide a second synchronization signal electrically isolated from the pulse signal; as well as Based on the second synchronization signal, a current threshold voltage for controlling the peak value of the current flowing through the primary switch tube is provided.

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