SiC device four-level split inverter low switching loss modulation method and system

Abstract

The invention belongs to the technical field of power electronics, and relates to a low switching loss modulation method and system for a four-level split inverter of a SiC device, and the method comprises the steps: generating a superposed signal according to an i-phase original sinusoidal modulation wave and a three-phase original sinusoidal modulation wave, and obtaining an i-phase final modulation wave; obtaining an i-phase lower modulation wave, an i-phase upper modulation wave and an i-phase intermediate modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage; generating an i-phase driving signal Si1 and an i-phase driving signal Si2 according to the set sizes of the upper-layer laminated carrier wave and the i-phase upper modulation wave, generating an i-phase driving signal Si3 and an i-phase driving signal Si4 according to the set sizes of the middle-layer laminated carrier wave and the i-phase middle modulation wave, and generating an i-phase driving signal Si5 and an i-phase driving signal Si6 according to the set sizes of the lower-layer laminated carrier wave and the i-phase lower modulation wave. The direct-current bus capacitor voltage sharing can be realized, the switching frequency is reduced, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics and relates to inverter modulation technology, and in particular to a low switching loss modulation method and system for a SiC device four-level split inverter. Background Art

[0002] Inverters are key equipment in power electronic systems such as renewable energy power generation and electric traction. Compared with traditional two-level inverters, four-level inverters have more output levels, which can reduce the voltage stress of power switching devices and help reduce output current harmonics. Traditional four-level inverters use silicon (Si) power switching devices, which have low switching losses and relatively slow switching speeds, limiting the performance of four-level inverters. Silicon carbide metal oxide semiconductor field effect transistors (hereinafter referred to as SiC MOSFETs) are a new type of power semiconductor switching device with the advantages of low switching losses and fast switching speeds. Applying SiC MOSFETs to a high-reliability four-level split inverter can further increase its switching frequency, control accuracy, and response speed.

[0003] However, the SiC device four-level split inverter has the following problems. First, if the SiC device four-level split inverter adopts the traditional modulation strategy, the capacitor voltage of the DC bus cannot be balanced, and the intermediate capacitor voltage of the DC bus will gradually decay to 0V during operation, resulting in an increase in output current harmonics. Second, if the SiC device four-level split inverter adopts the traditional modulation strategy, the SiC MOSFET switches many times in one fundamental cycle, resulting in large switching losses, which reduces the inverter efficiency and increases the heat generated by the SiC MOSFET. Summary of the invention

[0004] In view of the above-mentioned problems of large switching loss in the prior art, the present invention provides a low switching loss modulation method and system for a SiC device four-level split inverter, which can achieve voltage balancing of the DC bus capacitor voltage and reduce output current harmonics, thereby outputting a good current waveform and improving current quality. At the same time, it can reduce the switching times of the SiC device, reduce switching losses, and improve the efficiency of the SiC device four-level split inverter.

[0005] In a first aspect, the present invention provides a low switching loss modulation method for a SiC device four-level split inverter, the specific steps of which are: Superposition signal generation step: generating a superposition signal according to the three-phase original sinusoidal modulation wave; Modulation wave generation steps: obtain the final modulation wave of phase i according to the original sinusoidal modulation wave of phase i and the superimposed signal, i=A, B, C; Three modulation wave generation steps: according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the DC bus voltage, obtain the lower modulation wave of phase i and the upper modulation wave of phase i; according to the final modulation wave of phase i, the DC bus voltage and the DC bus intermediate capacitor voltage, obtain the intermediate modulation wave of phase i; Driving signal generation step: Generate the i-phase driving signal S according to the size of the upper layer stacked carrier and the i-phase modulation wave i1 and i-phase drive signal S i2 , according to the size of the set middle layer stacked carrier and the i phase intermediate modulation wave, the i phase drive signal S is generated i3 and i-phase drive signal S i4 , according to the setting of the lower layer stacked carrier and the size of the i-phase down modulation wave, the i-phase drive signal S is generated. i5 and i-phase drive signal S i6 .

[0006] In some embodiments, in the superimposed signal generating step, the method of generating the superimposed signal according to the three-phase original sinusoidal modulation wave is: 1 minus the original sinusoidal modulation wave of phase A to obtain the first signal s a1 , 1 minus the original sinusoidal modulation wave of phase B to obtain the second signal s b1 , 1 minus the C-phase original sinusoidal modulation wave to obtain the third signal s c1 ; Take the original sinusoidal modulation wave of phase A as the first comparison signal. If the first comparison signal>0, the signal s au Equal to the first signal s a1 Otherwise, the signal s au Equal to the original sinusoidal modulation wave of phase A; the original sinusoidal modulation wave of phase B is used as the second comparison signal. If the second comparison signal>0, the signal is obtained. s bu Equal to the second signal s b1 Otherwise, the signal s bu Equal to the original sinusoidal modulation wave of phase B; the original sinusoidal modulation wave of phase C is used as the third comparison signal. If the third comparison signal>0, the signal is obtained. s cu Equal to the third signal s c1 Otherwise, the signal s cu Equal to the original sinusoidal modulation wave of phase C; respectively s au ,Signal s bu ,Signal scu Take the absolute value to get the signal s a_u ,Signal s b_u ,Signal s c_u , get the signal s a_u ,Signal s b_u ,Signal s c_u The minimum signal among the three signals is the first minimum value s min1 ; 1 plus the original sinusoidal modulation wave of phase A to obtain the fourth signal s a2 , 1 plus the original sinusoidal modulation wave of phase B to obtain the fifth signal s b2 , 1 plus the original sinusoidal modulation wave of phase C to obtain the sixth signal s c2 ; Take the original sinusoidal modulation wave of phase A as the fourth comparison signal. If the fourth comparison signal ≤ 0, the signal is obtained. s ad Equal to the fourth signal s a2 Otherwise, the signal s ad Equal to the original sinusoidal modulation wave of phase A; the original sinusoidal modulation wave of phase B is used as the fifth comparison signal. If the fifth comparison signal ≤ 0, the signal is obtained. s bd Equal to the fifth signal s b2 Otherwise, the signal s bd =Equal to the original sinusoidal modulation wave of phase B; the original sinusoidal modulation wave of phase C is used as the sixth comparison signal. If the sixth comparison signal ≤ 0, the signal is obtained. s cd Equal to the sixth signal s c2 Otherwise, the signal s cd Equal to the original sinusoidal modulation wave of phase C; respectively s ad ,Signal s bd ,Signal s cd Take the absolute value to get the signal s a_d ,Signal s b_d ,Signal s c_d , get the signal s a_d ,Signals b_d ,Signal s c_d The smallest signal among the three signals is the second smallest value s min2 ; Take the first minimum value s min1 , the second minimum s min2 The minimum value in is the third smallest value s min3 ; Take the first minimum s min1 Subtract the second smallest value s min2 The difference obtained s min is the seventh comparison signal. If the difference s min >0, then the signal is obtained c _ alpha Equal to -1, otherwise get a signal c _ alpha is equal to 1; The third minimum s min3 Multiply the signal c _ alpha Get the superimposed signal.

[0007] In some embodiments, in the modulation wave generating step, the method of obtaining the final modulation wave of phase i according to the original sinusoidal modulation wave of phase i and the superimposed signal is as follows: the original sinusoidal modulation wave of phase i is added with the superimposed signal and then multiplied by 300 to obtain the final modulation wave of phase i.

[0008] In some embodiments, in the three modulation wave generating step, the method of obtaining the i-phase lower modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage is: The DC bus voltage is multiplied by -1 / 6 to obtain the first modulation wave s i11 The final modulation wave of phase i is multiplied by 2 / 3 and then added with -1 / 6 times the DC bus voltage to obtain the second modulation wave s i12 ; If the final modulation wave of phase i>0, the modulation wave of phase i is the first modulation wave s i11 ; If the final modulation wave of phase i is ≤0, the modulation wave of phase i is the second modulation wave s i12 .

[0009] In some embodiments, in the three-modulation wave generation step, the method for obtaining the i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage is: multiply the DC bus intermediate capacitor voltage by 3 and divide it by the DC bus voltage, multiply it by the i-phase final modulation wave, and then multiply it by 1 / 3 to obtain the i-phase intermediate modulation wave.

[0010] In some embodiments, the method according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the modulation wave on phase i of the DC bus voltage is: The final modulation wave of phase i is multiplied by 2 / 3 and then added with 1 / 6 of the DC bus voltage to obtain the third modulation wave. s i31 , multiply the DC bus voltage by 1 / 6 to get the fourth modulation wave s i32 ; If the final modulation wave of phase i>0, the modulation wave on phase i is the third modulation wave s i31 ; If the final modulation wave of phase i is ≤0, the modulation wave on phase i is the fourth modulation wave s i32 .

[0011] In some embodiments, in the step of generating the driving signal, the i-phase driving signal S is generated according to the size of the upper stacked carrier and the i-phase modulation wave. i1 and i-phase drive signal S i2 The method is: when the modulation wave on phase i is greater than or equal to the upper layer stacked carrier, S i1 is high level, S i2 When the modulation wave on phase i is less than the upper layer stacked carrier, S i1 is low level, S i2 is high level; The i-phase drive signal S is generated by setting the size of the middle-layer stacked carrier and the i-phase intermediate modulation wave. i3 and i-phase drive signal S i4 The method is: when the intermediate modulation wave of phase i is greater than or equal to the set middle layer stacked carrier, S i3 is high level, S i4 When the intermediate modulation wave of phase i is less than the set middle layer stacked carrier wave, S i3 is low level, S i4 is high level; The i-phase drive signal S is generated by setting the lower layer stacked carrier and the size of the i-phase down modulation wave. i5 and i-phase drive signal S i6 The method is: when the modulation wave of phase i is greater than or equal to the lower stacked carrier, S i5 is high level, S i6 is low level; when the modulation wave of phase i is less than the set lower layer stacked carrier, S i5is low level, S i6 is high level.

[0012] In a second aspect of the present invention, a low switching loss modulation system for a four-level split inverter of a SiC device is provided, which is used to implement the low switching loss modulation method for a four-level split inverter of a SiC device according to the first aspect of the present invention, comprising: A superposition signal generating module generates a superposition signal according to the three-phase original sinusoidal modulation wave; A modulation wave generation module generates an i-phase final modulation wave according to an i-phase original sinusoidal modulation wave and a superimposed signal; Three modulation wave generation modules, generating an i-phase lower modulation wave and an i-phase upper modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage, and generating an i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage; The driving signal generation module generates the i-phase driving signal S according to the size of the upper layer stacked carrier and the i-phase modulation wave. i1 and i-phase drive signal S i2 , according to the size of the set middle layer stacked carrier and the i phase intermediate modulation wave, the i phase drive signal S is generated i3 and i-phase drive signal S i4 , according to the setting of the lower layer stacked carrier and the size of the i-phase down modulation wave, the i-phase drive signal S is generated. i5 and i-phase drive signal S i6 .

[0013] In some embodiments, the three-modulation wave generation module includes: A down-modulation wave generating module generates an i-phase down-modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage; An intermediate modulation wave generating module generates an i-phase intermediate modulation wave according to an i-phase final modulation wave, a DC bus voltage and a DC bus intermediate capacitor voltage; The upper modulation wave generating module generates the i-phase upper modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage.

[0014] In some embodiments, the driving signal generating module includes: Logic module I, when the modulation wave on phase i ≥ the set upper layer stacked carrier, output S i1 is high level, S i2 When the modulation wave on phase i is less than the set upper layer stacked carrier, the output S i1 is low level, S i2 is high level; Logic module II, when the intermediate modulation wave of phase i ≥ the set middle layer stacked carrier, output S i3 is high level, Si4 When the intermediate modulation wave of phase i is less than the set middle layer stacked carrier wave, the output S i3 is low level, S i4 is high level; Logic module III, when the modulation wave of phase i is greater than or equal to the set lower layer stacked carrier, output S i5 is high level, S i6 When the modulation wave of phase i is less than the set lower layer stacking carrier, the output S i5 is low level, S i6 is high level.

[0015] Compared with the prior art, the advantages and positive effects of the present invention are: The low switching loss modulation method and system of the SiC device four-level split inverter provided by the present invention obtains the final modulation wave by superimposing signals, and obtains the upper modulation wave, the middle modulation wave and the lower modulation wave according to the size of the final modulation wave, the final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage. At any time, the three modulation waves are clamped at a specific level. U dc / 2, 0, - U dc / 2. On the one hand, it can realize DC bus capacitor voltage balancing, thereby outputting a good current waveform and improving power quality. On the other hand, after the clamping level is compared with the upper, middle and lower three-layer stacked carrier, it will not cause the SiC MOSFET to switch, which can effectively reduce switching losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A circuit diagram of a ripple bus SiC device isolated output inverter according to an embodiment of the present invention; Figure 2 This is a flow chart of a low switching loss modulation method for a four-level split inverter of a SiC device according to an embodiment of the present invention; Figure 3 A schematic diagram of superimposed signal generation according to an embodiment of the present invention; Figure 4 A schematic diagram of the modulation wave generation according to an embodiment of the present invention; Figure 5 A schematic diagram of the generation of three modulation waves according to an embodiment of the present invention; Figure 6 A schematic diagram of the driving signal generation according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the A-phase three-modulation wave generation link according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the A-phase drive signal generation link according to an embodiment of the present invention; Fig. 9The upper layer stacked carrier described in the embodiment of the present invention U c1 With A phase up modulation wave s Az3 Waveform diagram of ; Fig.10 The middle layer stacked carrier described in the embodiment of the present invention U c2 Intermediate modulation wave with phase A s Az2 Waveform diagram of ; Fig.11 The lower layer stacked carrier described in the embodiment of the present invention U c3 With A phase down modulation wave s Az1 Waveform diagram of ; Fig.12 This is a structural block diagram of a low switching loss modulation system of a SiC device four-level split inverter according to an embodiment of the present invention; Fig.13 It is a schematic diagram of the three-phase output current waveform using the traditional stacked carrier modulation method; Fig.14 A schematic diagram of a three-phase output current waveform of a low switching loss modulation method and system for a four-level split inverter of a SiC device according to an embodiment of the present invention; Fig.15 A schematic diagram of the A-phase driving signal waveform using the traditional stacked carrier modulation method; Fig.16 The figure is a schematic diagram of the A-phase drive signal waveform of the low switching loss modulation method and system of the SiC device four-level split inverter according to the embodiment of the present invention.

[0017] In the figure, 1. superposition signal generation module, 2. modulation wave generation module, 3. three modulation wave generation module, 4. driving signal generation module, 5. A phase modulation module, 6. B phase modulation module, 7. C phase modulation module. DETAILED DESCRIPTION

[0018] The present invention will be described in detail below by way of exemplary embodiments in conjunction with the accompanying drawings. However, it should be understood that, without further description, elements, structures and features in one embodiment may also be beneficially combined in other embodiments.

[0019] Figure 1 The main topology circuit of the SiC device four-level split inverter is shown in FIG. U dc is the DC bus voltage, C 1 , C 2 , C3 is the DC bus capacitance; Q a1 To Q a6 A is the SiC MOSFET power switch device, D a1 To D a10 For the A-phase SiC Schottky diode, L a1 To L a6 Isolation inductance of phase A; i a , i b , i c is the three-phase current; L a , L b , L c is the three-phase load inductance, R a , R b , R c It should be noted that since the three-phase circuits A, B, and C are completely symmetrical, the topological circuit structures of the three-phase circuits A, B, and C are exactly the same. Figure 1 Only the topological circuit structure of phase A is given, and the topological circuit structures of phases B and C are the same as the topological circuit structure of phase A.

[0020] Continue to see Figure 1 Since the ABC three-phase bridge arms are completely symmetrical, phase A is used as an example to illustrate the connection method of the main circuit. U dc Provide the overall voltage for the DC bus, and the DC bus capacitors are connected in series from top to bottom. C 1 , DC bus capacitor C 2 , DC bus capacitor C 3 ; U dc One end and C 1 One end of is connected to point P, U dc The other end of C 3 One end of is connected to point N. C 1 and C 2 Connect to O 1 point, C 2 and C 3 Connect to O 2 Point; Q a1 and D a1 One end is connected to the positive pole P of the DC bus, D a1The other end and Q a2 Connect to X a1 Point, Q a1 The other end and D a2 Connect to X a2 Point; Q a2 The other end and D a2 The other end of the Q a3 , D a3 One end passes through X a3 Connect the dots; Q a3 The other end and D a4 Connect to X a4 Point, D a3 The other end and Q a4 Connect to X a5 Point, Q a4 The other end and D a4 The other end of the Q a5 , D a5 One end passes through X a6 Connect the dots, D a5 The other end and Q a6 Connect to X a7 Point, Q a5 The other end and D a6 Connect to X a8 Point, Q a6 With D a6 The other end is connected to the negative pole of the DC bus, point N. a3 and L a4 In parallel, one end is connected in parallel to X a13 Point, X a4 and X a13 Through the inductor L a3 Connect, X a5 and X a13 Through the inductor L a4 Connection. Isolation inductor L a1 and L a2 In parallel, one end is connected in parallel to X a9 Point, X a1 and X a9 Through the inductor L a1 Connect, X a2 and X a9 Through the inductor L a2 Connect. D a7 One end of L a1 and L a2 The parallel combination is connected to X a9 point, and the other end is D a8 Connect to X a10 Point, D a8 The other end of X a6 Point connection; isolation inductor L a5 and La6 In parallel, one end is connected in parallel to X a12 Point, X a7 and X a12 Through the inductor L a5 Connect, X a8 and X a12 Through the inductor L a6 Connect, D a9 One end and X a3 point, and the other end is connected to D a10 Connect to X a11 Point, D a10 The other end of L a5 and L a6 The parallel combination is connected to X a12 Point. 1 Dot and X a10 Connect the dots, O 2 Dot and X a11 Connect the dots, L a With R a Series, X a13 point and the load neutral point O through L a With R a The connection method of the B-phase and C-phase main circuits is the same as that of the A-phase, and will not be repeated here.

[0021] For the above-mentioned SiC device four-level split inverter, the present invention provides a low switching loss modulation method and system for a SiC device four-level split inverter, which generates a superimposed signal that needs to be injected into the final modulation wave according to the three-phase original sinusoidal modulation wave, and the three-phase original sinusoidal modulation wave is superimposed with the superimposed signal to generate a three-phase final modulation wave. The three modulation waves generated by the three final modulation waves, the DC bus voltage and the DC bus intermediate capacitor voltage are compared with the stacked carrier to generate a driving signal. On the one hand, it can achieve DC bus capacitor voltage balancing, thereby outputting a good current waveform and improving the power quality. On the other hand, after the clamping level is compared with the upper, middle and lower three-layer stacked carriers, the SiC MOSFET switch will not be actuated, which can effectively reduce the switching loss.

[0022] The low switching loss modulation method and system of the SiC device four-level split inverter of the present invention are described in detail below in conjunction with the accompanying drawings and embodiments.

[0023] See also Figure 2 The first aspect of the present invention provides a low switching loss modulation method for a four-level split inverter of a SiC device, and the specific steps are as follows: S1, superimposed carrier generation step: generating a superimposed signal according to the three-phase original sinusoidal modulation wave.

[0024] Specifically, see Figure 3, the method of generating superposition signal based on the three-phase original sinusoidal modulation wave is: 1 minus A phase original sine modulation wave s A Get the first signal s a1 , 1 minus B phase original sinusoidal modulation wave s B Get the second signal s b1 , 1 minus the original C-phase sinusoidal modulation wave s C Get the third signal s c1 ; With the original sinusoidal modulation wave of phase A s A The first comparison signal s ac1 , if the first comparison signal s ac1 >0, then the signal is obtained s au Equal to the first signal s a1 Otherwise, the signal s au Equal to the original sinusoidal modulation wave of phase A s A ; With the original sinusoidal modulation wave of phase B s B The second comparison signal s bc1 , if the second comparison signal s bc1 >0, then the signal is obtained s bu Equal to the second signal s b1 Otherwise, the signal s bu Equal to the original sinusoidal modulation wave of phase B s B ; Using the C phase original sine modulation wave s C The third comparison signal s cc1 , if the third comparison signal s cc1 >0, then the signal is obtained s cu Equal to the third signal s c1 Otherwise, the signal s cu Equal to the original sinusoidal modulation wave of phase C s C ; respectively for the signal s au ,Signals bu ,Signal s cu Take the absolute value to get the signal s a_u ,Signal s b_u ,Signal s c_u , get the signal s a_u ,Signal s b_u ,Signal s c_u The minimum signal among the three signals is the first minimum value s min1 ; 1 plus A phase original sine modulation wave s A Get the fourth signal s a2 , 1 plus B phase original sine modulation wave s B Get the fifth signal s b2 , 1 plus C phase original sinusoidal modulation wave s C Get the sixth signal s c2 ; With the original sinusoidal modulation wave of phase A s A The fourth comparison signal s ac2 , if the fourth comparison signal s ac2 ≤0, then the signal is obtained s ad Equal to the fourth signal s a2 Otherwise, the signal s ad Equal to the original sinusoidal modulation wave of phase A s A ; With the original sinusoidal modulation wave of phase B s B The fifth comparison signal s bc2 , if the fifth comparison signal s bc2 ≤0, then the signal is obtained s bd Equal to the fifth signal s b2 Otherwise, the signal s bd Equal to the original sinusoidal modulation wave of phase B s B ; Using the C phase original sine modulation wave sC The sixth comparison signal s cc2 , if the sixth comparison signal s cc2 ≤0, then the signal is obtained s cd Equal to the sixth signal s c2 Otherwise, the signal s cd Equal to the original sinusoidal modulation wave of phase C s C ; respectively for the signal s ad ,Signal s bd ,Signal s cd Take the absolute value to get the signal s a_d ,Signal s b_d ,Signal s c_d , get the signal s a_d ,Signal s b_d ,Signal s c_d The smallest signal among the three signals is the second smallest value s min2 ; Take the first minimum value s min1 , the second minimum s min2 The minimum value in is the third smallest value s min3 ; Take the first minimum s min1 Subtract the second smallest value s min2 The difference obtained s min is the seventh comparison signal. If the difference s min >0, then the signal is obtained c _ alpha Equal to -1, otherwise get a signal c _ alpha is equal to 1; The third minimum s min3 Multiply the signal c _ alpha Get the superimposed signal s z .

[0025] S2, modulation wave generation step: obtain the final modulation wave of phase i according to the original sinusoidal modulation wave of phase i and the superimposed signal.

[0026] Specifically, in some embodiments, see Figure 4 The method for obtaining the final modulation wave of phase i according to the original sinusoidal modulation wave of phase i and the superimposed signal is as follows: the original sinusoidal modulation wave of phase i is added with the superimposed signal, and then multiplied by 300 to obtain the final modulation wave of phase i.

[0027] Specifically, see Figure 4 , A phase original sinusoidal modulation wave s A Add superimposed signal s z Then multiply by 300 to get the final modulation wave of phase A. s Az . B phase original sinusoidal modulation wave s B Add superimposed signal s z Then multiply by 300 to get the final modulation wave of phase B. s Bz . C phase original sinusoidal modulation wave s C Add superimposed signal s z Then multiply by 300 to get the final modulation wave of phase C s Cz .

[0028] S3, three modulation wave generation steps: according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the DC bus voltage, the lower modulation wave of phase i and the upper modulation wave of phase i are obtained; according to the final modulation wave of phase i, the DC bus voltage and the DC bus intermediate capacitor voltage, the intermediate modulation wave of phase i is obtained.

[0029] Specifically, in some embodiments, see Figure 5 , according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the DC bus voltage, the method of obtaining the modulation wave of phase i is: DC bus voltage U dc Multiply by -1 / 6 to get the first modulation wave s i11 , the final modulation wave of phase i s iz Multiply by 2 / 3 and add -1 / 6 times the DC bus voltage U dc Get the second modulation wave s i12 ; If the final modulation wave of phase i s iz >0, i phase down modulation waves iz1 The first modulation wave s i11 ; If the final modulation wave of phase i s iz ≤0, i phase down modulation wave s iz1 The second modulation wave s i12 .

[0030] Specifically, in some embodiments, continue to see Figure 5 The method of obtaining the intermediate modulation wave of phase i according to the final modulation wave of phase i, the DC bus voltage and the DC bus intermediate capacitor voltage is: U dc2 Multiply by 3 and divide by the DC bus voltage U dc After that, multiply it by the final modulation wave of phase i s iz , and then multiply by 1 / 3 to get the intermediate modulation wave of phase i s iz2 .

[0031] Specifically, in some embodiments, continue to see Figure 5 , according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the modulation wave on phase i of the DC bus voltage: Final modulation wave of phase i s iz Multiply by 2 / 3 and add 1 / 6 times the DC bus voltage U dc Get the third modulation wave s i31 , DC bus voltage U dc Multiply by 1 / 6 to get the fourth modulation wave s i32 ; If the final modulation wave of phase i s iz >0, i phase up modulation wave s iz3 The third modulation wave s i31 ; If the final modulation wave of phase i s iz ≤0, i phase upper modulation wave s iz3 The fourth modulation wave s i32 .

[0032] S4, driving signal generation step: see Figure 6 , according to the setting of the upper layer stacked carrier Uc1 , i-phase up-modulation wave s iz3 The size of the i-phase drive signal S is generated i1 and i-phase drive signal S i2 , according to the setting of the middle layer stacked carrier U c2 , i-phase intermediate modulation wave s iz2 The size of the i-phase drive signal S is generated i3 and i-phase drive signal S i4 , according to the setting of the lower layer stacked carrier U c3 , i-phase down-modulation wave s iz1 The size of the i-phase drive signal S is generated i5 and i-phase drive signal S i6 .

[0033] Specifically, in some embodiments, continue to see Figure 6 In the driving signal generating step, according to setting the upper layer stacked carrier U c1 , i-phase up-modulation wave s iz3 The size of the i-phase drive signal S is generated i1 and i-phase drive signal S i2 The method is: i phase up modulation wave s iz3 ≥Set the upper layer carrier U c1 When the driving signal S i1 is high level, driving signal S i2 Low level; i phase up modulation wave s iz3 <Set the upper layer overlay carrier U c1 When the driving signal S i1 is low level, driving signal S i2 is high level.

[0034] Specifically, in some embodiments, continue to see Figure 6 , according to the setting of the middle layer stacked carrier U c2 , i-phase intermediate modulation wave s iz2 The size of the i-phase drive signal S is generated i3 and i-phase drive signal S i4 The method is: i-phase intermediate modulation wave s iz2 ≥Set the middle layer stacking carrier U c2 When the driving signal Si3 is high level, driving signal S i4 Is low level; i phase intermediate modulation wave s iz2 <Setting the middle layer overlay carrier U c2 When the driving signal S i3 is low level, driving signal S i4 is high level.

[0035] Specifically, in some embodiments, continue to see Figure 6 , according to the setting of the lower layer stacked carrier U c3 , i-phase down-modulation wave s iz1 The size of the i-phase drive signal S is generated i5 and i-phase drive signal S i6 The method is: i phase down modulation wave s iz1 ≥Set the lower layer overlay carrier U c3 When the driving signal S i5 is high level, driving signal S i6 Low level; i phase down modulation wave s iz1 <Set the lower layer overlay carrier U c3 When the driving signal S i5 is low level, driving signal S i6 is high level.

[0036] exist Figure 3-Figure 6 In each link shown, the signal is judged and selected by selecting the switch Switch. The Switch is divided into an input side and an output side. In the input side, there are three signal inputs, the terminals "+" and "-" are signal input terminals, the terminal in is the comparison signal input terminal, and the terminal O is the signal output terminal. When the signal of the comparison signal terminal in is greater than 0, the O terminal outputs the signal received by the "+" terminal; when the comparison signal received by the in terminal is less than 0, the O terminal outputs the signal received by the "-" terminal.

[0037] It should be noted that, since the A-phase modulation, the B-phase modulation, and the C-phase modulation are the same, the modulation principle of the above method is described below using the A-phase modulation as an example.

[0038] See also Figure 7 In the A-phase three-modulation wave generation link, the DC bus voltage U dc Multiply by -1 / 6 to get the first modulation wave s A11 , the final modulation wave of phase A s AzMultiply by 2 / 3 and add -1 / 6 times the DC bus voltage U dc Get the second modulation wave s A12 ; If the final modulation wave of phase A s Az >0, A phase down modulation wave s Az1 The first modulation wave s A11 ; If the final modulation wave of phase A s Az ≤0, A phase down modulation wave s Az1 The second modulation wave s A12 . DC bus intermediate capacitor voltage U dc2 Multiply by 3 and divide by the DC bus voltage U dc After that, multiply it by the final modulation wave of phase A s Az , and then multiply by 1 / 3 to get the intermediate modulation wave of phase A s Az2 The final modulation wave of phase A s Az Multiply by 2 / 3 and add 1 / 6 times the DC bus voltage U dc Get the third modulation wave s A31 , DC bus voltage U dc Multiply by 1 / 6 to get the fourth modulation wave s A32 ; If the final modulation wave of phase A s Az >0, A phase up modulation wave s Az3 The third modulation wave s A31 ; If the final modulation wave of phase A s Az ≤0, A phase upper modulation wave s Az3 The fourth modulation wave s A32 .

[0039] See also Figure 8 , in the A phase drive signal generation link, the A phase upper modulation wave s Az3 ≥Set the upper layer carrier U c1 When the driving signal S A1 is high level, driving signal S A2Low level; A phase up modulation wave s Az3 <Set the upper layer overlay carrier U c1 When the driving signal S A1 is low level, driving signal S A2 A phase intermediate modulation wave s Az2 ≥Set the middle layer stacking carrier U c2 When the driving signal S A3 is high level, driving signal S A4 Low level; A phase intermediate modulation wave s Az2 <Setting the middle layer overlay carrier U c2 When the driving signal S A3 is low level, driving signal S A4 A phase down modulation wave s Az1 ≥Set the lower layer overlay carrier U c3 When the driving signal S A5 is high level, driving signal S A6 Low level; A phase down modulation wave s Az1 <Set the lower layer overlay carrier U c3 When the driving signal S A5 is low level, driving signal S A6 is high level.

[0040] In order to more intuitively demonstrate the basic principle of low switching loss modulation method of SiC device four-level split inverter, Fig. 9 Shows the upper layer stacked carrier U c1 With A phase up modulation wave s Az3 The waveform of Fig.10 Demonstrates mid-layer stacked carrier U c2 Intermediate modulation wave with phase A s Az2 The waveform of Fig.11 Demonstrates the underlying stacked carrier U c3 With A phase down modulation wave s Az1 It can be seen that at any time, the modulation wave of phase A is s Az1 , A phase intermediate modulation wave s Az2 , A phase up modulation wave sAz3 are clamped at a specific level U dc / 2, 0, - U dc / 2. Through the above modulation method, on the one hand, the DC bus capacitor voltage can be balanced, so as to output a good current waveform and improve the power quality. On the other hand, after the clamping level is compared with the stacked three-carrier, the SiCMOSFET switch will not be activated, which can effectively reduce the switching loss.

[0041] The above specifically introduces the A phase drive signal S A1 , S A2 , S A3 , S A4 , S A5 , S A6 The generation process of the driving signal of phase B and phase C is the same, which will not be repeated here.

[0042] See also Fig.12 The second aspect of the present invention provides a low switching loss modulation system for a four-level split inverter of a SiC device, which is used to implement the low switching loss modulation method for a four-level split inverter of a SiC device described in the first aspect of the present invention, including a superposition signal generation module 1, a modulation wave generation module 2, an A-phase modulation module 5, a B-phase modulation module 6 and a C-phase modulation module 7 three-phase single-carrier modulation module, and each phase modulation module includes three modulation wave generation modules 3 and a drive signal generation module 4.

[0043] The superposition signal generating module 1 generates a superposition signal according to the three-phase original sinusoidal modulation wave.

[0044] The modulation wave generating module 2 generates the final modulation wave of the i phase according to the original sinusoidal modulation wave of the i phase and the superimposed signal.

[0045] The three modulation wave generation module 3 generates an i-phase lower modulation wave and an i-phase upper modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage, and generates an i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage.

[0046] The driving signal generating module 4 generates the i-phase driving signal S according to the size of the upper stacked carrier and the i-phase modulation wave. i1 and i-phase drive signal S i2 , according to the size of the set middle layer stacked carrier and the i phase intermediate modulation wave, the i phase drive signal S is generated i3 and i-phase drive signal S i4 , according to the setting of the lower layer stacked carrier and the size of the i-phase down modulation wave, the i-phase drive signal S is generated. i5 and i-phase drive signal S i6 .

[0047] In some embodiments, the three-modulation wave generation module includes: A down-modulation wave generating module generates an i-phase down-modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage; An intermediate modulation wave generating module generates an i-phase intermediate modulation wave according to an i-phase final modulation wave, a DC bus voltage and a DC bus intermediate capacitor voltage; The upper modulation wave generating module generates the i-phase upper modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage.

[0048] In some embodiments, the driving signal generating module includes: Logic module I, when the modulation wave on phase i ≥ the set upper layer stacked carrier, output S i1 is high level, S i2 When the modulation wave on phase i is less than the set upper layer stacked carrier, the output S i1 is low level, S i2 is high level; Logic module II, when the intermediate modulation wave of phase i ≥ the set middle layer stacked carrier, output S i3 is high level, S i4 When the intermediate modulation wave of phase i is less than the set middle layer stacked carrier wave, the output S i3 is low level, S i4 is high level; Logic module III, when the modulation wave of phase i ≥ the set lower layer stacked carrier, the output S i5 is high level, S i6 When the modulation wave of phase i is less than the set lower layer stacking carrier, the output S i5 is low level, S i6 is high level.

[0049] In order to verify the effectiveness of the low switching loss modulation method and system of the SiC device four-level split inverter of the present invention, simulation verification is carried out in MATLAB / Simulink. The DC bus voltage is 600V, the three DC bus capacitors are 1000μF, the load resistance is 30Ω, and the load inductance is 2mH. In the simulation model, the traditional fixed stacked triangle carrier modulation method and the low switching loss modulation method and system of the SiC device four-level split inverter proposed by the present invention are used for modulation. Fig.13The three-phase output current waveform using the traditional fixed stacked triangle carrier modulation method is given. Since it does not have the voltage stabilization function of the DC bus capacitor voltage, the bus capacitor voltage gradually decays to 0 during operation, and the corresponding three-phase current is severely distorted. Through Fourier analysis, it can be seen that the total harmonic distortion rates THD of the three-phase currents A, B, and C in the dynamic process are 4.54%, 4.92%, and 4.81% respectively. Fig.14 The three-phase current waveform of the low switching loss modulation method and system of the SiC device four-level split inverter proposed by the present invention is given. Since the proposed method has the voltage stabilization function of the DC bus capacitor voltage, the three capacitor voltages of the DC bus are balanced, so that the sinusoidality of the three-phase output current waveform is significantly improved. Through Fourier analysis, it can be seen that the total harmonic distortion rate THD of the three-phase current of A, B, and C is 2.49%, 2.50%, and 2.51% respectively.

[0050] Fig.15 The A-phase driving signal waveform using the traditional fixed stacked triangle carrier modulation method is given; Fig.16 The A-phase drive signal waveform of the low switching loss modulation method and system of the SiC device four-level split inverter proposed by the present invention is given. Fig.15 and Fig.16 It can be seen that the low switching loss modulation method and system of the SiC device four-level split inverter proposed by the present invention can reduce the number of SiC MOSFET switches and effectively reduce the switching loss. Improve the efficiency of the SiC device four-level split inverter.

[0051] The above embodiments are used to explain the present invention rather than to limit the present invention. Any modification and change made to the present invention within the spirit of the present invention and the protection scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A low switching loss modulation method for a SiC device four-level split inverter, characterized in that: The specific steps are: Superposition signal generation step: generating a superposition signal according to the three-phase original sinusoidal modulation wave; Modulation wave generation steps: obtain the final modulation wave of phase i according to the original sinusoidal modulation wave of phase i and the superimposed signal, i=A, B, C; Three modulation wave generation steps: according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the DC bus voltage, obtain the lower modulation wave of phase i and the upper modulation wave of phase i; according to the final modulation wave of phase i, the DC bus voltage and the DC bus intermediate capacitor voltage, obtain the intermediate modulation wave of phase i; Driving signal generation step: Generate the i-phase driving signal S according to the size of the upper layer stacked carrier and the i-phase modulation wave i1 and i-phase drive signal S i2 , according to the size of the set middle layer stacked carrier and the i phase intermediate modulation wave, the i phase drive signal S is generated i3 and i-phase drive signal S i4 , according to the setting of the lower layer stacked carrier and the size of the i-phase down modulation wave, the i-phase drive signal S is generated. i5 and i-phase drive signal S i6 .

2. The low switching loss modulation method for a SiC device four-level split inverter according to claim 1, characterized in that: In the superimposed signal generation step, the method for generating the superimposed signal according to the three-phase original sinusoidal modulation wave is: 1 minus the original sinusoidal modulation wave of phase A to obtain the first signal s a1 , 1 minus the B phase original sine modulation wave to get the second signal s b1 , 1 minus the C-phase original sinusoidal modulation wave to obtain the third signal s c1 ; Take the original sinusoidal modulation wave of phase A as the first comparison signal. If the first comparison signal>0, the signal is obtained. s au Equal to the first signal s a1 Otherwise, the signal s au Equal to the original sinusoidal modulation wave of phase A; the original sinusoidal modulation wave of phase B is used as the second comparison signal. If the second comparison signal>0, the signal is obtained. s bu Equal to the second signal s b1 Otherwise, the signal s bu Equal to the original sinusoidal modulation wave of phase B; The original sinusoidal modulation wave of phase C is used as the third comparison signal. If the third comparison signal > 0, the signal is obtained. s cu Equal to the third signal s c1 Otherwise, the signal s cu Equal to the original sinusoidal modulation wave of phase C; respectively for the signal s au ,Signal s bu ,Signal s cu Take the absolute value to get the signal s a_u ,Signal s b_u ,Signal s c_u , get the signal s a_u ,Signal s b_u ,Signal s c_u The minimum signal among the three signals is the first minimum value s min1 ; 1 plus the original sinusoidal modulation wave of phase A to obtain the fourth signal s a2 , 1 plus the original sinusoidal modulation wave of phase B to obtain the fifth signal s b2 , 1 plus the original sinusoidal modulation wave of phase C to obtain the sixth signal s c2 ; Take the original sinusoidal modulation wave of phase A as the fourth comparison signal. If the fourth comparison signal ≤ 0, the signal is obtained. s ad Equal to the fourth signal s a2 Otherwise, the signal s ad Equal to the original sinusoidal modulation wave of phase A; the original sinusoidal modulation wave of phase B is used as the fifth comparison signal. If the fifth comparison signal ≤ 0, the signal is obtained. s bd Equal to the fifth signal s b2 Otherwise, the signal s bd Equal to the original sinusoidal modulation wave of phase B; The original sinusoidal modulation wave of phase C is used as the sixth comparison signal. If the sixth comparison signal is ≤0, the signal is obtained. s cd Equal to the sixth signal s c2 Otherwise, the signal s cd Equal to the original sinusoidal modulation wave of phase C; respectively s ad ,Signal s bd ,Signal s cd Take the absolute value to get the signal s a_d ,Signal s b_d ,Signal s c_d , get the signal s a_d ,Signal s b_d ,Signal s c_d The smallest signal among the three signals is the second smallest value s min2 ; Take the first minimum value s min1 , the second minimum s min2 The minimum value in is the third smallest value s min3 ; Take the first minimum s min1 Subtract the second smallest value s min2 The difference obtained s min is the seventh comparison signal. If the difference s min >0, then the signal is obtained c _ alpha Equal to -1, otherwise get a signal c _ alpha is equal to 1; The third minimum s min3 Multiply the signal c _ alpha Get the superimposed signal.

3. The low switching loss modulation method for a SiC device four-level split inverter according to claim 1, characterized in that: In the modulation wave generation step, the method for obtaining the final modulation wave of phase i according to the original sinusoidal modulation wave of phase i and the superimposed signal is: the original sinusoidal modulation wave of phase i is added with the superimposed signal and then multiplied by 300 to obtain the final modulation wave of phase i.

4. The low switching loss modulation method for a SiC device four-level split inverter according to claim 1, characterized in that: In the three modulation wave generation step, the method for obtaining the i-phase lower modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage is: The DC bus voltage is multiplied by -1 / 6 to obtain the first modulation wave s i11 The final modulation wave of phase i is multiplied by 2 / 3 and then added with -1 / 6 times the DC bus voltage to obtain the second modulation wave s i12 ; If the final modulation wave of phase i>0, the modulation wave of phase i is the first modulation wave s i11 ; If the final modulation wave of phase i is ≤0, the modulation wave of phase i is the second modulation wave s i12 .

5. The low switching loss modulation method for a SiC device four-level split inverter according to claim 1, characterized in that: In the three-modulation wave generation step, the method for obtaining the i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage is: multiply the DC bus intermediate capacitor voltage by 3 and divide it by the DC bus voltage, multiply it by the i-phase final modulation wave, and then multiply it by 1 / 3 to obtain the i-phase intermediate modulation wave.

6. The low switching loss modulation method for a SiC device four-level split inverter according to claim 1, characterized in that: In the three modulation wave generation step, the method according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the modulation wave on phase i of the DC bus voltage is: The final modulation wave of phase i is multiplied by 2 / 3 and then added with 1 / 6 of the DC bus voltage to obtain the third modulation wave. s i31 , multiply the DC bus voltage by 1 / 6 to get the fourth modulation wave s i32 ; If the final modulation wave of phase i>0, the modulation wave on phase i is the third modulation wave s i31 ; If the final modulation wave of phase i is ≤0, the modulation wave on phase i is the fourth modulation wave s i32 .

7. The low switching loss modulation method for a SiC device four-level split inverter according to claim 1, characterized in that: In the driving signal generating step, the i-phase driving signal S is generated according to the setting of the upper layer stacked carrier and the magnitude of the i-phase modulation wave. i1 and i-phase drive signal S i2 The method is: when the modulation wave on phase i is greater than or equal to the upper layer stacked carrier, S i1 is high level, S i2 When the modulation wave on phase i is less than the upper layer stacked carrier, S i1 is low level, S i2 is high level; The i-phase drive signal S is generated by setting the size of the middle-layer stacked carrier and the i-phase intermediate modulation wave. i3 and i-phase drive signal S i4 The method is: when the intermediate modulation wave of phase i is greater than or equal to the set middle layer stacked carrier, S i3 is high level, S i4 When the intermediate modulation wave of phase i is less than the set middle layer stacked carrier wave, S i3 is low level, S i4 is high level; The i-phase drive signal S is generated by setting the lower layer stacked carrier and the size of the i-phase down modulation wave. i5 and i-phase drive signal S i6 The method is: when the modulation wave of phase i is greater than or equal to the lower stacked carrier, S i5 is high level, S i6 is low level; when the modulation wave of phase i is less than the set lower layer stacked carrier, S i5 is low level, S i6 is high level.

8. A low switching loss modulation system for a SiC device four-level split inverter, used to implement a low switching loss modulation method for a SiC device four-level split inverter as claimed in any one of claims 1 to 7, characterized in that: include: A superposition signal generating module generates a superposition signal according to the three-phase original sinusoidal modulation wave; A modulation wave generation module generates an i-phase final modulation wave according to an i-phase original sinusoidal modulation wave and a superimposed signal; Three modulation wave generation modules, generating an i-phase lower modulation wave and an i-phase upper modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage, and generating an i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage; The driving signal generation module generates the i-phase driving signal S according to the size of the upper layer stacked carrier and the i-phase modulation wave. i1 and i-phase drive signal S i2 , according to the size of the set middle layer stacked carrier and the i phase intermediate modulation wave, the i phase drive signal S is generated i3 and i-phase drive signal S i4 , according to the setting of the lower layer stacked carrier and the size of the i-phase down modulation wave, the i-phase drive signal S is generated. i5 and i-phase drive signal S i6 .

9. The SiC device four-level split inverter low switching loss modulation system according to claim 8, characterized in that: The three-modulation wave generation module includes: A down-modulation wave generating module generates an i-phase down-modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage; An intermediate modulation wave generating module generates an i-phase intermediate modulation wave according to an i-phase final modulation wave, a DC bus voltage and a DC bus intermediate capacitor voltage; The upper modulation wave generating module generates the i-phase upper modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage.

10. The SiC device four-level split inverter low switching loss modulation system according to claim 8, characterized in that: The driving signal generating module comprises: Logic module I, when the modulation wave on phase i ≥ the set upper layer stacked carrier, output S i1 is high level, S i2 When the modulation wave on phase i is less than the set upper layer stacked carrier, the output S i1 is low level, S i2 is high level; Logic module II, when the intermediate modulation wave of phase i ≥ the set middle layer stacked carrier, output S i3 is high level, S i4 When the intermediate modulation wave of phase i is less than the set middle layer stacked carrier wave, the output S i3 is low level, S i4 is high level; Logic module III, when the modulation wave of phase i is greater than or equal to the set lower layer stacked carrier, output S i5 is high level, S i6 When the modulation wave of phase i is less than the set lower layer stacking carrier, the output S i5 is low level, S i6 is high level.

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