Circuit board, electronic mainboard and electronic equipment

Abstract

The invention relates to the field of circuit boards, and discloses a circuit board, an electronic mainboard and electronic equipment. The circuit board comprises a substrate, a processor bonding pad, a first memory bonding pad, a second memory bonding pad, a first signal wire and a second signal wire, the substrate comprises four circuit layers which are arranged in a stacked mode, ground planes are laid on the first circuit layer and the fourth circuit layer, the processor bonding pad is arranged on the first circuit layer, and the second memory bonding pad is arranged on the second circuit layer. The first memory bonding pad and the second memory bonding pad are arranged on the first circuit layer or the fourth circuit layer, the first signal wiring is connected with the processor bonding pad and the first memory bonding pad, and the ground plane of the first circuit layer can provide a reference plane for the first signal wiring of the second circuit layer; the second signal wire connects the processor pad and the first memory pad, and the ground plane of the fourth circuit layer can provide a reference plane for the second signal wire of the third circuit layer. According to the embodiment, an additional circuit layer is not needed to provide a reference plane for signals, and the number of circuit layers of the circuit board can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of circuit boards, and in particular to a circuit board, an electronic mainboard and an electronic device. Background Art

[0002] With the rapid development of storage technology, the highest operating frequency (memory main frequency) that can be achieved by Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), such as DDR3, DDR4, and DDR5, has reached over 1 GHz. These high-frequency memories are connected to the processor on the circuit board through high-speed signal lines such as clock lines, data lines, and address lines to transmit high-speed signals to each other.

[0003] High-speed signals In the process of transmitting high-speed signals on the circuit board, the lack of a good signal return path may cause a lot of noise to be generated in the circuit board. This noise can generate erroneous signals, thereby interfering with the normal operation of the circuit. The lack of a direct return path will also introduce impedance in this path and generate a voltage drop on the ground plane, causing ground bounce. Signal returns will couple to anywhere they can find, and if there is no good reference plane, this energy may even couple to other traces, which may create antennas in unexpected places and may generate additional noise. The reference plane is also designed to contain the signal energy field generated around the trace. If there is not enough reference plane close to the signal on the trace, then these energy fields may extend to the rest of the board or to other devices.

[0004] Therefore, circuit boards usually need to set up reference planes to solve problems such as signal integrity and EMC (Electromagnetic Compatibility) of high-speed signals. Currently, separate circuit layers are usually set up on circuit boards to provide reference planes for high-speed signals transmitted on adjacent circuit layers. However, this method requires more circuit layers, which increases the cost of the circuit board and the height of the circuit board. Summary of the invention

[0005] An object of the embodiments of the present invention is to provide a circuit board, an electronic mainboard and an electronic device, which can solve the defects existing in the prior art.

[0006] In a first aspect, an embodiment of the present invention provides a circuit board, including:

[0007] The substrate comprises a first circuit layer, a second circuit layer, a third circuit layer and a fourth circuit layer which are stacked, and the first circuit layer and the fourth circuit layer are both paved with a ground plane;

[0008] A processor pad is arranged on the first circuit layer;

[0009] A first memory pad is disposed on the first circuit layer or the fourth circuit layer;

[0010] A second memory pad is disposed on the first circuit layer or the fourth circuit layer;

[0011] A first signal routing line is used to connect the processor pad and the first memory pad, the first signal routing line is routed on the second circuit layer, and the signal of the first signal routing uses the ground plane of the first circuit layer as a reference plane;

[0012] The second signal routing is used to connect the processor pad and the second memory pad. The second signal routing is routed on the third circuit layer. The signal of the second signal routing uses the ground plane of the fourth circuit layer as a reference plane.

[0013] Optionally, the first circuit layer, the second circuit layer, the third circuit layer or the fourth circuit layer is provided with a plurality of first vias corresponding to the processor pads, a plurality of second vias corresponding to the first memory pads and a plurality of third vias corresponding to the second memory pads;

[0014] The first signal trace connects the processor pad and the first memory pad through the first via, the second circuit layer and the second via;

[0015] The second signal wiring connects the processor pad and the second memory pad through the first via, the third circuit layer and the third via.

[0016] Optionally, if the first memory pad and the second memory pad are both arranged on the first circuit layer, the first signal routing is electrically connected to the processor pad on the first circuit layer, is routed on the second circuit layer after passing through the first via, and is electrically connected to the first memory pad on the first circuit layer after passing through the second via; the second signal routing is electrically connected to the processor pad on the first circuit layer, is routed on the third circuit layer after passing through the first via, and is electrically connected to the second memory pad on the first circuit layer after passing through the third via.

[0017] Optionally, if the first memory pad and the second memory pad are both arranged in the fourth circuit layer, the first signal routing is electrically connected to the processor pad in the first circuit layer, is routed in the second circuit layer after passing through the first via, and is electrically connected to the first memory pad in the fourth circuit layer after passing through the second via; the second signal routing is electrically connected to the processor pad in the first circuit layer, is routed in the third circuit layer after passing through the first via, and is electrically connected to the second memory pad in the fourth circuit layer after passing through the third via.

[0018] Optionally, if the first memory pad is set on the first circuit layer and the second memory pad is set on the fourth circuit layer, the first signal routing is electrically connected to the processor pad on the first circuit layer, is routed on the second circuit layer after passing through the first via, and is electrically connected to the first memory pad on the first circuit layer after passing through the second via; the second signal routing is electrically connected to the processor pad on the first circuit layer, is routed on the third circuit layer after passing through the first via, and is electrically connected to the second memory pad on the fourth circuit layer after passing through the third via.

[0019] Optionally, the first memory pad includes a first ground pin, the first ground pin is electrically connected to a ground plane of the circuit layer where the first memory pad is located, and the first ground pin and the ground plane of the circuit layer where the first memory pad is located constitute a complete reference plane;

[0020] The second memory pad includes a second ground pin, the second ground pin is electrically connected to the ground plane of the circuit layer where the second memory pad is located, and the second ground pin and the ground plane of the circuit layer where the second memory pad is located constitute a complete reference plane.

[0021] Optionally, it also includes power wiring; the power wiring is arranged in the first circuit layer and / or the fourth circuit layer.

[0022] Optionally, a first insulating dielectric layer is provided between the first circuit layer and the second circuit layer, and a thickness of the first insulating dielectric layer is less than or equal to a minimum spacing that satisfies a requirement that a ground plane of the first circuit layer shields a signal of a first signal line routed in the second circuit layer;

[0023] A second insulating dielectric layer is disposed between the third circuit layer and the fourth circuit layer, and a thickness of the second insulating dielectric layer is less than or equal to a minimum spacing required for a ground plane of the fourth circuit layer to shield a signal of a second signal line routed on the third circuit layer.

[0024] Optionally, a third insulating dielectric layer is arranged between the second circuit layer and the third circuit layer, and the thickness of the third insulating dielectric layer is greater than or equal to the minimum spacing that satisfies the requirement that the signal of the first signal line routed in the second circuit layer and the signal of the second signal line routed in the third circuit layer do not affect each other.

[0025] In a second aspect, an embodiment of the present invention provides an electronic mainboard, comprising the circuit board as described above.

[0026] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the electronic mainboard as described above.

[0027] In the circuit board provided in the embodiment of the present invention, it includes a substrate, a processor, a first memory, a second memory, a first signal routing and a second signal routing, the substrate includes a first circuit layer, a second circuit layer, a third circuit layer and a fourth circuit layer which are stacked, the first circuit layer and the fourth circuit layer are both paved with a ground plane, the processor pad is arranged on the first circuit layer, the first memory pad and the second memory pad are arranged on the first circuit layer or the fourth circuit layer, the first signal routing connects the processor and the first memory pad, the ground plane of the first circuit layer can provide a reference plane for the first signal routing arranged on the second circuit layer, the second signal routing connects the processor and the first memory pad, and the ground plane of the fourth circuit layer can provide a reference plane for the second signal routing arranged on the third circuit layer. In this embodiment, the device pad is arranged on the circuit layer which can provide a reference plane for the signal, and there is no need to arrange an additional circuit layer to provide a reference plane for the signal, which can reduce the number of circuit layers of the circuit board, and is conducive to reducing the cost and height of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are illustrated only as examples in the corresponding drawings, and these examples do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0029] Figure 1 It is a structural schematic diagram of an electronic mainboard provided by an embodiment of the present invention;

[0030] Figure 2 is a schematic structural diagram of a circuit board provided by an embodiment of the present invention;

[0031] Figure 3 is a schematic structural diagram of a circuit board provided by another embodiment of the present invention;

[0032] Figure 4 is a structural schematic diagram of a circuit board provided by another embodiment of the present invention;

[0033] Figure 5 is a structural schematic diagram of a circuit board provided by another embodiment of the present invention;

[0034] Figure 6 yes Figure 3 A schematic diagram of the layout of the circuit board shown;

[0035] Figure 7 This is a schematic structural diagram of a circuit board provided by yet another embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0037] It should be noted that, if there is no conflict, the various features in the embodiments of the present invention can be combined with each other, all within the scope of protection of the present invention. In addition, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a different order from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in the present invention do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0038] The embodiment of the present invention provides an electronic mainboard. Figure 1 The electronic mainboard 100 includes a circuit board 11, a processor 12, a first memory component 13 and a second memory component 14.

[0039] The circuit board 11 can be called a printed circuit board or a printed circuit board, and its English name is (Printed Circuit Board) PCB, (Flexible Printed Circuit board) FPC circuit board (FPC circuit board is also called flexible circuit board. Flexible circuit board is made of polyimide or polyester film as a substrate and has high reliability and excellent flexibility.

[0040] The circuit board 11 can use glass fiber as the basic material and is processed through copper coating, gold plating, etching and other processes. It serves as a supporting carrier for connecting electronic components and circuits together, and is used to realize the layout design of complex circuits in electrical and electronic equipment and electrical signal transmission and other functions.

[0041] The circuit board 11 can be formed by laminating a plurality of circuit layers (conductive pattern layers) with insulating materials therebetween, and the conductive patterns therebetween are interconnected as required to form a complex circuit network.

[0042] The processor 12 is disposed on the circuit board 11 , wherein the processor 12 is the computing and control core of the computer system and is the final execution unit for information processing and program running.

[0043] The first memory component 13 is disposed on the circuit board 11, wherein the first memory component 13 includes a first memory 131 and a first memory base 132, the first memory base 132 is used to install the first memory 131, when the first memory base 132 is mounted, the first memory base 132 can be soldered to the circuit board 11, in some embodiments, the first memory base 132 includes a ground pin, a signal pin and a power pin.

[0044] The second memory component 14 is disposed on the circuit board 11, wherein the second memory component 14 includes a second memory 141 and a second memory base 142, the second memory base 142 is used to install the second memory 141, when the second memory base 142 is mounted, the second memory base 142 can be welded to the circuit board 11, in some embodiments, the second memory base 142 includes a ground pin, a signal pin and a ground pin.

[0045] The first memory 131 and the second memory 141 are memory modules of the computer system, which are used to store programs and data. In some embodiments, the first memory 131 and the second memory 141 are SODIMMs (small outline dual in-line memory modules). SODIMMs are computer memories using integrated circuits, and are often used in systems with limited space, such as laptops, small-volume personal computers, high-end upgradeable office printers, and network hardware such as routers and NAS devices.

[0046] Please also read Figures 2 to 5 The circuit board 11 includes a substrate 111 , a processor pad 112 , a first memory pad 113 , a second memory pad 114 , a first signal trace 115 , and a second signal trace 116 .

[0047] The substrate 111 includes a first circuit layer L1 , a second circuit layer L2 , a third circuit layer L3 and a fourth circuit layer L4 which are stacked.

[0048] The first circuit layer L1 and the fourth circuit layer L4 are both paved with ground planes.

[0049] The ground plane is used as a reference plane to provide a reference return path for the return signal of the signal path. From the perspective of electromagnetic wave transmission, the signal path and the return path together form a special physical structure in which the electromagnetic wave is transmitted. From the perspective of the current loop, the signal path carries the signal current and the return path carries the return current.

[0050] In some embodiments, the ground plane can be made of any suitable metal material such as copper to form a plane. A large-area metal plane can provide an ideal return path for the return signal.

[0051] The ground plane of the first circuit layer L1 is used to provide a reference plane for the signals of the signal lines routed on the second circuit layer L2.

[0052] When the signal of the signal line routed on the second circuit layer L2 is transmitted on the second circuit layer L2, the signal flows back through the ground plane of the first circuit layer L1.

[0053] The ground plane of the fourth circuit layer L4 is used to provide a reference plane for the signals of the signal lines routed on the third circuit layer L3.

[0054] When the signal of the signal line routed on the third wiring layer L3 is transmitted on the third wiring layer L3, the signal flows back through the ground plane of the fourth wiring layer L4.

[0055] The processor pad 112 is disposed on the first circuit layer L1 .

[0056] When the processor 12 is mounted, the processor pad 112 may be soldered together with the processor 12 .

[0057] The first memory pad 113 may be disposed on the first circuit layer L1 or the fourth circuit layer L4. Figure 2 and Figure 4 As shown, the first memory pad 113 is disposed on the first circuit layer L1. Figure 3 and Figure 5 As shown, the first memory pad 113 is disposed on the fourth wiring layer L4.

[0058] When the first memory base 132 is mounted, the first memory pad 113 may be welded to the first memory base 132 .

[0059] Similarly, the second memory pad 114 can be disposed on the first circuit layer L1 or the fourth circuit layer L4. Figure 2 and Figure 5 As shown, the second memory pad 114 is disposed on the first circuit layer L1. Figure 3 and Figure 4 As shown, the second memory pad 114 is disposed on the fourth wiring layer L4.

[0060] When the second memory base 142 is mounted, the second memory pad 114 may be welded to the second memory base 142 .

[0061] The first memory pad 113 and the second memory pad 114 may be disposed on the same circuit layer of the circuit board 11, or may be disposed on different circuit layers of the circuit board 11. Figure 2 and Figure 3 As shown, the first memory pad 113 and the second memory pad 114 are arranged on the same circuit layer of the circuit board 11. Figure 4 and Figure 5 As shown, the first memory pad 113 and the second memory pad 114 are disposed on different circuit layers of the circuit board 11 .

[0062] The first signal trace 115 is used to connect the processor pad 112 and the first memory pad 113. Figures 2 to 5 As shown, the first signal line 115 is routed on the second circuit layer L2. After the first memory 131 is installed on the first memory base 132, the first signal line 115 transmits high-speed signals between the processor 12 and the first memory 131 on the second circuit layer L2.

[0063] See also Figure 6 The first signal wiring 115 includes a variety of signal lines, wherein the signal lines may be high-speed signal lines such as clock lines, data lines, address lines, etc.

[0064] The first signal routing 115 routed on the second wiring layer L2 uses the ground plane of the first wiring layer L1 as a reference plane. The second wiring layer L2 is used to provide a signal path for the signal of the first signal routing 115. The ground plane of the first wiring layer L1 is used to provide a return path for the signal of the first signal routing 115, thereby ensuring the signal integrity of the first signal routing 115. In addition, since the ground plane of the first wiring layer L1 is arranged on the surface layer of the circuit board 11, it can shield the signal of the first signal routing 115, which is beneficial to control electromagnetic radiation.

[0065] The second signal trace 116 is used to connect the processor pad 112 and the second memory pad 114. Figures 2 to 5 As shown, the second signal line 116 is routed on the third circuit layer L3. After the second memory 141 is installed on the second memory base 142, the second signal line 116 transmits high-speed signals between the processor 12 and the second memory 141 on the third circuit layer L3.

[0066] like Figure 6 As shown, the second signal wiring 116 includes a variety of signal lines, wherein the signal lines may be high-speed signal lines such as clock lines, data lines, address lines, etc.

[0067] The second signal routing 116 routed on the third wiring layer L3 uses the ground plane of the fourth wiring layer L4 as a reference plane. The third wiring layer L3 is used to provide a signal path for the signal of the second signal routing 116. The ground plane of the fourth wiring layer L4 is used to provide a return path for the signal of the second signal routing 116, thereby ensuring the signal integrity of the second signal routing 116. In addition, since the ground plane of the fourth wiring layer L4 is arranged on the surface layer of the circuit board 11, it can shield the signal of the second signal routing 116, which is beneficial to control electromagnetic radiation.

[0068] On the one hand, this embodiment sets the device pads (processor pads 112, first memory pads 113, and second memory pads 114) on a circuit layer (first circuit layer L1 or fourth circuit layer L4) that can provide a reference plane for the signal, without setting an additional circuit layer to provide a reference plane for the signal, which can reduce the number of circuit layers of the circuit board and help reduce the cost and height of the circuit board. On the other hand, the circuit layers used to provide a reference plane for the signal are all set on the surface of the circuit board 11, which is conducive to placing the processor 12, the first memory component 13, and the second memory component 14, and is also conducive to shielding the high-speed signal transmitted in the inner layer of the circuit board 11.

[0069] In general, this embodiment optimizes the structure of the circuit board 11 and reduces the circuit board cost and height by adopting this configuration while meeting various index requirements.

[0070] In some embodiments, the first memory pad 113 includes a first signal pin and a first ground pin, the first signal pin is electrically connected to the first signal trace 115 , and the first ground pin is electrically connected to the ground plane of the circuit layer where the first memory pad 113 is located.

[0071] For example, when the circuit layer where the first memory pad 113 is located is the first circuit layer L1, the first ground pin is electrically connected to the ground plane of the first circuit layer L1. When the circuit layer where the first memory pad 113 is located is the fourth circuit layer L4, the first ground pin is electrically connected to the ground plane of the fourth circuit layer L4.

[0072] When the first memory base 132 is mounted, the first signal pin is electrically connected to the signal pin of the first memory base 132 , and the first ground pin is electrically connected to the ground pin of the first memory base 132 .

[0073] The first signal pin may include any type of signal pin such as a clock signal pin, a clock enable signal pin, a chip select signal pin, etc., which is not limited here.

[0074] The first ground pin is used to form a complete reference plane together with the ground plane of the circuit layer where the first memory pad 113 is located, thereby providing a more ideal return path for the signal of the first signal line 115 routed on the second circuit layer L2, thereby facilitating improving signal quality.

[0075] In some embodiments, the second memory pad 114 includes a second signal pin and a second ground pin, the second signal pin is electrically connected to the second signal trace 116 , and the second ground pin is electrically connected to the ground plane of the circuit layer where the second memory pad 114 is located.

[0076] For example, when the circuit layer where the second memory pad 114 is located is the first circuit layer L1, the second ground pin is electrically connected to the ground plane of the first circuit layer L1; when the circuit layer where the second memory pad 114 is located is the fourth circuit layer L4, the second ground pin is electrically connected to the ground plane of the fourth circuit layer L4.

[0077] When the second memory base 142 is mounted, the second signal pin is electrically connected to the signal pin of the second memory base 142 , and the second ground pin is electrically connected to the ground pin of the second memory base 142 .

[0078] The second signal pin may include any type of signal pin such as a clock signal pin, a clock enable signal pin, a chip select signal pin, etc., which is not limited here.

[0079] The second ground pin is used to form a complete reference plane together with the ground plane of the circuit layer where the second memory pad 114 is located, thereby providing a more ideal return path for the signal of the second signal line 116 routed on the third circuit layer L3, thereby facilitating improving signal quality.

[0080] In some embodiments, please refer to Figures 2 to 5 The first circuit layer L1, the second circuit layer L2, the third circuit layer L3 or the fourth circuit layer L4 is provided with a plurality of first vias 112a corresponding to the processor pad 112, a plurality of second vias 113a corresponding to the first memory pad 113 and a plurality of third vias 114a corresponding to the second memory pad 114.

[0081] The first signal trace 115 connects the processor pad 112 and the first memory pad 113 through the first via 112 a , the second wiring layer L2 , and the second via 113 a .

[0082] If the first memory pad 113 is disposed on the first circuit layer L1, Figure 2 and Figure 4As shown, the first signal trace 115 is electrically connected to the processor pad 112 in the first circuit layer L1, is routed in the second circuit layer L2 after passing through the first via 112a, and is electrically connected to the first memory pad 113 in the first circuit layer L1 after passing through the second via 113a.

[0083] If the first memory pad 113 is disposed on the fourth circuit layer L4, Figure 3 and Figure 5 As shown, the first signal trace 115 is electrically connected to the processor pad 112 in the first circuit layer L1, passes through the first via 112a and then is routed in the second circuit layer L2, and passes through the second via 113a and then is electrically connected to the first memory pad 113 in the fourth circuit layer L4.

[0084] The second signal trace 116 connects the processor pad 112 and the second memory pad 114 through the first via 112 a , the third wiring layer L3 , and the second via 113 a .

[0085] If the second memory pad 114 is disposed on the first circuit layer L1, Figure 2 and Figure 5 As shown, the second signal trace 116 is electrically connected to the processor pad 112 in the first circuit layer L1, is routed in the third circuit layer L3 after passing through the first via 112a, and is electrically connected to the second memory pad 114 in the first circuit layer L1 after passing through the third via 114a.

[0086] If the second memory pad 114 is disposed on the fourth circuit layer L4, Figure 3 and Figure 4 As shown, the second signal trace 116 is electrically connected to the processor pad 112 in the first circuit layer L1, is routed in the third circuit layer L3 after passing through the first via 112a, and is electrically connected to the second memory pad 114 in the fourth circuit layer L4 after passing through the third via 114a.

[0087] In some embodiments, the circuit board 11 also includes power traces.

[0088] The power trace is electrically connected to the processor pad 112 , the power pin of the first memory pad 113 , and the power pin of the second memory pad 114 , and is used to supply power to the processor 12 , the first memory 131 , and the second memory 141 , respectively.

[0089] The power supply wiring may be disposed on the first circuit layer L1 or on the fourth circuit layer L4.

[0090] By setting the power supply wiring on the first circuit layer L1 or the fourth circuit layer L4 as the reference plane, there is no need to set an additional circuit layer on the circuit board 11 for the power supply wiring, which is beneficial to further optimize the structure of the circuit board 11.

[0091] In some embodiments, see Figure 7 A first insulating dielectric layer 1111 is disposed between the first circuit layer L1 and the second circuit layer L2, and a thickness of the first insulating dielectric layer 1111 is less than or equal to a minimum spacing required for the ground plane of the first circuit layer L1 to shield the signal of the first signal line 115 routed in the second circuit layer L2.

[0092] The first insulating dielectric layer 1111 is used to maintain insulation between the circuits of the first circuit layer L1 and the circuits of the second circuit layer L2 to ensure safe operation of the circuit. In some embodiments, the thickness of the first insulating dielectric layer 1111 is in the range of 2.7 mils to 5 mils.

[0093] like Figure 7 As shown, a second insulating dielectric layer 1112 is arranged between the third circuit layer L3 and the fourth circuit layer L4, and the thickness of the second insulating dielectric layer 1112 is less than or equal to the minimum spacing requirement that the ground plane of the fourth circuit layer L4 shields the signal of the second signal line 116 routed in the third circuit layer L3.

[0094] The second insulating dielectric layer 1112 is used to maintain insulation between the circuits of the third circuit layer L3 and the circuits of the fourth circuit layer L4 to ensure safe operation of the circuit. In some embodiments, the thickness of the second insulating dielectric layer 1112 is in the range of 2.7 mils to 5 mils.

[0095] like Figure 7 As shown, a third insulating dielectric layer 1113 is arranged between the second circuit layer L2 and the third circuit layer L3, and the thickness of the third insulating dielectric layer 1113 is greater than or equal to the minimum spacing that satisfies the requirement that the signal of the first signal wiring 115 routed on the second circuit layer L2 and the signal of the second signal wiring 116 routed on the third circuit layer L3 do not affect each other.

[0096] The third insulating dielectric layer 1113 is used to prevent the signal of the first signal line 115 routed on the second line layer L2 from affecting the signal of the second signal line 116 routed on the third line layer L3, thereby improving the signal quality of the two signals.

[0097] In some embodiments, the thickness of the third insulating dielectric layer 1113 is 51 mils.

[0098] In some embodiments, the first insulating dielectric layer 1111 , the second insulating dielectric layer 1112 , or the third insulating dielectric layer 1113 may be made of any suitable insulating coating material, such as glass fiber epoxy resin, polyurethane, silicone, polyparaxylene, acrylic resin, etc.

[0099] As another embodiment of the present invention, the embodiment of the present invention provides an electronic device, and the electronic device includes the electronic mainboard 100 as described above.

[0100] Finally, it should be noted that the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. These embodiments are not intended to be additional limitations on the content of the present invention. The purpose of providing these implementations is to make the understanding of the disclosure of the present invention more thorough and comprehensive. In addition, under the idea of ​​the present invention, the above-mentioned technical features continue to be combined with each other, and there are many other changes in different aspects of the present invention as described above, which are all considered to be within the scope of the present invention specification; further, for ordinary technicians in this field, they can be improved or transformed according to the above description, and all these improvements and transformations should belong to the scope of protection of the claims attached to the present invention.

Claims

1. A circuit board, characterized in that: include: The substrate comprises a first circuit layer, a second circuit layer, a third circuit layer and a fourth circuit layer which are stacked, wherein the first circuit layer and the fourth circuit layer are both paved with a ground plane; A processor pad is arranged on the first circuit layer; A first memory pad is disposed on the first circuit layer or the fourth circuit layer; A second memory pad is disposed on the first circuit layer or the fourth circuit layer; A first signal routing line, used to connect the processor pad and the first memory pad, the first signal routing line is routed on the second circuit layer, and a signal of the first signal routing line uses a ground plane of the first circuit layer as a reference plane; The second signal routing is used to connect the processor pad and the second memory pad. The second signal routing is routed on the third circuit layer. The signal of the second signal routing uses the ground plane of the fourth circuit layer as a reference plane.

2. The circuit board according to claim 1, characterized in that: The first circuit layer, the second circuit layer, the third circuit layer or the fourth circuit layer is provided with a plurality of first via holes corresponding to the processor pads, a plurality of second via holes corresponding to the first memory pads and a plurality of third via holes corresponding to the second memory pads; The first signal trace connects the processor pad and the first memory pad through the first via, the second circuit layer and the second via; The second signal trace connects the processor pad and the second memory pad through the first via, the third circuit layer, and the third via.

3. The circuit board according to claim 2, characterized in that: If the first memory pad and the second memory pad are both set in the first circuit layer, the first signal routing is electrically connected to the processor pad in the first circuit layer, and is routed in the second circuit layer after passing through the first via, and is electrically connected to the first memory pad in the first circuit layer after passing through the second via; the second signal routing is electrically connected to the processor pad in the first circuit layer, and is routed in the third circuit layer after passing through the first via, and is electrically connected to the second memory pad in the first circuit layer after passing through the third via.

4. The circuit board according to claim 2, characterized in that: If the first memory pad and the second memory pad are both arranged in the fourth circuit layer, the first signal routing is electrically connected to the processor pad in the first circuit layer, is routed in the second circuit layer after passing through the first via hole, and is electrically connected to the first memory pad in the fourth circuit layer after passing through the second via hole; the second signal routing is electrically connected to the processor pad in the first circuit layer, is routed in the third circuit layer after passing through the first via hole, and is electrically connected to the second memory pad in the fourth circuit layer after passing through the third via hole.

5. The circuit board according to claim 2, characterized in that: If the first memory pad is set on the first circuit layer and the second memory pad is set on the fourth circuit layer, the first signal routing is electrically connected to the processor on the first circuit layer, is routed on the second circuit layer after passing through the first via, and is electrically connected to the first memory pad on the first circuit layer after passing through the second via; the second signal routing is electrically connected to the processor pad on the first circuit layer, is routed on the third circuit layer after passing through the first via, and is electrically connected to the second memory pad on the fourth circuit layer after passing through the third via.

6. The circuit board according to claim 1, characterized in that: The first memory pad includes a first ground pin, the first ground pin is electrically connected to a ground plane of the circuit layer where the first memory pad is located, and the first ground pin and the ground plane of the circuit layer where the first memory pad is located constitute a complete reference plane; The second memory pad includes a second ground pin, the second ground pin is electrically connected to a ground plane of the circuit layer where the second memory pad is located, and the second ground pin and the ground plane of the circuit layer where the second memory pad is located constitute a complete reference plane.

7. The circuit board according to claim 1, characterized in that: It also includes power routing; The power supply wiring is arranged in the first circuit layer and / or the fourth circuit layer.

8. The circuit board according to claim 1, characterized in that: A first insulating dielectric layer is provided between the first circuit layer and the second circuit layer, and a thickness of the first insulating dielectric layer is less than or equal to a minimum spacing that satisfies a requirement that a ground plane of the first circuit layer shields a signal of a first signal line routed on the second circuit layer; A second insulating dielectric layer is disposed between the third circuit layer and the fourth circuit layer, and a thickness of the second insulating dielectric layer is less than or equal to a minimum spacing required for the ground plane of the fourth circuit layer to shield a signal of a second signal line routed in the third circuit layer.

9. The circuit board according to claim 8, characterized in that: A third insulating dielectric layer is arranged between the second circuit layer and the third circuit layer, and the thickness of the third insulating dielectric layer is greater than or equal to the minimum spacing that satisfies the requirement that the signal of the first signal line routed in the second circuit layer and the signal of the second signal line routed in the third circuit layer do not affect each other.

10. An electronic mainboard, characterized in that: Comprising the circuit board as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: Comprising the electronic mainboard as claimed in claim 10.

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