P-channel gallium nitride device, preparation method thereof and electronic equipment

Abstract

The invention provides a P-channel gallium nitride device, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductor devices. By setting the first etching self-stop layer as the etching stop interface of the P-type channel, the influence on the main P-type channel layer when the first P-type channel layer is etched is avoided, the high quality of the surface of the main P-type channel layer at the gate groove is ensured, the required etching depth of the P-type channel can be ensured to conform to the expectation, and the etching efficiency of the P-type channel is improved. And the thickness of the P-type channel under the gate structure is effectively controlled, so that the performance of the P-type channel gallium nitride device is improved. Especially when the P-type channel gallium nitride devices are prepared on a large scale, the etching stop interfaces of all the P-type channel gallium nitride devices are the same when the P-type channel etching is carried out, the condition that the P-type channel etching depths are not uniform when different P-type channel gallium nitride devices are prepared is improved, and the preparation yield is improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a P-channel gallium nitride device and a preparation method thereof and an electronic device. Background Art

[0002] GaN material has a large bandgap and a high breakdown electric field, making it an ideal candidate material for the next generation of high-frequency and high-power switching applications. Currently, most commercially available GaN transistors are discrete N-channel GaN power transistors, and their switching frequency is often limited by parasitic inductance in the circuit board layout.

[0003] Therefore, in order to fully realize the full potential of GaN, it is particularly important to develop P-channel GaN power transistors. Summary of the invention

[0004] In view of this, the present application provides a P-channel gallium nitride device and a preparation method and electronic device thereof, which avoids affecting the main P-type channel layer when etching the first P-type channel layer by setting a first etch self-stop layer as an etch stop interface of the P-type channel, and ensures that the surface quality of the main P-type channel layer at the gate groove is high, thereby improving the performance of the P-type channel gallium nitride device. In particular, when preparing P-type channel gallium nitride devices on a large scale, the etch stop interface of all P-type channel gallium nitride devices during P-type channel etching is the same, which improves the uneven P-type channel etching depth that occurs when preparing different P-type channel gallium nitride devices, and improves the preparation yield.

[0005] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0006] A method for preparing a P-channel gallium nitride device, comprising:

[0007] providing a substrate;

[0008] Epitaxially growing a buffer layer, an N-type channel layer, a barrier layer, a main P-type channel layer, a first etching self-stop layer and a first P-type channel layer in sequence on the substrate;

[0009] Based on a preset etching gas and using an inductively coupled plasma etching process, etching the gate groove from one side of the first P-type channel layer until the first etching self-stop layer is reached and the etching is stopped, wherein the etching is stopped when the etching stop condition is satisfied based on the plasma etching of the preset etching gas to the first etching self-stop layer;

[0010] removing a corresponding portion of the first etching self-stop layer at the gate groove;

[0011] A source and a drain are formed on a surface of the first P-type channel layer facing away from the substrate, and a gate structure is formed at the gate groove.

[0012] Optionally, after epitaxially growing the main P-type channel layer and before epitaxially growing the first etching self-stop layer, the method further includes:

[0013] At least one pair of etching self-stop layers and P-type channel layers are alternately epitaxially grown on the main P-type channel layer, and are defined as the Nth etching self-stop layer to the second etching word stop layer and the NP-type channel layer to the second P-type channel layer in the order of epitaxial growth, where N is an integer not less than 2;

[0014] Wherein, after removing the corresponding portion of the first etching self-stop layer at the gate groove and before forming the source, the drain and the gate structure, the method further includes:

[0015] Based on a preset etching gas and using an inductively coupled plasma etching process, etching the second P-type channel layer at the gate groove until the etching reaches the second etching self-stop layer and the etching stops, wherein the etching stops when the etching stop condition is satisfied when the plasma etching based on the preset etching gas reaches the second etching self-stop layer;

[0016] removing a corresponding portion of the second etch self-stop layer at the gate groove;

[0017] The same method and steps as above are adopted until the corresponding portion of the i-th etching self-stop layer is removed at the gate groove, where i is an integer not greater than N and not less than 2.

[0018] Optionally, the preset etching gas is a F-based etching gas or an oxygen-containing etching gas, and the material of the corresponding etching self-stop layer is a GaN derivative containing an Al component.

[0019] Optionally, forming a gate structure at the gate groove includes:

[0020] A gate is formed at the gate groove to obtain a Schottky gate P-channel gallium nitride device.

[0021] Optionally, forming a gate structure at the gate groove includes:

[0022] Growing a gate dielectric layer covering at least the inner wall of the gate groove;

[0023] A gate is formed on the gate dielectric layer to obtain a MIS gate P-channel gallium nitride device.

[0024] Optionally, after epitaxially growing the barrier layer and before epitaxially growing the main P-type channel layer, the method further includes:

[0025] A hole supply layer and a barrier insertion layer are epitaxially grown in sequence on the barrier layer, and the hole supply layer, the barrier insertion layer and the main P-type channel layer form a heterojunction structure.

[0026] Based on the same inventive concept, the present application also provides a P-channel gallium nitride device, including:

[0027] substrate;

[0028] A buffer layer, an N-type channel layer, a barrier layer, a main P-type channel layer, a first etch self-stop layer and a first P-type channel layer are located on the substrate and epitaxially grown in sequence, wherein a stack of the first etch self-stop layer and the first P-type channel layer forms a gate groove penetrating the stack;

[0029] A source and a drain are located on a surface of the first P-type channel layer facing away from the substrate, and a gate structure is located at the gate groove.

[0030] Optionally, the layer located between the main P-type channel layer and the first etching self-stop layer also includes:

[0031] At least one pair of etch self-stop layers and P-type channel layers alternately grown epitaxially on the P-type channel layer, and defined in sequence as the Nth etch self-stop layer to the second etch word stop layer and the NP-type channel layer to the second P-type channel layer in the order of epitaxial growth, where N is an integer not less than 2;

[0032] The gate groove penetrates the stack from the i-th etching stop layer to the first P-type channel layer, and i is an integer not greater than N and not less than 2.

[0033] Optionally, the layer between the barrier layer and the main P-type channel layer further includes:

[0034] A hole supply layer and a barrier insertion layer are sequentially epitaxially grown on the barrier layer, and the hole supply layer, the barrier insertion layer and the main P-type channel layer form a heterojunction structure.

[0035] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned P-channel gallium nitride device.

[0036] Compared with the prior art, the technical solution provided by this application has at least the following advantages:

[0037] The present application provides a P-channel gallium nitride device and a preparation method thereof and an electronic device, the preparation method comprising: providing a substrate; epitaxially growing a buffer layer, an N-type channel layer, a barrier layer, a main P-type channel layer, a first etching self-stop layer and a first P-type channel layer on the substrate in sequence; etching a gate groove from one side of the first P-type channel layer based on a preset etching gas and using an inductively coupled plasma etching process until the etching is stopped when the first etching self-stop layer is etched, wherein the etching is stopped when the etching stop condition is met when the plasma etching based on the preset etching gas reaches the first etching self-stop layer; removing a corresponding portion of the first etching self-stop layer at the gate groove; forming a source and a drain on the surface of the first P-type channel layer on a side away from the substrate, and forming a gate structure at the gate groove.

[0038] As can be seen from the above content, the technical solution provided by the present application, by setting the first etch self-stop layer as the etch stop interface of the P-type channel, avoids the influence on the main P-type channel layer when etching the first P-type channel layer, ensures the high quality of the surface of the main P-type channel layer at the gate groove, and at the same time ensures that the required etching depth of the P-type channel meets expectations, effectively controls the thickness of the P-type channel under the gate structure, thereby improving the performance of the P-type channel gallium nitride device. In particular, when preparing P-type channel gallium nitride devices on a large scale, the etching stop interface of all P-type channel gallium nitride devices during P-type channel etching is the same, which improves the uneven etching depth of the P-type channel that occurs when preparing different P-type channel gallium nitride devices, and improves the preparation yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0040] Figure 1 A flow chart of a method for preparing a P-channel gallium nitride device provided in an embodiment of the present application;

[0041] Figure 2a to Figure 2e for Figure 1 The structural schematic diagram corresponding to each step in the figure;

[0042] Figure 3 A schematic diagram of the structure of a P-channel gallium nitride device provided in an embodiment of the present application;

[0043] Figure 4 A flow chart of another method for preparing a P-channel gallium nitride device provided in an embodiment of the present application;

[0044] Figure 5 A schematic diagram of the structure of another P-channel gallium nitride device provided in an embodiment of the present application;

[0045] Figure 6 A schematic diagram of the structure of another P-channel gallium nitride device provided in an embodiment of the present application;

[0046] Figure 7 A schematic structural diagram of another P-channel gallium nitride device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] As mentioned in the background technology, GaN materials have a large bandgap and a high breakdown electric field, making them ideal candidates for next-generation high-frequency and high-power switching applications. Currently, most commercially available GaN transistors are discrete N-channel GaN power transistors, whose switching frequency is often limited by parasitic inductance in the circuit board layout. Therefore, in order to fully tap the full potential of GaN, it is particularly important to develop P-channel GaN power transistors.

[0049] In GaN power integrated circuits, GaN complementary logic circuits composed of N-channel GaN devices and P-channel GaN devices are the basic units of gate drive circuits and other functional circuits. N-channel devices are mainly electron-conductive, while P-channel devices are mainly hole-conductive. With the presence of high-density and high-mobility two-dimensional electron gas (2DEG) on the surface of AlGaN / GaN heterojunction, N-channel GaN devices made based on this structure have gradually been used in the field of high-voltage and high-frequency switching. However, due to factors such as low hole mobility and high acceptor activation energy, P-channel GaN devices have always had a lower current density.

[0050] In addition, in the manufacture of enhanced P-channel GaN devices, trench gate technology has gradually become the mainstream. After etching to form a gate groove, a dielectric layer can be deposited to make an MIS (metal-insulator-semiconductor) gate or a metal can be directly evaporated to form a Schottky gate. The P-type GaN channel under the gate is depleted under zero gate bias, that is, the enhanced operation mode is achieved. When using gate dry etching to manufacture P-channel GaN devices, the thickness of the channel layer reserved under the gate has a great influence on the performance of the device. A thicker channel layer will make the device unable to achieve enhanced operation mode, and the gate control ability will be reduced; while deeper etching will enhance the gate control ability, but it will cause the on-resistance of the device to increase and the current density to decrease. In addition, the plasma generated during dry etching will bombard the etched surface, thereby deteriorating the etching interface quality of the P-type channel layer and affecting the performance of the device.

[0051] Based on this, the embodiment of the present application provides a P-channel gallium nitride device and a preparation method and electronic device thereof, which avoids affecting the main P-type channel layer when etching the first P-type channel layer by setting a first etch self-stop layer as an etch stop interface of the P-type channel, and ensures that the surface quality of the main P-type channel layer at the gate groove is high, thereby improving the performance of the P-type channel gallium nitride device. In particular, when preparing P-type channel gallium nitride devices on a large scale, the etch stop interface of all P-type channel gallium nitride devices during P-type channel etching is the same, which improves the uneven P-type channel etching depth that occurs when preparing different P-type channel gallium nitride devices, and improves the preparation yield.

[0052] To achieve the above purpose, the technical solution provided in the embodiment of the present application is as follows, specifically combined with Figures 1 to 7 The technical solution provided in the embodiments of the present application is described in detail.

[0053] refer to Figure 1 As shown, it is a flow chart of a method for preparing a P-channel gallium nitride device provided in an embodiment of the present application. A P-channel device is a device that relies on holes for conduction. When the P-channel device is turned on, holes accumulate in the channel under the gate, and the holes in the P-channel device play a major role in conduction. The preparation method includes:

[0054] S1. Provide a substrate.

[0055] S2. epitaxially growing a buffer layer, an N-type channel layer, a barrier layer, a main P-type channel layer, a first etching self-stop layer and a first P-type channel layer in sequence on the substrate.

[0056] S3. Based on a preset etching gas and using an inductively coupled plasma etching process, etching of the gate groove is performed from one side of the first P-type channel layer until the first etching self-stop layer is reached and the etching is stopped, wherein the etching is stopped when the etching stop condition is met based on the plasma etching of the preset etching gas to the first etching self-stop layer.

[0057] S4. Removing a corresponding portion of the first etching self-stop layer at the gate groove.

[0058] S5. Form a source and a drain on a surface of the first P-type channel layer facing away from the substrate, and form a gate structure in the gate groove.

[0059] It can be understood that the technical solution provided in the embodiment of the present application, when the plasma of the preset etching gas etches to the first etching self-stop layer, the etching stops when the etching stop condition is met, and the etching self-stop process can be completed without adding etching control related processes, thereby reducing the difficulty of the preparation process. Thus, by setting the first etching self-stop layer as the etching stop interface of the P-type channel, the main P-type channel layer is avoided from being affected when the first P-type channel layer is etched, and the surface quality of the main P-type channel layer at the gate groove is ensured to be high. At the same time, it can also ensure that the required etching depth of the P-type channel meets expectations, and effectively control the thickness of the P-type channel under the gate structure, thereby improving the performance of the P-type channel gallium nitride device. In particular, when preparing P-type channel gallium nitride devices on a large scale, the etching stop interface of all P-type channel gallium nitride devices during P-type channel etching is the same, which improves the uneven etching depth of the P-type channel that occurs when preparing different P-type channel gallium nitride devices, and improves the preparation yield.

[0060] The following is a more detailed description of the technical solution provided by the embodiment of the present application in combination with the device structure corresponding to each step in the preparation method. Figure 2a to Figure 2e As shown, Figure 1 Schematic diagram of the corresponding structure of each step.

[0061] like Figure 2a As shown, corresponding to step S1, a substrate 100 is provided. The material of the substrate 100 can be Si, sapphire, GaN, etc.

[0062] like Figure 2bAs shown, corresponding to step S2, a buffer layer 200, an N-type channel layer 300, a barrier layer 400, a main P-type channel layer 500, a first etching self-stop layer 610 and a first P-type channel layer 710 are sequentially epitaxially grown on the substrate 100. The material of the N-type channel layer 300 can be GaN, InGaN or the like, which can produce a polarization effect with the barrier layer 400; and the material of the barrier layer 400 can be AlGaN, AlN, AlInGaN or the like, which can produce a polarization effect with the N-type channel layer 300, and the bandgap width of the barrier layer 400 is greater than the bandgap width of the N-type channel layer 300. A polarization effect is generated between the N-type channel layer 300 and the barrier layer 400, so that a high concentration of two-dimensional electron gas is generated at the interface between the two. For example, when the material of the N-type channel layer 300 is GaN and the material of the barrier layer 400 is AlGaN, because the bandgap widths of AlGaN and GaN materials are different, the bandgap width of GaN is lower than that of AlGaN, and there is a deviation between the bottoms of the conduction bands of the two. The energy band bending leads to the formation of a two-dimensional potential well at the heterojunction interface. The two-dimensional potential well will limit the movement of polarized electrons in the direction perpendicular to the abrupt heterojunction. These electrons can only move in two dimensions along the plane parallel to the abrupt junction interface in the potential well, so it is called a two-dimensional electron gas. The main P-type channel layer 500 can be a GaN layer doped with Mg or C, an InGaN layer, etc. The material of the first etching self-stop layer 610 can be a GaN derivative containing Al components such as AlGaN, AlN, AlInGaN, etc. And, the first P-type channel layer 700 can be a GaN layer doped with Mg or C, an InGaN layer, etc.

[0063] like Figure 2c As shown, corresponding to step S3, based on the preset etching gas and using the inductively coupled plasma etching process, the gate groove 10 is etched from the first P-type channel layer 710 side until the first etching self-stop layer 610 is etched and the etching is stopped, wherein the etching stop condition is satisfied when the first etching self-stop layer 610 is etched based on the plasma of the preset etching gas. The etching stop condition may include that the plasma of the etching gas can react with the etching self-stop layer and form a non-volatile protective film on the surface of the etching self-stop layer, thereby making it impossible for the plasma of the etching gas to etch the etching self-stop layer and the etching stops; and the etching stop condition may also include that the plasma of the etching gas has a high selectivity etching characteristic, and the etching rate of the plasma of the etching gas to the etching self-stop layer is lower than the etching rate to the P-type channel layer and the etching stops.

[0064] Optionally, the preset etching gas provided in the embodiment of the present application is a F-based etching gas or an oxygen-containing etching gas, and the material of the corresponding etching self-stop layer is a GaN derivative containing an Al component, and the material of the P-type channel layer to be etched is various epitaxial materials that provide hole conductivity and do not contain an Al component, such as the material of the first P-type channel layer 710 is various epitaxial materials that provide hole conductivity and do not contain an Al component; and since the main P-type channel layer 500 does not need to be etched, it can be various epitaxial materials that improve hole conductivity. For example, when the etching gas is SF6 gas, when SF6 gas performs plasma etching on the structural layer of the GaN derivative containing an Al component, a layer of non-volatile AlF3 film will be formed on the surface of the structural layer of the GaN derivative containing an Al component, thereby protecting the structural layer of the GaN derivative containing an Al component from being etched. Or the etching gas is an oxygen-containing etching gas. When the oxygen-containing etching gas performs plasma etching on the structural layer of the GaN derivative containing Al component, the etching rate will drop suddenly. The etching rate of the oxygen-containing etching gas on the structural layer of the GaN derivative containing Al component is much lower than the etching rate on the P-type channel layer.

[0065] like Figure 2d As shown, corresponding to step S4, the corresponding portion of the first etching self-stop layer 610 is removed at the gate groove 10. Specifically, the corresponding portion of the first etching self-stop layer 610 corresponding to the gate groove 10 can be removed by a wet or dry etching process. The main P-type channel layer 500 provided in the embodiment of the present application does not need to be etched, so it can be designed to have an expected thickness and doping, thereby achieving the purpose of regulating the threshold voltage of the P-channel gallium nitride device. Similarly, due to the existence of the etching self-stop layer, there is no need to consider the control of the etching depth of the P-type channel layer when etching the P-type channel layer, so the first P-type channel layer 710 can be designed to have an expected thickness and doping to meet the device performance requirements.

[0066] like Figure 2e As shown, corresponding to step S5, a source electrode 810 and a drain electrode 820 are formed on the surface of the first P-type channel layer 710 facing away from the substrate 100, and a gate structure 830 is formed at the gate groove 10. The source electrode 810 and the drain electrode 820 are respectively located on both sides of the gate structure 830. Optionally, the source electrode 810, the drain electrode 820 and the gate provided in the embodiment of the present application can be prepared by photolithography and stripping processes, and the present application does not make specific restrictions on this.

[0067] Continue to refer Figure 2e As shown, the gate structure 830 provided in the embodiment of the present application can be prepared as a Schottky gate, that is, the gate structure 830 is formed at the gate groove 10, including: forming a gate 831 at the gate groove 10 to obtain a Schottky gate P-channel gallium nitride device. Or refer to Figure 3 , which is a schematic diagram of the structure of a P-channel gallium nitride device provided in an embodiment of the present application, wherein the gate structure 830 provided in the embodiment of the present application may be a MIS gate, that is, the gate structure is formed at the gate groove 10, including: growing a gate dielectric layer 832 covering at least the inner wall of the gate groove 10; forming a gate 831 on the gate dielectric layer 832 to obtain a MIS gate P-channel gallium nitride device. The material of the gate dielectric layer 832 may be Al2O3, SiO2, SiN x The P-channel gallium nitride device provided in the embodiment of the present application prepares the gate structure 830 as a trench gate structure, and can deposit a dielectric layer 832 to make an MIS gate or directly evaporate a metal to form a Schottky gate, and deplete the P-type channel under the gate 831 under zero gate bias, that is, to achieve an enhanced operation mode.

[0068] In order to further improve the performance of the P-channel GaN device, the P-channel GaN device can also be optimized by setting the structural layer. Figure 4 As shown, it is a flow chart of another method for preparing a P-channel gallium nitride device provided in an embodiment of the present application. In step S2, after epitaxially growing the barrier layer and before epitaxially growing the main P-type channel layer, it also includes: epitaxially growing a hole supply layer and a barrier insertion layer on the barrier layer in sequence, and the hole supply layer, the barrier insertion layer and the main P-type channel layer form a heterojunction structure; wherein the hole supply layer can be a P-type GaN layer or an InGaN layer, and the barrier insertion layer can be an AlN layer or an AlInN layer. That is, step S2 is to epitaxially grow a buffer layer, an N-type channel layer, a barrier layer, a hole supply layer, a barrier insertion layer, a main P-type channel layer, a first etching self-stop layer and a first P-type channel layer on the substrate in sequence, wherein the hole supply layer, the barrier insertion layer and the main P-type channel layer form a heterojunction structure, which can not only increase the channel hole concentration and the current density of the P-channel gallium nitride device through the heterojunction structure, but also reduce the resistance at the P-type channel through the barrier insertion layer, thereby further improving the performance of the P-channel gallium nitride device.

[0069] like Figure 5 FIG. 1 is a schematic diagram of the structure of another P-channel gallium nitride device provided in an embodiment of the present application, wherein Figure 5 The structure shown can be adopted Figure 4The Schottky gate P-channel gallium nitride device prepared by the preparation method provided includes a substrate 10, a buffer layer 200, an N-type channel layer 300, a barrier layer 400, a hole supply layer 910, a barrier insertion layer 920, a main P-type channel layer 500, a first etching self-stop layer 610 and a first P-type channel layer 710, a gate groove runs through the stack of the first etching self-stop layer 610 and the first P-type channel layer 710, and a metal is directly evaporated at the gate groove to form a gate 831 to form a Schottky gate P-channel gallium nitride device. In addition, a source 810 and a drain 820 are arranged on both sides of the gate 831 and are located on the surface of the first P-type channel layer 710. Among them, the hole supply layer 910, the barrier insertion layer 920 and the main P-type channel layer 500 form a heterojunction structure.

[0070] like Figure 6 FIG. 1 is a schematic diagram of the structure of another P-channel gallium nitride device provided in an embodiment of the present application, wherein Figure 6 The structure shown can be adopted Figure 4 The MIS gate P-channel gallium nitride device prepared by the provided preparation method includes a substrate 10, a buffer layer 200, an N-type channel layer 300, a barrier layer 400, a hole supply layer 910, a barrier insertion layer 920, a main P-type channel layer 500, a first etching self-stop layer 610 and a first P-type channel layer 710, a gate groove runs through the stack of the first etching self-stop layer 610 and the first P-type channel layer 710, a gate dielectric layer 832 is formed at the gate groove, and a gate 831 is formed on the surface of the gate dielectric layer 832 to form a MIS gate P-channel gallium nitride device. In addition, a source 810 and a drain 820 are arranged on both sides of the gate 831 and are located on the surface of the first P-type channel layer 710. Among them, the hole supply layer 910, the barrier insertion layer 920 and the main P-type channel layer 500 form a heterojunction structure.

[0071] In one embodiment of the present application, the preparation method provided by the present application, after epitaxially growing the main P-type channel layer and before epitaxially growing the first etching self-stop layer, further includes: alternately epitaxially growing at least one pair of etching self-stop layers and P-type channel layers on the main P-type channel layer, and sequentially defined as the Nth etching self-stop layer to the second etching word stop layer and the NP-type channel layer to the second P-type channel layer in the order of epitaxial growth, wherein the Nth etching self-stop layer is grown on the main P-type channel layer, and the first etching self-stop layer is epitaxially grown on the second P-type channel layer, and N is an integer not less than 2; wherein, the corresponding portion of the first etching self-stop layer is removed at the gate groove. After the division, and before the formation of the source, the drain and the gate structure, it also includes: based on a preset etching gas and using an inductively coupled plasma etching process, etching the second P-type channel layer at the gate groove until the etching reaches the second etching self-stop layer and the etching is stopped, wherein the etching is stopped when the etching stop condition is met when the plasma etching based on the preset etching gas reaches the second etching self-stop layer; removing the corresponding part of the second etching self-stop layer at the gate groove; using the same method steps as above until the removal of the corresponding part of the i-th etching self-stop layer at the gate groove is completed, and i is an integer not greater than N and not less than 2.

[0072] It can be understood that when the preparation method provided in the embodiment of the present application is prepared with multiple etching self-stop layers, the thickness of any etching self-stop layer can be about 3nm. Since the P-channel gallium nitride device needs to pass through one more heterojunction to achieve conduction when it is forward-conducting, and passing through one more heterojunction means that there will be a larger on-resistance, so the thinner first etching self-stop layer can reduce the voltage drop on the heterojunction, but the thicker first etching self-stop layer can achieve a better etching self-stop process. At the same time, since the etching self-stop layer contains Al elements, the band gap is large, and the polarization effect generated will increase the hole density of the P-type channel layer on the upper side of the etching self-stop layer, and promote the ionization of holes in the lower P-type channel. In addition, since the thickness of the P-type channel under the gate structure is directly related to the gate control ability, on-resistance and current density, by setting multiple etching self-stop layers, the thickness of the P-type channel under the prepared gate structure can be flexibly selected when preparing the device, and finally the purpose of flexibly controlling the device performance is achieved. Optionally, when the preparation method provided in the embodiment of the present application forms multiple etching self-stop layers, after the corresponding portion of the i-th etching self-stop layer corresponding to the gate groove is etched away, the inner wall of the gate groove can be formed into a step shape, that is, the size of the stacking removal of the i-1th etching self-stop layer and the i-1th P-type channel layer is greater than the size of the i-th etching self-stop layer and the i-th P-type channel layer, and finally a step-shaped gate structure is prepared to improve the performance of the P-channel gallium nitride device. Figure 7In the structure of the P-channel gallium nitride device shown, the size of the stack removed by the first etch self-stop layer 610 and the first P-type channel layer 710 is larger than the size of the stack removed by the second etch self-stop layer 620 and the second P-type channel layer 720, and the gate structure 830 is formed to have a stepped shape.

[0073] Based on the same inventive concept, the embodiment of the present application further provides a P-channel gallium nitride device, which is prepared by the preparation method provided in any of the above embodiments. Figure 3 As shown, the P-channel gallium nitride device provided in the embodiment of the present application includes: a substrate 10; a buffer layer 200, an N-type channel layer 300, a barrier layer 400, a main P-type channel layer 500, a first etch self-stop layer 610 and a first P-type channel layer 710 located on the substrate 10 and epitaxially grown in sequence, wherein the stack of the first etch self-stop layer 610 and the first P-type channel layer 710 forms a gate groove 10 that penetrates the stack; a source 810 and a drain 820 located on the surface of the first P-type channel layer 710 on the side away from the substrate 100, and a gate structure 830 located at the gate groove 10.

[0074] Continue to refer Figure 3 As shown, the P-channel gallium nitride device provided in the embodiment of the present application can be a MIS-gate P-channel gallium nitride device, wherein at least the inner wall of the gate groove 10 is covered with a gate dielectric layer 832; a gate 831 is formed on the gate dielectric layer 832 to obtain a MIS-gate P-channel gallium nitride device. Or refer to Figure 2e As shown, the P-channel gallium nitride device provided in the embodiment of the present application can also be a Schottky gate P-channel gallium nitride device, and the gate 831 is directly formed at the gate groove 10 to obtain a Schottky gate P-channel gallium nitride device.

[0075] In order to further improve the performance of the P-channel GaN device, the P-channel GaN device may also be provided with an optimized structural layer. Optionally, between the barrier layer and the main P-type channel layer, there is also included: a hole supply layer and a barrier insertion layer epitaxially grown sequentially on the barrier layer, wherein the hole supply layer, the barrier insertion layer and the main P-type channel layer form a heterojunction structure. Figure 5The Schottky gate P-channel gallium nitride device shown includes a substrate 10, a buffer layer 200, an N-type channel layer 300, a barrier layer 400, a hole supply layer 910, a barrier insertion layer 920, a main P-type channel layer 500, a first etching self-stop layer 610 and a first P-type channel layer 710, a gate groove runs through the stack of the first etching self-stop layer 610 and the first P-type channel layer 710, and a metal is directly evaporated at the gate groove to form a gate 831, so as to form a Schottky gate P-channel gallium nitride device. In addition, a source 810 and a drain 820 are arranged on both sides of the gate 831 and are located on the surface of the first P-type channel layer 710. Among them, the hole supply layer 910, the barrier insertion layer 920 and the main P-type channel layer 500 form a heterojunction structure.

[0076] Or refer to Figure 6 The MIS gate P-channel gallium nitride device shown includes a substrate 10, a buffer layer 200, an N-type channel layer 300, a barrier layer 400, a hole supply layer 910, a barrier insertion layer 920, a main P-type channel layer 500, a first etching self-stop layer 610 and a first P-type channel layer 710, a gate groove runs through the stack of the first etching self-stop layer 610 and the first P-type channel layer 710, a gate dielectric layer 832 is formed at the gate groove, and a gate 831 is formed on the surface of the gate dielectric layer 832 to form a MIS gate P-channel gallium nitride device. In addition, a source 810 and a drain 820 are arranged on both sides of the gate 831 and are located on the surface of the first P-type channel layer 710. Among them, the hole supply layer 910, the barrier insertion layer 920 and the main P-type channel layer 500 form a heterojunction structure.

[0077] In an embodiment of the present application, the P-channel gallium nitride device provided in the embodiment of the present application, located between the main P-type channel layer and the first etch self-stop layer, also includes: at least one pair of etch self-stop layers and P-type channel layers alternately grown epitaxially on the P-type channel layer, and are defined in sequence as the Nth etch self-stop layer to the second etch word stop layer and the NP-type channel layer to the second P-type channel layer in the order of epitaxial growth, where N is an integer not less than 2; wherein the gate groove passes through the stack from the i-th etch self-stop layer to the first P-type channel layer, where i is an integer not greater than N and not less than 2.

[0078] It can be understood that when the preparation method provided in the embodiment of the present application is prepared with multiple etching self-stop layers, the thickness of any etching self-stop layer can be about 3nm. Since the P-channel gallium nitride device needs to pass through one more heterojunction to achieve conduction when it is forward-conducting, and passing through one more heterojunction means that there will be a larger on-resistance, so the thinner first etching self-stop layer can reduce the voltage drop on the heterojunction, but the thicker first etching self-stop layer can achieve a better etching self-stop process. At the same time, since the etching self-stop layer contains Al elements, the band gap is large, and the polarization effect generated will increase the hole density of the P-type channel layer on the upper side of the etching self-stop layer, and promote the ionization of holes in the lower P-type channel. In addition, since the thickness of the P-type channel under the gate structure is directly related to the gate control ability, on-resistance and current density, by setting multiple etching self-stop layers, the thickness of the P-type channel under the prepared gate structure can be flexibly selected when preparing the device, and finally the purpose of flexibly controlling the device performance is achieved. Optionally, when the preparation method provided in the embodiment of the present application forms multiple etching self-stop layers, after the corresponding portion of the i-th etching self-stop layer corresponding to the gate groove is etched away, the inner wall of the gate groove can be formed into a step shape, that is, the size of the stacking removal of the i-1th etching self-stop layer and the i-1th P-type channel layer is greater than the size of the i-th etching self-stop layer and the i-th P-type channel layer, and finally a step-shaped gate structure is prepared to improve the performance of the P-channel gallium nitride device. Figure 7 In the structure of the P-channel gallium nitride device shown, the size of the stack removed by the first etch self-stop layer 610 and the first P-type channel layer 710 is larger than the size of the stack removed by the second etch self-stop layer 620 and the second P-type channel layer 720, and the gate structure 830 is formed to have a stepped shape.

[0079] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes the P-channel gallium nitride device provided by any one of the above embodiments.

[0080] The embodiment of the present application provides a P-channel gallium nitride device and a preparation method and an electronic device thereof, the preparation method comprising: providing a substrate; epitaxially growing a buffer layer, an N-type channel layer, a barrier layer, a main P-type channel layer, a first etching self-stop layer and a first P-type channel layer on the substrate in sequence; etching a gate groove from one side of the first P-type channel layer based on a preset etching gas and using an inductively coupled plasma etching process until the etching is stopped when the first etching self-stop layer is etched, wherein the etching is stopped when the etching stop condition is met when the plasma etching based on the preset etching gas reaches the first etching self-stop layer; removing a corresponding portion of the first etching self-stop layer at the gate groove; forming a source and a drain on the surface of the first P-type channel layer on the side away from the substrate, and forming a gate structure at the gate groove.

[0081] As can be seen from the above content, the technical solution provided in the embodiment of the present application, by setting the first etch self-stop layer as the etch stop interface of the P-type channel, avoids the influence on the main P-type channel layer when etching the first P-type channel layer, ensures the high quality of the surface of the main P-type channel layer at the gate groove, and at the same time ensures that the required etching depth of the P-type channel meets expectations, effectively controls the thickness of the P-type channel under the gate structure, thereby improving the performance of the P-type channel gallium nitride device. In particular, when preparing P-type channel gallium nitride devices on a large scale, the etching stop interface of all P-type channel gallium nitride devices during P-type channel etching is the same, which improves the uneven etching depth of the P-type channel that occurs when preparing different P-type channel gallium nitride devices, and improves the preparation yield.

[0082] In the description of the embodiments of the present application, it needs to be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0083] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0084] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0085] In the embodiments of the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0086] In the embodiments of the present application, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples without contradiction.

[0087] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for preparing a P-channel gallium nitride device, characterized in that: include: providing a substrate; Epitaxially growing a buffer layer, an N-type channel layer, a barrier layer, a main P-type channel layer, a first etching self-stop layer and a first P-type channel layer in sequence on the substrate; Based on a preset etching gas and using an inductively coupled plasma etching process, etching the gate groove from one side of the first P-type channel layer until the first etching self-stop layer is reached and the etching is stopped, wherein the etching is stopped when the etching stop condition is satisfied based on the plasma etching of the preset etching gas to the first etching self-stop layer; removing a corresponding portion of the first etching self-stop layer at the gate groove; A source and a drain are formed on a surface of the first P-type channel layer facing away from the substrate, and a gate structure is formed at the gate groove.

2. The method for preparing a P-channel gallium nitride device according to claim 1, characterized in that: After epitaxially growing the main P-type channel layer and before epitaxially growing the first etching self-stop layer, the method further includes: At least one pair of etching self-stop layers and P-type channel layers are alternately epitaxially grown on the main P-type channel layer, and are defined as the Nth etching self-stop layer to the second etching word stop layer and the NP-type channel layer to the second P-type channel layer in the order of epitaxial growth, where N is an integer not less than 2; Wherein, after removing the corresponding portion of the first etching self-stop layer at the gate groove and before forming the source, the drain and the gate structure, the method further includes: Based on a preset etching gas and using an inductively coupled plasma etching process, etching the second P-type channel layer at the gate groove until the etching reaches the second etching self-stop layer and the etching stops, wherein the etching stops when the etching stop condition is satisfied when the plasma etching based on the preset etching gas reaches the second etching self-stop layer; removing a corresponding portion of the second etch self-stop layer at the gate groove; The same method and steps as above are adopted until the corresponding portion of the i-th etching self-stop layer is removed at the gate groove, where i is an integer not greater than N and not less than 2.

3. The method for preparing a P-channel gallium nitride device according to claim 1, characterized in that: The preset etching gas is a F-based etching gas or an oxygen-containing etching gas, and the material of the corresponding etching self-stop layer is a GaN derivative containing an Al component.

4. The method for preparing a P-channel gallium nitride device according to claim 1, characterized in that: The forming of a gate structure at the gate groove comprises: A gate is formed at the gate groove to obtain a Schottky gate P-channel gallium nitride device.

5. The method for preparing a P-channel gallium nitride device according to claim 1, characterized in that: The forming of a gate structure at the gate groove comprises: Growing a gate dielectric layer covering at least the inner wall of the gate groove; A gate is formed on the gate dielectric layer to obtain a MIS gate P-channel gallium nitride device.

6. The method for preparing a P-channel gallium nitride device according to claim 1, characterized in that: After epitaxially growing the barrier layer and before epitaxially growing the main P-type channel layer, the method further includes: A hole supply layer and a barrier insertion layer are epitaxially grown in sequence on the barrier layer, and the hole supply layer, the barrier insertion layer and the main P-type channel layer form a heterojunction structure.

7. A P-channel gallium nitride device, characterized in that: include: substrate; A buffer layer, an N-type channel layer, a barrier layer, a main P-type channel layer, a first etch self-stop layer and a first P-type channel layer are located on the substrate and epitaxially grown in sequence, wherein a stack of the first etch self-stop layer and the first P-type channel layer forms a gate groove penetrating the stack; A source and a drain are located on a surface of the first P-type channel layer facing away from the substrate, and a gate structure is located at the gate groove.

8. The P-channel gallium nitride device according to claim 7, characterized in that: Also located between the main P-type channel layer and the first etching self-stop layer: At least one pair of etch self-stop layers and P-type channel layers alternately grown epitaxially on the P-type channel layer, and defined in sequence as the Nth etch self-stop layer to the second etch word stop layer and the NP-type channel layer to the second P-type channel layer in the order of epitaxial growth, where N is an integer not less than 2; The gate groove penetrates the stack from the i-th etching stop layer to the first P-type channel layer, and i is an integer not greater than N and not less than 2.

9. The P-channel gallium nitride device according to claim 7, characterized in that: Also included between the barrier layer and the main P-type channel layer: A hole supply layer and a barrier insertion layer are sequentially epitaxially grown on the barrier layer, and the hole supply layer, the barrier insertion layer and the main P-type channel layer form a heterojunction structure.

10. An electronic device, characterized in that: The electronic device comprises the P-channel gallium nitride device according to any one of claims 7 to 9.

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