Power device and manufacturing method thereof

Abstract

The invention discloses a power device and a manufacturing method thereof. The power device comprises a gallium oxide substrate; the N-type gallium oxide epitaxial layer is located on the first side surface of the gallium oxide substrate; the P-type gallium nitride layer is located on the surface of the gallium oxide epitaxial layer, grooves are formed in the P-type gallium nitride layer, the P-type gallium nitride layer comprises a first region and a second region, the first region is located between the adjacent grooves, and the second region is located at the bottoms of the grooves; the first N-type gallium nitride layer is positioned in the surface of the first region of the P-type gallium nitride layer; the second N-type gallium nitride layer is positioned in the surface of the second region of the P-type gallium nitride layer; the gate dielectric layer and the gate electrode layer at least cover partial regions of the second N-type gallium nitride layer and the first N-type gallium nitride layer; the source electrode layer is electrically connected with the first N-type gallium nitride layer; and the drain electrode layer is electrically connected with one side, far away from the gallium oxide epitaxial layer, of the gallium oxide substrate. The power device combines the advantages of GaN and Ga2O3 materials, and has better performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power device and a method for manufacturing the same. Background Art

[0002] In recent years, the application scope of power devices has become more and more extensive, from mobile phones and fast charging of new energy vehicles to photovoltaic power generation and high-voltage power grid transmission, gradually penetrating into all aspects of life, bringing great convenience to our daily life. Therefore, power devices will play an important role in the future to improve people's quality of life. However, the performance of existing power devices needs to be improved. Summary of the invention

[0003] In view of the above problems, the present application provides a power device and a method for manufacturing the same to achieve the purpose of improving performance. The specific solution is as follows:

[0004] A power device, comprising:

[0005] Gallium oxide substrate;

[0006] An N-type gallium oxide epitaxial layer located on a first side surface of the gallium oxide substrate;

[0007] A P-type gallium nitride layer located on a surface of the gallium oxide epitaxial layer away from the gallium oxide substrate, wherein the P-type gallium nitride layer has a groove, and the P-type gallium nitride layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, wherein the first region is located between adjacent grooves, and the second region is located at the bottom of the groove;

[0008] A first N-type gallium nitride layer located in the first region of the surface of the P-type gallium nitride layer and a second N-type gallium nitride layer located in the second region of the surface of the P-type gallium nitride layer, in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thicknesses of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer, and the second N-type gallium nitride layer is in contact with the gallium oxide epitaxial layer;

[0009] a gate dielectric layer and a gate electrode layer covering at least a portion of the second N-type gallium nitride layer and the first N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer;

[0010] A source electrode layer electrically connected to the first N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer;

[0011] A drain electrode layer is electrically connected to a side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

[0012] Optionally, the first N-type gallium nitride layer is not formed in a third region of the P-type gallium nitride layer on a side away from the gallium oxide epitaxial layer, and the P-type gallium nitride layer is also electrically connected to the source electrode layer.

[0013] Optionally, the first region includes a first sub-region and a second sub-region, and in a plane parallel to a plane where the P-type gallium nitride layer is located, the third region is located between the first sub-region and the second sub-region.

[0014] Optionally, the power device includes at least one column of trenches arranged along a first direction, one column of trenches includes at least one trench, and the first direction is parallel to a plane where the gallium oxide substrate is located.

[0015] Optionally, a column of grooves includes one groove, a projection of the groove on the gallium oxide substrate is in a rectangular shape, an extending direction of the groove is in a second direction, the second direction is parallel to a plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

[0016] Optionally, one second N-type gallium nitride layer is disposed in one of the grooves, an extension direction of the second N-type gallium nitride layer is the same as an extension direction of the groove, and a size of the second N-type gallium nitride layer along the extension direction is the same as a size of the groove along the extension direction;

[0017] Alternatively, a plurality of second N-type gallium nitride layers are disposed in a trench, an extension direction of the second N-type gallium nitride layer is the same as an extension direction of the trench, and a size of the second N-type gallium nitride layer along the extension direction is smaller than a size of the trench along the extension direction.

[0018] Optionally, when a plurality of second N-type gallium nitride layers are disposed in a trench, sizes of different second N-type gallium nitride layers along their extension directions are the same or different.

[0019] Optionally, a row of grooves includes a plurality of grooves arranged along a second direction, the second direction is parallel to a plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

[0020] Optionally, a projection shape of the groove on the gallium oxide substrate is a circle, a polygon or a rounded square.

[0021] A method for manufacturing a power device, comprising:

[0022] forming an N-type gallium oxide epitaxial layer on a gallium oxide substrate;

[0023] forming a P-type gallium nitride layer on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate;

[0024] A first N-type gallium nitride layer is formed in the surface of the first region of the P-type gallium nitride layer, and a second N-type gallium nitride layer is formed in the surface of the second region of the P-type gallium nitride layer, wherein the P-type gallium nitride layer has a groove, and the P-type gallium nitride layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region is located between adjacent grooves, and the second region is located at the bottom of the groove, in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thickness of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer, and the second N-type gallium nitride layer is in contact with the gallium oxide epitaxial layer;

[0025] forming a gate dielectric layer and a gate electrode layer covering at least the second N-type gallium nitride layer and a partial region of the first N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer;

[0026] forming a source electrode layer electrically connected to the first N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer;

[0027] A drain electrode layer is formed which is electrically connected to a side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

[0028] Optionally, a first N-type gallium nitride layer is formed on the surface of the first region of the P-type gallium nitride layer, and a second N-type gallium nitride layer is formed on the surface of the second region of the P-type gallium nitride layer, the P-type gallium nitride layer has a groove, the P-type gallium nitride layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region is located between adjacent grooves, and the second region is located at the bottom of the groove, and in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thickness of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer, including:

[0029] doping a fourth region of the P-type gallium nitride layer to form a first N-type gallium nitride layer in a fourth region on a surface of the P-type gallium nitride epitaxial layer away from the gallium oxide substrate, wherein the fourth region includes the first region;

[0030] Etching a fifth region of the P-type gallium nitride layer to form a groove in the P-type gallium nitride layer, wherein a depth of the groove is greater than a depth of the first N-type gallium nitride layer and less than a thickness of the P-type gallium nitride layer, and the fifth region is different from the first region;

[0031] The P-type gallium nitride layer exposed by the groove is doped to form a second N-type gallium nitride layer in the second region surface of the P-type gallium nitride layer, and in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thickness of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer.

[0032] Optionally, a fourth region of the P-type gallium nitride layer is doped to form a first N-type gallium nitride layer in a fourth region on a surface of the P-type gallium nitride epitaxial layer away from the gallium oxide substrate, wherein the fourth region includes the first region:

[0033] doping the first region of the P-type gallium nitride layer, retaining the third region of the P-type gallium nitride layer, and forming a first N-type gallium nitride layer in a first region of a surface of the P-type gallium nitride epitaxial layer away from the gallium oxide substrate;

[0034] The third region of the P-type gallium nitride layer is electrically connected to the source electrode layer.

[0035] By means of the above technical solution, the power device provided by the present application comprises an N-type gallium oxide epitaxial layer located on a gallium oxide substrate and a P-type gallium nitride layer located on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate, wherein the gallium oxide epitaxial layer and the P-type gallium nitride layer can form an epitaxial structure with a heterogeneous PN junction, thereby solving the device construction problem caused by the lack of P-type doping in the current gallium oxide material. Moreover, the power device provided by the embodiment of the present application integrates the GaN and Ga2O3 material systems, which can give play to the advantages of the high critical electric field and low substrate cost of Ga2O3, and also give play to the characteristics of GaN as a P-type material with high thermal conductivity.

[0036] In addition, in the power device provided in the embodiment of the present application, the power device forms an epitaxial structure with a heterogeneous PN junction through the gallium oxide epitaxial layer and the P-type gallium nitride layer. There are fewer electrons in the P-type gallium nitride layer. Therefore, when the voltage applied to the gate of the power device is 0V, there is no need to generate a depletion zone by depleting electrons, so that the requirement for the size between adjacent grooves is relatively low, so that the size between adjacent grooves can be achieved to about 1μm, which significantly reduces the process requirements of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0038] Figure 1 A schematic diagram of the structure of a current power device;

[0039] Figure 2 A schematic diagram of the structure of a power device provided in one embodiment of the present application;

[0040] Figure 3 A top view of a trench and a second N-type gallium nitride layer in a power device provided by an embodiment of the present application;

[0041] Figure 4 A top view of a trench and a second N-type gallium nitride layer in a power device provided by another embodiment of the present application;

[0042] Figure 5 A top view of a trench and a second N-type gallium nitride layer in a power device provided by yet another embodiment of the present application;

[0043] Figure 6 A top view of a trench and a second N-type gallium nitride layer in a power device provided by yet another embodiment of the present application;

[0044] Figure 7 A top view of a trench and a second N-type gallium nitride layer in a power device provided by yet another embodiment of the present application;

[0045] Figure 8 A top view of a trench and a second N-type gallium nitride layer in a power device provided by yet another embodiment of the present application;

[0046] Fig. 9 A schematic diagram of the structure of a power device provided in another embodiment of the present application;

[0047] Fig.10 A schematic diagram of the structure of a power device provided in yet another embodiment of the present application;

[0048] Fig.11 A schematic diagram of the structure of a power device provided in yet another embodiment of the present application;

[0049] Fig.12 A schematic diagram of energy bands of separated P-type GaN and N-type β-Ga2O3 in a power device provided in one embodiment of the present application;

[0050] Fig.13 In a power device provided in an embodiment of the present application, the energy band diagram of P-type GaN and N-type β-Ga2O3 in a thermal equilibrium state is shown in FIG.

[0051] Fig.14 A schematic diagram of the energy band contact between N-type GaN and N-type Ga2O3 in a power device provided in one embodiment of the present application;

[0052] Figure 15-Figure 29A schematic diagram of some structures involved in a method for manufacturing a power device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0054] It is obvious to those skilled in the art that various modifications and changes can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and changes of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0055] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0056] As described in the background technology section, the performance of existing power devices needs to be improved.

[0057] It should be noted that in the application of power devices, the Baliga's figure-of-merit (BFOM) is an indicator used to indicate the applicability of semiconductor materials in power electronics. It is expressed as: BFOM = εμE3, ε is the dielectric constant, μ is the mobility, E is the breakdown field strength of the semiconductor, and the BFOM value is roughly positively correlated with the sixth power of the bandgap width Eg. Therefore, a larger bandgap width means that wide-bandgap semiconductors have lower power loss and higher conversion efficiency in the application of power devices, thereby achieving more excellent and ideal power electronics applications.

[0058] Among wide bandgap semiconductor materials, Ga2O3 has a bandgap width of 4.8eV, an ideal breakdown electric field strength of 8MV / cm, and a BFOM value of up to 3400, which is about 4 times that of GaN and 10 times that of SiC. Therefore, in today's power electronics applications with higher power density and lower power consumption requirements, Ga2O3 materials have more significant research significance and broader market application prospects.

[0059] However, there is no report on the successful realization of p-type doping in Ga2O3, which limits the application of Ga2O3 devices compared with Si and SiC materials. As for the active area of ​​gallium oxide power devices, gallium oxide power devices can only be prepared by depleting the carriers in the conductive channel through a narrow FIN structure to achieve enhancement mode devices or high voltage devices.

[0060] In order to prepare an enhanced and high-voltage-resistant gallium oxide FET (Field Effect Transistor) device, a multi-fin structure can be used. This structure can make the movable carriers in the channel between the two fins of the gallium oxide FET device mutually deplete, thereby generating a high-resistance region. Then, when the voltage applied to the gate of the gallium oxide FET device is 0V, the gallium oxide FET device can be normally turned off; and the field plate structure formed by the multi-fin in the gallium oxide FET device can withstand the reverse electric field and reduce the surface leakage current, thereby forming an enhanced and high-voltage-resistant gallium oxide FET device.

[0061] However, the above solution has the following technical problems:

[0062] First, the spacing between two adjacent trenches needs to be about 0.35μm (that is, the width of the fin needs to be about 0.35μm). The reason is that there is a work function difference between the metal deposited on the sidewalls of the two trenches and the gallium oxide. When the voltage applied to the gate is 0V, the power function difference will deplete the conductive channel with a smaller spacing to produce a channel depletion region, thereby realizing the fabrication of an enhanced device. However, the fabrication of such a small conductive channel requires specific photoresists and photolithography machines, which increases the cost of the entire device and the difficulty of the process.

[0063] Second, under the reverse bias state, the electric field is mainly concentrated on the side walls and bottom corners of the gate dielectric, causing the gate dielectric deposited at the bottom of the trench to be subjected to a larger electric field. The gate dielectric is usually thinner, so a larger tunneling current may appear in the gate dielectric, increasing device leakage and affecting the long-term working stability of the device. In severe cases, the gate dielectric may be broken down and burned, resulting in a high device failure rate or even burning of the device.

[0064] In view of this, an embodiment of the present application provides a power device and a method for manufacturing the same, so as to reduce the process requirements of the power device and the failure rate during application and improve the performance. Optionally, the power device includes at least one field effect transistor.

[0065] like Figure 2 As shown, the power device provided in the embodiment of the present application includes:

[0066] Gallium oxide substrate 10;

[0067] An N-type doped gallium oxide epitaxial layer 20 located on a first side surface of the gallium oxide substrate 10;

[0068] A P-type gallium nitride layer 30 located on a surface of the gallium oxide epitaxial layer 20 away from the gallium oxide substrate 10, wherein the P-type gallium nitride layer 30 has a groove, and the P-type gallium nitride layer 30 includes a first region and a second region parallel to the plane where the gallium oxide substrate 10 is located, wherein the first region is located between adjacent grooves, and the second region is located at the bottom of the groove;

[0069] A first N-type gallium nitride layer 31 located in the first region of the surface of the P-type gallium nitride layer 30 and a second N-type gallium nitride layer 32 located in the second region of the surface of the P-type doped gallium nitride layer 30, in a direction perpendicular to the plane where the gallium oxide substrate 10 is located, the sum of the thickness of the first N-type gallium nitride layer 31 and the second N-type gallium nitride layer 32 is less than the thickness of the P-type gallium nitride layer;

[0070] A gate dielectric layer 40 and a gate electrode layer 50 covering at least a portion of the second N-type gallium nitride layer 32 and the first N-type gallium nitride layer 31 , wherein the gate dielectric layer 40 is located between the gate electrode layer 50 and the second N-type gallium nitride layer 32 ;

[0071] a source electrode layer 80 electrically connected to the first N-type gallium nitride layer 31 , wherein the source electrode layer 80 is electrically insulated from the gate electrode layer 50 ;

[0072] A drain electrode layer 90 is electrically connected to a side of the gallium oxide substrate 10 away from the gallium oxide epitaxial layer 20 .

[0073] It should be noted that, in one embodiment of the present application, the power device includes at least one repeating unit A, and one repeating unit may correspond to one field effect transistor. The present application does not limit this, and it depends on the specific circumstances.

[0074] Specifically, in one embodiment of the present application, the gate dielectric layer at least covers the bottom of the trench and the sidewalls of the trench. Optionally, the gate dielectric layer extends to cover a portion of the surface of the first N-type gallium nitride layer away from the gallium oxide substrate, but the present application does not limit this and it depends on the specific circumstances.

[0075] In the above embodiment, the gate electrode layer is located at the bottom of the trench and the sidewall of the trench. Specifically, in a direction perpendicular to the plane where the gallium oxide substrate is located, the gate electrode layer covers the second N-type gallium nitride layer, and in a direction parallel to the plane where the gallium oxide substrate is located, the gate electrode layer covers at least a partial area of ​​the first N-type gallium nitride layer.

[0076] The power device provided in the embodiment of the present application includes an N-type gallium oxide epitaxial layer located on a gallium oxide substrate and a P-type gallium nitride layer located on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium oxide epitaxial layer and the P-type gallium nitride layer can form an epitaxial structure with a heterogeneous PN junction, thereby solving the device construction problem caused by the lack of P-type doping in the current gallium oxide material. Moreover, the power device provided in the embodiment of the present application integrates the GaN and Ga2O3 material systems, which can give play to the advantages of the high critical electric field and low substrate cost of Ga2O3, and also give play to the characteristics of GaN as a P-type material with high thermal conductivity, and has high performance.

[0077] At the same time, compared with P-type materials such as NiO and Cu2O, gallium nitride (GaN) does not decompose in high-temperature environments and has higher heat dissipation capabilities. In addition, the lattice mismatch rate between GaN and Ga2O3 can be as low as 2.6%, so the N-type gallium oxide layer and the P-type gallium nitride layer form a better heterogeneous interface and have higher performance.

[0078] In addition, in the power device provided in the embodiment of the present application, the power device forms an epitaxial structure with a heterogeneous PN junction through the gallium oxide epitaxial layer and the P-type gallium nitride layer. There are fewer electrons in the P-type gallium nitride layer. Therefore, when the voltage applied to the gate of the power device is 0V, there is no need to generate a depletion zone by depleting electrons, so that the requirement for the size between adjacent grooves is relatively low, so that the size between adjacent grooves can be achieved to about 1μm, which significantly reduces the process requirements of the power device.

[0079] It should be noted that, in the present embodiment, the gallium oxide substrate is also N-type doped, but due to the growth process of the gallium oxide substrate, the doping concentration in the gallium oxide substrate is relatively high. If a subsequent P-type gallium nitride layer is directly formed on the gallium oxide substrate, the voltage resistance of the power device will be relatively poor. Therefore, in the power device provided in the embodiment of the present application, a low-concentration N-type doped gallium oxide layer is formed on the gallium oxide substrate, and the P-type gallium nitride layer is formed on the surface of the N-type gallium oxide layer to improve the voltage resistance performance of the power device.

[0080] Optionally, in one embodiment of the present application, the doping concentration of the N-type gallium oxide epitaxial layer is 2E16cm -3 The thickness of the N-type gallium oxide epitaxial layer is in the range of 5 μm to 10 μm; the thickness of the P-type gallium nitride layer is about 1 μm; the doping concentration of the P-type gallium nitride layer is in the range of 2e17 cm -3 ~1e18cm -3 ; This application does not limit this and it depends on the specific circumstances.

[0081] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 As shown, the first N-type gallium nitride layer 31 is not formed in the third region of the P-type gallium nitride layer 30 away from the gallium oxide epitaxial layer 20, and the P-type gallium nitride layer 30 is also electrically connected to the source electrode layer 80, so that when a reverse voltage is applied to the power device, the electric field is concentrated on the contact surface of the P-type gallium nitride layer 30 and the gallium oxide epitaxial layer 20, thereby reducing the electric field strength at the gate dielectric layer, reducing the risk of the gate dielectric layer being broken down or burned, thereby reducing the risk of failure of the power device and improving the stability of the power device.

[0082] Moreover, the P-type gallium nitride layer 30 is also electrically connected to the source electrode layer 80 , which can also improve the stability of the threshold voltage of the power device and improve the performance of the power device.

[0083] It should be noted that, in the above embodiment, the surface of the third region away from the gallium oxide substrate 10 may be flush with the surface of the first region away from the gallium oxide substrate 10 or may not be flush with the surface of the first region away from the gallium oxide substrate 10 . This is not limited in the present application and depends on the specific circumstances.

[0084] Optionally, in one embodiment of the present application, continue as Figure 2 As shown, the first region includes a first sub-region and a second sub-region, and in a plane parallel to the plane where the P-type gallium nitride layer is located, the third region is located between the first sub-region and the second sub-region. However, the present application does not limit this, and in other embodiments of the present application, the first region and the third region may also be arranged side by side, such as the third region is located on one side of the first region, depending on the specific situation.

[0085] Based on any of the above embodiments, in one embodiment of the present application, the power device includes at least one column of grooves arranged along a first direction, one column of grooves includes at least one groove, and the first direction is parallel to the plane where the gallium oxide substrate is located.

[0086] On the basis of the above embodiments, in one embodiment of the present application, a column of grooves includes a groove, the projection of the groove on the gallium oxide substrate is in a rectangular shape, and the extending direction is a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

[0087] Specifically, in one embodiment of the present application, Figure 3As shown, a second N-type gallium nitride layer 32 is disposed in a groove 33, and the extension direction of the second N-type gallium nitride layer 32 is the same as the extension direction of the groove 33, and the size of the second N-type gallium nitride layer 32 along its extension direction is the same as the size of the groove 33 along its extension direction, so as to increase the on-current of the power device, so that the power device has a smaller on-resistance.

[0088] In another embodiment of the present application, Figure 4 As shown, a plurality of second N-type gallium nitride layers 32 are arranged in a groove 33, and the extension direction of the second N-type gallium nitride layer 32 is the same as the extension direction of the groove 33, and the size of the second N-type gallium nitride layer 32 along the extension direction is smaller than the size of the groove 33 along the extension direction, so as to reduce the reverse leakage current of the power device, so that the power device has better regulation ability and better robustness when a short circuit occurs in the power device.

[0089] It should be noted that, in the above embodiment, Figure 4 As shown, when a plurality of second N-type gallium nitride layers are disposed in a trench, the sizes of different second N-type gallium nitride layers along their extension directions may be the same or different, depending on the specific circumstances.

[0090] It should also be noted that the larger the size of the second N-type gallium nitride layer along its extension direction, the smaller the on-resistance of the power device and the larger the on-current; the smaller the size of the second N-type gallium nitride layer along its extension direction, the smaller the reverse leakage current of the power device. The present application does not limit the size of the second N-type gallium nitride layer along its extension direction, which depends on the specific situation.

[0091] In other embodiments of the present application, Figure 5 As shown, one second N-type gallium nitride layer may be disposed in one of some of the grooves, and multiple second N-type gallium nitride layers may be disposed in one of some of the grooves. This application does not limit this, and it depends on the specific circumstances.

[0092] In another embodiment of the present application, a row of grooves includes a plurality of grooves arranged along a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different; in this embodiment, a second N-type gallium nitride layer is disposed in a groove.

[0093] Optionally, in one embodiment of the present application, the projection shape of the groove 33 on the gallium oxide substrate may be circular, such as Figure 6 As shown, it can also be a polygon, such as a hexagon, as Figure 7 As shown, it can also be a rounded square, such as Figure 8As shown, in other embodiments of the present application, the projection shape of the groove 33 on the gallium oxide substrate may also be other shapes, which is not limited in the present application and depends on specific circumstances.

[0094] Based on any of the above embodiments, in one embodiment of the present application, a second N-type gallium nitride layer may be disposed at the bottom of one of the trenches, and the second N-type gallium nitride layer may be located in the middle region of the bottom of the trench. Figure 2 As shown, it can also be located in the non-middle area at the bottom of the groove, such as Fig. 9 As shown; in another embodiment of the present application, at least two second N-type gallium nitride layers may be provided at the bottom of one of the trenches, such as Fig.10 As shown, optionally, the at least two second N-type gallium nitride layers are evenly distributed at the bottom of the trench, but the present application does not limit this and it depends on the specific circumstances.

[0095] Based on any of the above embodiments, in one embodiment of the present application, the power device further includes: a source ohmic contact layer 70 located between the source electrode layer 80 and the first N-type gallium nitride layer 31 , and a drain ohmic contact layer 91 located between the drain electrode layer 90 and the gallium oxide substrate 10 .

[0096] Based on any of the above embodiments, in one embodiment of the present application, the power device further includes a first insulating layer 60 located between the gate electrode layer 50 and the source electrode layer 80 to prevent the gate electrode layer 50 and the source electrode layer 80 from short-circuiting.

[0097] Based on any of the above embodiments, in one embodiment of the present application, Fig.11 As shown, the power device also includes: a second insulating layer 100 covering the source electrode layer 80 to serve as a protective layer for the source electrode layer 80; meanwhile, the second insulating layer 100 has an opening, and the opening of the second insulating layer 100 exposes a partial area of ​​the source electrode layer 80 to facilitate electrical connection of the source electrode layer 80 with the outside, such as being electrically connected to a test terminal as a test lead-out terminal.

[0098] like Fig.12 and Fig.13 As shown, Fig.12 The energy band diagram of separated P-type GaN and N-type β-Ga2O3 is shown. Fig.13The energy band diagram of P-type GaN and N-type β-Ga2O3 in thermal equilibrium is shown. The dotted line T represents the Fermi level, T1 is the Fermi level of P-type GaN, and T2 is the Fermi level of N-type β-Ga2O3; χ represents the electron affinity (the difference between the bottom of the conduction band and the vacuum energy level), such as the electron affinity (the difference between the bottom of the conduction band and the vacuum energy level) of P-type GaN = 4.1eV; E g Indicates the bandgap width, that is, the width between the bottom of the conduction band and the top of the valence band, such as the bandgap width E of P-type GaN g =3.4 eV; E F -E V It represents the difference between the Fermi level and the valence band top of P-type GaN. The smaller the difference, the greater the P-type doping concentration. For example, the difference between the Fermi level and the valence band top of P-type GaN is E F -E V =0.12eV; △E F It represents the difference in Fermi levels between two semiconductors (P-type GaN and N-type β-Ga2O3). The larger the difference, the more severe the bending of the conduction band and valence band and the wider the depletion layer when the two semiconductors are in contact. V Indicates the valence band difference between P-type GaN and N-type β-Ga2O3; E C -E F It represents the difference between the Fermi level and the bottom of the conduction band of N-type Ga2O3. The smaller the difference, the greater the N-type doping concentration. d is the depletion width, where the depletion width d of P-type GaN is GaN =1.34μm, the depletion width d of N-type β-Ga2O3 Ga2O3 =0.60μm.

[0099] from Fig.13 It can be seen from the figure that in the thermal equilibrium state, when the heterojunction is in the reverse bias state, the current of the heterojunction is generated by the conduction of minority carriers, so the leakage current is very small. , the reverse characteristic of the power device is good.

[0100] like Fig.14 As shown, Fig.14 Schematic diagram of the energy band contact between N-type GaN and N-type Ga2O3. Fig.14 It can be seen that the conduction band bottom △E of N-type GaN and N-type Ga2O3 C It is very close, with a barrier height of only 0.1eV. When forward biased, electrons can easily move from the N-type GaN side to the N-type Ga2O3 side, thereby achieving current conduction.

[0101] It can be seen that in the power device provided in the embodiment of the present application, the N-type GaN can provide an electron channel when the power device is forward biased, thereby achieving normal conduction of the device; at the same time, when reverse biased, the P-type GaN on both sides of the N-type GaN can play a role in shielding the electric field of the gate dielectric layer at the bottom of the trench, so that the power device can withstand a higher voltage.

[0102] In addition, the embodiment of the present application also provides a method for manufacturing the power device provided in any of the above embodiments. Specifically, the method for manufacturing the power device provided in the embodiment of the present application includes:

[0103] S1: Fig.15 As shown, an N-type gallium oxide epitaxial layer 20 is formed on a gallium oxide substrate 10 .

[0104] Optionally, in one embodiment of the present application, forming an N-type gallium oxide epitaxial layer on a gallium oxide substrate includes: epitaxially growing the N-type gallium oxide epitaxial layer on the gallium oxide substrate using a HVPE (Hydride Vapor Phase Epitaxy) method.

[0105] It should be noted that, in the present embodiment, the gallium oxide substrate is also N-type doped, but due to the growth process of the gallium oxide substrate, the doping concentration in the gallium oxide substrate is relatively high. If a subsequent P-type gallium nitride layer is directly formed on the gallium oxide substrate, the voltage resistance of the power device will be relatively poor. Therefore, the method for manufacturing a power device provided in the embodiment of the present application adopts an epitaxial process to epitaxially grow a low-concentration N-type doped gallium oxide layer on the gallium oxide substrate, and then performs subsequent process steps to improve the voltage resistance performance of the power device.

[0106] Specifically, in one embodiment of the present application, the doping concentration of the N-type gallium oxide epitaxial layer is 2E16cm -3 The thickness of the N-type gallium oxide epitaxial layer ranges from 5 μm to 10 μm, but this application does not limit this and it depends on the specific situation.

[0107] S2: Fig.16 As shown, a P-type gallium nitride layer 30 is formed on a side of the N-type gallium oxide epitaxial layer 20 away from the gallium oxide substrate 10 .

[0108] Optionally, in one embodiment of the present application, forming a P-type gallium nitride layer on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate includes: using HVPE (Hydride Vapor Phase Epitaxy) or MOCVD (Metal-organic Chemical Vapor Deposition) method to grow a P-type gallium nitride layer, i.e., P-type GaN, on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate.

[0109] Specifically, in one embodiment of the present application, the thickness of the P-type gallium nitride layer is about 1 μm; the doping concentration of the P-type gallium nitride layer is in the range of 2e17 cm -3 ~1e18cm -3 This application does not limit this and the specific circumstances will depend on the specific situation.

[0110] S3: forming a first N-type gallium nitride layer in the surface of the first region of the P-type gallium nitride layer, and forming a second N-type gallium nitride layer in the surface of the second region of the P-type gallium nitride layer, wherein the P-type gallium nitride layer has a groove, and the P-type gallium nitride layer comprises a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region is located between adjacent grooves, and the second region is located at the bottom of the groove, in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thickness of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer, and the second N-type gallium nitride layer is in contact with the gallium oxide epitaxial layer.

[0111] Optionally, in one embodiment of the present application, a first N-type gallium nitride layer is formed on the surface of the first region of the P-type gallium nitride layer, and a second N-type gallium nitride layer is formed on the surface of the second region of the P-type gallium nitride layer, the P-type gallium nitride layer has a groove, the P-type gallium nitride layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region is located between adjacent grooves, and the second region is located at the bottom of the groove, in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thickness of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer, and the second N-type gallium nitride layer is in contact with the gallium oxide epitaxial layer, including:

[0112] S31: Fig.17 As shown, the fourth region of the P-type gallium nitride layer 30 is doped to form a first N-type gallium nitride layer 31 in the surface of the fourth region of the P-type gallium nitride layer 30 away from the gallium oxide substrate 10, and the fourth region includes the first region.

[0113] Optionally, in one embodiment of the present application, doping the fourth region of the P-type gallium nitride layer to form a first N-type gallium nitride layer in a surface of the fourth region of the P-type gallium nitride layer on a side away from the gallium oxide substrate includes:

[0114] Silicon element is implanted into a fourth region of the P-type gallium nitride layer away from the gallium oxide substrate to form a first N-type gallium nitride layer in a surface of the fourth region of the P-type gallium nitride layer away from the gallium oxide substrate.

[0115] Specifically, in one embodiment of the present application, doping the fourth region of the P-type gallium nitride layer to form a first N-type gallium nitride layer in the surface of the fourth region on a side of the P-type gallium nitride layer away from the gallium oxide substrate includes:

[0116] forming a first dielectric layer on a surface of the P-type gallium nitride layer away from the gallium oxide substrate, and optionally, the first dielectric layer is a silicon oxide layer;

[0117] forming a first photoresist layer on a surface of the first dielectric layer away from the P-type gallium nitride layer;

[0118] exposing and developing the first photoresist layer to form a first opening in the first photoresist layer;

[0119] Using the first photoresist layer as a mask, etching the first dielectric layer to expose a fourth region of the P-type gallium nitride layer, wherein the fourth region includes the first region;

[0120] removing the first photoresist layer;

[0121] Using the first dielectric layer as a mask, implanting silicon into the fourth region of the P-type gallium nitride layer, thereby forming a first N-type gallium nitride layer in the surface of the fourth region of the P-type gallium nitride layer away from the gallium oxide substrate;

[0122] The first dielectric layer is removed.

[0123] It should be noted that, in this embodiment, in a direction perpendicular to the plane where the gallium oxide substrate is located, the depth of the first N-type gallium nitride layer is less than the depth of the P-type gallium nitride layer.

[0124] S32: Fig.18As shown, the fifth region of the P-type gallium nitride layer 30 is etched to form a groove 33 in the P-type gallium nitride layer 30. The depth of the groove 33 is greater than the depth of the first N-type gallium nitride layer 31 and less than the thickness of the P-type gallium nitride layer 30. The fifth region and the first region are different regions. The depth of the groove is the dimension of the groove in a direction perpendicular to the plane where the gallium oxide substrate is located; similarly, the depth of the first N-type gallium nitride layer is the dimension of the first N-type gallium nitride layer in a direction perpendicular to the plane where the gallium oxide substrate is located.

[0125] Optionally, in an embodiment of the present application, the fourth region includes the first region and the fifth region, and etching the fifth region of the P-type gallium nitride layer to form a trench in the P-type gallium nitride layer includes:

[0126] The fourth region of the P-type gallium nitride layer except the first region is etched to form a trench in the P-type gallium nitride layer, wherein the depth of the trench is greater than the depth of the first N-type gallium nitride layer.

[0127] S33: doping at least a portion of the P-type gallium nitride layer exposed at the bottom of the trench to form a second N-type gallium nitride layer in a second region of the surface of the P-type gallium nitride layer, wherein in a direction perpendicular to a plane where the gallium oxide substrate is located, a sum of thicknesses of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than a thickness of the P-type gallium nitride layer.

[0128] Optionally, in one embodiment of the present application, the fourth region of the P-type gallium nitride layer is doped, and a first N-type gallium nitride layer is formed in a fourth region on the surface of the P-type gallium nitride epitaxial layer away from the gallium oxide substrate, and the fourth region includes the first region, including: doping the first region of the P-type gallium nitride layer, retaining the third region of the P-type gallium nitride layer, and forming a first N-type gallium nitride layer in the first region on the surface of the P-type gallium nitride epitaxial layer away from the gallium oxide substrate, so that the third region of the P-type gallium nitride layer is subsequently electrically connected to the source electrode layer.

[0129] It should be noted that the third region of the P-type gallium nitride layer is subsequently electrically connected to the source electrode layer, so that when a reverse voltage is applied to the power device, the electric field is concentrated on the contact surface of the P-type gallium nitride layer 30 and the gallium oxide epitaxial layer 20, reducing the electric field strength at the gate dielectric layer, reducing the risk of the gate dielectric layer being broken down or burned, thereby reducing the risk of failure of the power device and improving the stability of the power device. Moreover, the P-type gallium nitride layer 30 is also electrically connected to the source electrode layer 80, which can also improve the stability of the threshold voltage of the power device and improve the performance of the power device.

[0130] Optionally, in one embodiment of the present application, doping at least a portion of the P-type gallium nitride layer exposed at the bottom of the trench to form a second N-type gallium nitride layer in the second region surface of the P-type gallium nitride layer includes:

[0131] like Fig.19 As shown, a second photoresist layer 34 is formed on the surface of the P-type gallium nitride layer 30 and the first N-type gallium nitride layer 31 away from the gallium oxide substrate 10 and the surface of the groove;

[0132] planarizing the second photoresist layer 34;

[0133] Performing photolithography on the second photoresist layer 34 to form a second opening, wherein the second opening exposes at least a portion of the bottom of the trench;

[0134] Using the second photoresist layer 34 as a mask, silicon is implanted into the P-type gallium nitride layer 30 to form a second N-type gallium nitride layer 32 in the second region of the P-type gallium nitride layer 30, and the second photoresist layer is removed. Fig. 20 As shown, the second N-type gallium nitride layer 32 is in contact with the gallium oxide epitaxial layer 10 .

[0135] Optionally, in an embodiment of the present application, the power device includes at least one column of grooves arranged along a first direction, one column of grooves includes at least one groove, and the first direction is parallel to the plane where the gallium oxide substrate is located.

[0136] On the basis of the above embodiments, in one embodiment of the present application, a column of grooves includes a groove, the projection of the groove on the gallium oxide substrate is in a rectangular shape, and the extending direction is a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

[0137] Specifically, in one embodiment of the present application, a second N-type gallium nitride layer is disposed in a groove, an extension direction of the second N-type gallium nitride layer is the same as an extension direction of the groove, and a size of the second N-type gallium nitride layer along its extension direction is the same as a size of the groove along its extension direction, so as to increase the on-current of the power device, so that the power device has a smaller on-resistance.

[0138] In another embodiment of the present application, a plurality of second N-type gallium nitride layers are arranged in a groove, and an extension direction of the second N-type gallium nitride layer is the same as an extension direction of the groove, and a size of the second N-type gallium nitride layer along its extension direction is smaller than a size of the groove along its extension direction, so as to reduce the reverse leakage current of the power device, so that when a short circuit occurs in the power device, the power device has better regulation capability and better robustness.

[0139] It should be noted that, in the above embodiment, when a plurality of second N-type gallium nitride layers are disposed in one trench, the sizes of different second N-type gallium nitride layers along their extension direction may be the same or different, depending on the specific situation.

[0140] It should also be noted that the larger the size of the second N-type gallium nitride layer along its extension direction, the smaller the on-resistance of the power device and the larger the on-current; the smaller the size of the second N-type gallium nitride layer along its extension direction, the smaller the reverse leakage current of the power device. The present application does not limit the size of the second N-type gallium nitride layer along its extension direction, which depends on the specific situation.

[0141] In other embodiments of the present application, one second N-type gallium nitride layer may be disposed in one of some of the grooves, and multiple second N-type gallium nitride layers may be disposed in one of some of the grooves. The present application does not limit this, and it depends on the specific circumstances.

[0142] In another embodiment of the present application, a row of grooves includes a plurality of grooves arranged along a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different; in this embodiment, a second N-type gallium nitride layer is disposed in a groove.

[0143] Optionally, in one embodiment of the present application, the projection shape of the groove on the gallium oxide substrate may be a circle, a polygon, such as a hexagon, or a rounded square. In other embodiments of the present application, the projection shape of the groove on the gallium oxide substrate may be other shapes, which is not limited in the present application and depends on the specific circumstances.

[0144] S4: forming a gate dielectric layer and a gate electrode layer that at least cover the second N-type gallium nitride layer and a partial region of the first N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer.

[0145] Optionally, in one embodiment of the present application, forming a gate dielectric layer and a gate electrode layer that at least covers a portion of the second N-type gallium nitride layer and the first N-type gallium nitride layer includes:

[0146] As shown in 21, a gate dielectric layer 40 is formed covering the second N-type gallium nitride layer 32, the first N-type gallium nitride layer 31 and the P-type gallium nitride layer 30. Optionally, the gate dielectric layer 40 is formed by an epitaxial process;

[0147] like Fig. 22As shown, a gate electrode layer 50 is formed on the surface of the gate dielectric layer 40 away from the second N-type gallium nitride layer 32, and in a direction perpendicular to the plane where the gallium oxide substrate 10 is located, the gate electrode layer 50 covers the second N-type gallium nitride layer 32, and in a direction parallel to the plane where the gallium oxide substrate 10 is located, the gate electrode layer 50 covers at least a portion of the first N-type gallium nitride layer 31;

[0148] like Fig.23 As shown, a first insulating layer 60 covering the gate dielectric layer and the gate electrode layer is formed. Optionally, the first insulating layer 60 is a silicon dioxide layer. Optionally, the first insulating layer is formed by a deposition process, and has a thickness of about 1 μm. This application does not limit this, and it depends on the specific situation.

[0149] like Fig.24 and Fig.25 As shown, the first insulating layer 60 and the gate dielectric layer 40 are etched to form an opening in the gate dielectric layer 40, and the opening in the gate dielectric layer 40 exposes at least a portion of the surface of the first N-type gallium nitride layer 31 away from the gallium oxide substrate 10, so as to facilitate the subsequent electrical connection of the first N-type gallium nitride layer 31 with the source electrode layer.

[0150] Specifically, in one embodiment of the present application, etching the first insulating layer 60 and the gate dielectric layer 40 to form an opening in the gate dielectric layer 40 includes:

[0151] like Fig.24 As shown, a fourth photoresist layer 61 is formed on the first insulating layer 60 away from the gate dielectric layer 40, and the fourth photoresist layer 61 has a fourth opening, and the fourth opening exposes a partial area of ​​the first insulating layer 60, and the area where the fourth opening is located corresponds to the area of ​​the first N-type gallium nitride layer 31 used for subsequent electrical contact with the source electrode layer;

[0152] like Fig.25 As shown, the fourth photoresist layer 61 is used as a mask to remove the first insulating layer 60 and the exposed area of ​​the gate dielectric layer 40, and an opening is formed in the gate dielectric layer 40;

[0153] like Fig.26 As shown, the fourth photoresist layer is removed.

[0154] Specifically, in one embodiment of the present application, forming a gate electrode layer on the surface of the gate dielectric layer away from the second N-type gallium nitride layer includes: forming a whole first electrode layer on the side of the gate dielectric layer away from the second N-type gallium nitride layer; forming a third photoresist layer on the surface of the first electrode layer away from the gate dielectric layer; planarizing the third photoresist layer; etching the third photoresist layer to form a third opening, wherein the third opening exposes a partial area of ​​the first electrode layer; dry etching the first electrode layer through the third opening, retaining a portion of the first electrode layer in the area where the gate electrode layer is to be formed, and removing other portions to form the gate electrode layer. Optionally, the gate electrode layer is located at the bottom of the trench and the sidewall of the trench, so that in a direction perpendicular to the plane where the gallium oxide substrate is located, the gate electrode layer covers the second N-type gallium nitride layer, and in a direction parallel to the plane where the gallium oxide substrate is located, the gate electrode layer covers at least a partial area of ​​the first N-type gallium nitride layer.

[0155] Optionally, in one embodiment of the present application, the gate dielectric layer is a silicon nitride layer, and the thickness of the gate dielectric layer ranges from 30nm to 100nm; the gate electrode layer is a Ni metal layer or a Pt metal layer, and the thickness of the gate electrode layer ranges from 100nm to 200nm; the present application does not impose any limitation on this, and it depends on the specific circumstances.

[0156] It should be noted that, when the power device is working, a source voltage is applied to the first N-type gallium nitride layer, and a gate voltage is applied to the gate electrode layer. Under the control of the source voltage and the gate voltage, the electrons in the first N-type gallium nitride layer sequentially enter the second N-type gallium nitride layer along the contact surface between the gate dielectric layer and the first N-type gallium nitride layer, the contact surface between the gate dielectric layer and the P-type gallium nitride layer, and the gate dielectric layer and the second N-type gallium nitride layer.

[0157] S5: forming a source electrode layer electrically connected to the first N-type gallium nitride layer and a drain electrode layer electrically connected to a side of the gallium oxide substrate away from the gallium oxide epitaxial layer, wherein the source electrode layer is electrically insulated from the gate electrode layer.

[0158] Optionally, in one embodiment of the present application, forming a source electrode layer electrically connected to the first N-type gallium nitride layer and a drain electrode layer electrically connected to a side of the gallium oxide substrate away from the gallium oxide epitaxial layer includes:

[0159] like Fig. 27 As shown, a source ohmic contact layer 70 is formed on an exposed portion of the first N-type gallium nitride layer 31 away from the gallium oxide layer substrate 10 , and a drain ohmic contact layer 91 is formed on a side of the gallium oxide substrate 10 away from the gallium oxide epitaxial layer 20 ;

[0160] like Fig.28 As shown, a source electrode layer 80 is formed on a side of the source ohmic contact layer 70 away from the first N-type gallium nitride layer 31 , and a drain electrode layer 90 is formed on a side of the drain ohmic contact layer 91 away from the gallium oxide substrate 10 .

[0161] Specifically, in one embodiment of the present application, the source ohmic contact layer includes a stacked Ti metal layer and an Au metal layer, the thickness of the Ti metal layer in the source ohmic contact layer is 20 nm, and the thickness of the Au metal layer is 20 nm; the drain ohmic contact layer includes a stacked Ti metal layer and an Au metal layer, the thickness of the Ti metal layer in the drain ohmic contact layer is 20 nm, and the thickness of the Au metal layer is 20 nm. The present application does not limit this and it depends on the specific circumstances.

[0162] Specifically, in one embodiment of the present application, forming a source ohmic contact layer on an exposed portion of the first N-type gallium nitride layer away from the gallium oxide layer substrate, and forming a drain ohmic contact layer on a side of the gallium oxide substrate away from the gallium oxide epitaxial layer includes:

[0163] forming a second electrode layer on an exposed portion of the first N-type gallium nitride layer away from the gallium oxide layer substrate, and optionally, the second electrode layer is formed by an evaporation process;

[0164] Using a lift-off process, remove the portion of the second electrode layer that is not located in the opening of the gate dielectric layer, and only retain the portion of the second electrode layer that is located in the opening of the gate dielectric layer;

[0165] forming a third electrode layer on a side of the gallium oxide substrate away from the gallium oxide epitaxial layer, and optionally, the third electrode layer is formed by an evaporation process;

[0166] The second electrode layer and the third electrode layer are annealed in a N2 atmosphere at a temperature range of 450° to 500° for 1 minute to form a source ohmic base layer and a drain ohmic contact layer.

[0167] On the basis of any of the above embodiments, in one embodiment of the present application, the manufacturing method further includes:

[0168] like Fig.29 As shown, a second insulating layer 100 is formed to cover the source electrode layer 80, and the second insulating layer 100 has an opening. The opening of the second insulating layer 100 exposes a partial area of ​​the source electrode layer 80 to facilitate electrical connection of the source electrode layer 80 with the outside world, such as being electrically connected to the test terminal as a test lead-out terminal.

[0169] In summary, the method for manufacturing a power device provided in the embodiment of the present application adopts the method of growing a P-type gallium nitride layer on a gallium oxide epitaxial layer, which can utilize the properties of GaN having P-type doping and high thermal conductivity, and can also utilize the advantages of gallium oxide substrate and low cost of epitaxy, thereby solving the problem of expensive GaN homogeneous substrate and device construction problems caused by the lack of P-type doping in the current gallium oxide material, and giving full play to the performance advantages of these two materials, with high performance.

[0170] Moreover, in the power device provided in the embodiment of the present application, the power device forms an epitaxial structure with a heterogeneous PN junction through the gallium oxide epitaxial layer and the P-type gallium nitride layer. There are fewer electrons in the P-type gallium nitride layer. Therefore, when the voltage applied to the gate of the power device is 0V, there is no need to generate a depletion zone by depleting electrons, so that the requirement for the size between adjacent grooves is relatively low, so that the size between adjacent grooves can be achieved to about 1μm, which significantly reduces the process requirements of the power device.

[0171] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0172] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure marks throughout the embodiments of the specification identify the same structure. It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such articles or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the article or equipment including the above elements.

[0173] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power device, characterized in that: include: Gallium oxide substrate; An N-type gallium oxide epitaxial layer located on a first side surface of the gallium oxide substrate; A P-type gallium nitride layer located on a surface of the gallium oxide epitaxial layer away from the gallium oxide substrate, wherein the P-type gallium nitride layer has a groove, and the P-type gallium nitride layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, wherein the first region is located between adjacent grooves, and the second region is located at the bottom of the groove; A first N-type gallium nitride layer located in the first region of the surface of the P-type gallium nitride layer and a second N-type gallium nitride layer located in the second region of the surface of the P-type gallium nitride layer, in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thicknesses of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer, and the second N-type gallium nitride layer is in contact with the gallium oxide epitaxial layer; a gate dielectric layer and a gate electrode layer covering at least a portion of the second N-type gallium nitride layer and the first N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer; A source electrode layer electrically connected to the first N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer; A drain electrode layer is electrically connected to a side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

2. The power device according to claim 1, characterized in that: The first N-type gallium nitride layer is not formed in a third region of the P-type gallium nitride layer on a side away from the gallium oxide epitaxial layer, and the P-type gallium nitride layer is also electrically connected to the source electrode layer.

3. The power device according to claim 2, characterized in that: The first region includes a first sub-region and a second sub-region. In a plane parallel to the plane where the P-type gallium nitride layer is located, the third region is located between the first sub-region and the second sub-region.

4. The power device according to claim 1, characterized in that: The power device includes at least one row of trenches arranged along a first direction, wherein one row of trenches includes at least one trench, and the first direction is parallel to a plane where the gallium oxide substrate is located.

5. The power device according to claim 4, characterized in that: A row of grooves includes a groove, the projection of the groove on the gallium oxide substrate is in a rectangular shape, and the extending direction is a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

6. The power device according to claim 5, characterized in that: A second N-type gallium nitride layer is disposed in one of the grooves, an extension direction of the second N-type gallium nitride layer is the same as an extension direction of the groove, and a size of the second N-type gallium nitride layer along the extension direction is the same as a size of the groove along the extension direction; Alternatively, a plurality of second N-type gallium nitride layers are disposed in a trench, an extension direction of the second N-type gallium nitride layer is the same as an extension direction of the trench, and a size of the second N-type gallium nitride layer along the extension direction is smaller than a size of the trench along the extension direction.

7. The power device according to claim 6, characterized in that: When a plurality of second N-type gallium nitride layers are disposed in one trench, sizes of different second N-type gallium nitride layers along their extension directions are the same or different.

8. The power device according to claim 4, characterized in that: A row of grooves includes a plurality of grooves arranged along a second direction, the second direction is parallel to a plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

9. The power device according to claim 8, characterized in that: The projection shape of the groove on the gallium oxide substrate is circular, polygonal or rounded square.

10. A method for manufacturing a power device, characterized in that: include: forming an N-type gallium oxide epitaxial layer on a gallium oxide substrate; forming a P-type gallium nitride layer on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate; A first N-type gallium nitride layer is formed in the surface of the first region of the P-type gallium nitride layer, and a second N-type gallium nitride layer is formed in the surface of the second region of the P-type gallium nitride layer, wherein the P-type gallium nitride layer has a groove, and the P-type gallium nitride layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region is located between adjacent grooves, and the second region is located at the bottom of the groove, in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thickness of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer, and the second N-type gallium nitride layer is in contact with the gallium oxide epitaxial layer; forming a gate dielectric layer and a gate electrode layer covering at least a portion of the second N-type gallium nitride layer and the first N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer; forming a source electrode layer electrically connected to the first N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer; A drain electrode layer is formed which is electrically connected to a side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

11. The manufacturing method according to claim 10, characterized in that: A first N-type gallium nitride layer is formed on the surface of the first region of the P-type gallium nitride layer, and a second N-type gallium nitride layer is formed on the surface of the second region of the P-type gallium nitride layer, wherein the P-type gallium nitride layer has a groove, and the P-type gallium nitride layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region is located between adjacent grooves, and the second region is located at the bottom of the groove, and in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thickness of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer, including: doping a fourth region of the P-type gallium nitride layer to form a first N-type gallium nitride layer in a fourth region on a surface of the P-type gallium nitride epitaxial layer away from the gallium oxide substrate, wherein the fourth region includes the first region; Etching a fifth region of the P-type gallium nitride layer to form a groove in the P-type gallium nitride layer, wherein a depth of the groove is greater than a depth of the first N-type gallium nitride layer and less than a thickness of the P-type gallium nitride layer, and the fifth region is different from the first region; The P-type gallium nitride layer exposed by the groove is doped to form a second N-type gallium nitride layer in the second region surface of the P-type gallium nitride layer, and in a direction perpendicular to the plane where the gallium oxide substrate is located, the sum of the thickness of the first N-type gallium nitride layer and the second N-type gallium nitride layer is less than the thickness of the P-type gallium nitride layer.

12. The manufacturing method according to claim 11, characterized in that: Doping a fourth region of the P-type gallium nitride layer to form a first N-type gallium nitride layer in a fourth region on a surface of the P-type gallium nitride epitaxial layer away from the gallium oxide substrate, wherein the fourth region includes the first region: doping the first region of the P-type gallium nitride layer, retaining the third region of the P-type gallium nitride layer, and forming a first N-type gallium nitride layer in a first region of a surface of the P-type gallium nitride epitaxial layer away from the gallium oxide substrate; The third region of the P-type gallium nitride layer is electrically connected to the source electrode layer.

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