Power device and manufacturing method thereof

Abstract

The invention discloses a power device. The power device comprises a gallium oxide substrate; the N-type gallium oxide epitaxial layer is located on the surface of the gallium oxide substrate; the gallium nitride epitaxial layer is located on the surface of the side, away from the gallium oxide substrate, of the gallium oxide epitaxial layer and comprises a first P-type gallium nitride layer, a first N-type gallium nitride layer and a second P-type gallium nitride layer which are stacked, and a groove is formed in the gallium nitride epitaxial layer and extends into the first N-type gallium nitride layer; the gallium nitride epitaxial layer comprises a first region and a second region which are parallel to the plane where the gallium oxide substrate is located, the first region is located between the adjacent grooves, and the second region is located at the bottoms of the grooves; the second N-type gallium nitride layer is located in the first region of the gallium nitride epitaxial layer and located in the surface of the second P-type gallium nitride layer; and the third N-type gallium nitride layer is located in the second region of the gallium nitride epitaxial layer and located in the surface of the first P-type gallium nitride layer. The power device combines the advantages of GaN and Ga2O3 materials, and has better performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power device and a method for manufacturing the same. Background Technology

[0002] In recent years, the application of power devices has become increasingly widespread, from mobile phones and fast charging of new energy vehicles to photovoltaic power generation and high-voltage power grid transmission, gradually permeating all aspects of life and bringing great convenience to our daily lives. Therefore, power devices will play an important role in the future to improve people's quality of life. However, the performance of existing power devices needs improvement. Summary of the Invention

[0003] In view of the above problems, this application provides a power device and its fabrication method to improve performance. The specific solution is as follows:

[0004] A power device, comprising:

[0005] Gallium oxide substrate;

[0006] An N-type gallium oxide epitaxial layer located on the first side surface of the gallium oxide substrate;

[0007] A gallium nitride epitaxial layer is located on the surface of the gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer includes a first p-type gallium nitride layer, a first n-type gallium nitride layer, and a second p-type gallium nitride layer stacked together. The gallium nitride epitaxial layer has trenches that penetrate the second p-type gallium nitride layer and extend into the first n-type gallium nitride layer. The gallium nitride epitaxial layer includes a first region and a second region parallel to the plane of the gallium oxide substrate. The first region is located between adjacent trenches, and the second region is located at the bottom of the trenches.

[0008] The second N-type gallium nitride layer, located in the first region of the gallium nitride epitaxial layer and within the surface of the second P-type gallium nitride layer, and the third N-type gallium nitride layer, located in the second region of the gallium nitride epitaxial layer and within the surface of the first P-type gallium nitride layer, have a thickness in the direction perpendicular to the plane of the gallium oxide substrate that is less than the thickness of the second P-type gallium nitride layer, and a thickness in the third N-type gallium nitride layer that is equal to the thickness of the first P-type gallium nitride layer.

[0009] A gate dielectric layer and a gate electrode layer located within the trench and covering at least a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer;

[0010] A source electrode layer electrically connected to the second N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer;

[0011] A drain electrode layer electrically connected to the side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

[0012] Optionally, the second N-type gallium nitride layer is not formed in the third region on the side of the second P-type gallium nitride layer away from the gallium oxide epitaxial layer, and the second P-type gallium nitride layer is also electrically connected to the source electrode layer.

[0013] Optionally, the first region includes a first sub-region and a second sub-region, and the third region is located between the first sub-region and the second sub-region in a plane parallel to the plane where the gallium nitride epitaxial layer is located.

[0014] Optionally, the power device includes at least one row of trenches arranged along a first direction, the row of trenches including at least one trench, the first direction being parallel to the plane of the gallium oxide substrate.

[0015] Optionally, a row of trenches includes a single trench whose projection on the gallium oxide substrate is rectangular, and whose extension direction is a second direction, which is parallel to the plane of the gallium oxide substrate, and the first direction and the second direction are different.

[0016] Optionally, a third N-type gallium nitride layer is disposed at the position of the first P-type gallium nitride layer corresponding to one of the trenches. The extension direction of the third N-type gallium nitride layer is the same as the extension direction of the trench, and the dimension of the third N-type gallium nitride layer along its extension direction is the same as the dimension of the trench along its extension direction.

[0017] Alternatively, a trench may have multiple third N-type gallium nitride layers disposed at the position of the first P-type gallium nitride layer, wherein the extension direction of the third N-type gallium nitride layers is the same as the extension direction of the trench, and the dimension of the third N-type gallium nitride layers along their extension direction is smaller than the dimension of the trench along its extension direction.

[0018] Optionally, when multiple third N-type gallium nitride layers are disposed at the position of the first P-type gallium nitride layer in a trench, the dimensions of the different third N-type gallium nitride layers along their extension direction may be the same or not completely the same.

[0019] Optionally, a row of trenches includes a plurality of trenches arranged along a second direction, which is parallel to the plane of the gallium oxide substrate, and the first direction and the second direction are different.

[0020] Optionally, the projection shape of the trench on the gallium oxide substrate is circular, polygonal, or rounded square.

[0021] A method for fabricating a power device, comprising:

[0022] An N-type gallium oxide epitaxial layer is formed on a gallium oxide substrate;

[0023] A gallium nitride epitaxial layer is formed on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer includes a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together.

[0024] In a first region of the gallium nitride epitaxial layer, a second N-type gallium nitride layer is formed within the surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer is formed within the surface of the first P-type gallium nitride layer. The gallium nitride epitaxial layer has trenches that penetrate the second P-type gallium nitride layer and extend into the first N-type gallium nitride layer. The gallium nitride epitaxial layer includes a first region and a second region parallel to the plane of the gallium oxide substrate. The first region is located between adjacent trenches, and the second region is located at the bottom of the trenches. In a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer.

[0025] A gate dielectric layer and a gate electrode layer are formed within the trench, and at least cover a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer;

[0026] A source electrode layer is formed that is electrically connected to the second N-type gallium nitride layer, and the source electrode layer is electrically insulated from the gate electrode layer;

[0027] A drain electrode layer is formed on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer, which is electrically connected.

[0028] Optionally, in the first region of the gallium nitride epitaxial layer, a second N-type gallium nitride layer is formed within the surface of the second P-type gallium nitride layer, and in the second region of the gallium nitride epitaxial layer, a third N-type gallium nitride layer is formed within the surface of the first P-type gallium nitride layer. The gallium nitride epitaxial layer has trenches that penetrate the second P-type gallium nitride layer and extend into the first N-type gallium nitride layer. The gallium nitride epitaxial layer includes a first region and a second region parallel to the plane of the gallium oxide substrate. The first region is located between adjacent trenches, and the second region is located at the bottom of the trenches.

[0029] The fourth region of the gallium nitride epitaxial layer is doped to form a second N-type gallium nitride layer on the fourth region of the surface of the second P-type gallium nitride epitaxial layer away from the gallium oxide substrate, and the fourth region includes the first region;

[0030] The fifth region of the gallium nitride epitaxial layer is etched to form a trench in the gallium nitride epitaxial layer. The trench penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer. The fifth region is a different region from the first region.

[0031] A portion of the first P-type gallium nitride layer corresponding to the trench is doped to form a third N-type gallium nitride layer within the surface of the second region of the first P-type gallium nitride layer. In a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer.

[0032] Optionally, the fourth region of the gallium nitride epitaxial layer is doped to form a second N-type gallium nitride layer on the fourth region of the surface of the second P-type gallium nitride layer away from the gallium oxide substrate. The fourth region includes the first region, comprising:

[0033] The fourth region of the first P-type gallium nitride layer in the gallium nitride epitaxial layer is doped, the third region of the first P-type gallium nitride layer in the gallium nitride epitaxial layer is retained, and a second N-type gallium nitride layer is formed in the first region on the surface of the first P-type gallium nitride layer away from the gallium oxide substrate.

[0034] The third region of the first P-type gallium nitride layer is electrically connected to the source electrode layer.

[0035] The power device provided in this application includes an N-type gallium oxide epitaxial layer on a gallium oxide substrate and a gallium nitride epitaxial layer on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer includes a stacked first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer, forming a PNP sandwich structure. This allows the gallium oxide epitaxial layer and the gallium nitride epitaxial layer to form an epitaxial structure with a heterojunction, solving the device construction problem caused by the lack of P-type doping in current gallium oxide materials. High-voltage devices can be fabricated using conventional processes. Furthermore, the power device provided in this application integrates GaN and Ga2O3 material systems, leveraging the advantages of Ga2O3's high critical electric field and low substrate cost, while also utilizing GaN's P-type material properties and high thermal conductivity, resulting in higher performance. Moreover, compared to P-type materials such as NiO and Cu2O, gallium nitride (GaN) does not decompose in high-temperature environments and has higher heat dissipation capabilities. In addition, the lattice mismatch rate between GaN and Ga2O3 can be as low as 2.6%, thus the N-type gallium oxide layer and the gallium nitride epitaxial layer form a better heterostructure interface with higher performance.

[0036] In addition, in the power device provided in this application embodiment, the power device forms an epitaxial structure with a heterojunction through the gallium oxide epitaxial layer and the gallium nitride epitaxial layer. Since there are fewer electrons in the gallium nitride epitaxial layer, when the voltage applied to the gate of the power device is 0V, it is not necessary to generate a depletion region by depleting electrons. This reduces the size requirements between adjacent trenches, allowing the size between adjacent trenches to be around 1μm, which significantly reduces the process requirements of the power device.

[0037] Furthermore, in the power device provided in this application embodiment, the second P-type gallium nitride layer is used to control the threshold voltage of the power device, and the first P-type gallium nitride layer is used to control the directional breakdown electric field of the power device. The first N-type gallium nitride layer is disposed between the first P-type gallium nitride layer and the second P-type gallium nitride layer, which can decouple the threshold voltage and reverse breakdown voltage of the power device, reduce the connection between the two, and make the design of the power device more flexible. Attached Figure Description

[0038] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0039] Figure 1 This is a schematic diagram of a current power device structure;

[0040] Figure 2 This is a schematic diagram of the structure of a power device provided in one embodiment of this application;

[0041] Figure 3 This is a top view of the trench and the third N-type gallium nitride layer in a power device provided in one embodiment of this application;

[0042] Figure 4 A top view of the trench and the third N-type gallium nitride layer in a power device provided in another embodiment of this application;

[0043] Figure 5 A top view of the trench and the third N-type gallium nitride layer in a power device provided in yet another embodiment of this application;

[0044] Figure 6 A top view of the trench and the third N-type gallium nitride layer in a power device provided in another embodiment of this application;

[0045] Figure 7 A top view of the trench and the third N-type gallium nitride layer in a power device provided in yet another embodiment of this application;

[0046] Figure 8 A top view of the trench and the third N-type gallium nitride layer in a power device provided in another embodiment of this application;

[0047] Figure 9 This is a schematic diagram of the structure of a power device provided in another embodiment of this application;

[0048] Figure 10 This is a schematic diagram of the structure of a power device provided in another embodiment of this application;

[0049] Figure 11 This is a schematic diagram of the structure of a power device provided in yet another embodiment of this application;

[0050] Figure 12 A schematic diagram of the energy bands of separated P-type GaN and N-type β-Ga2O3 in a power device provided in one embodiment of this application;

[0051] Figure 13 The energy band diagrams of P-type GaN and N-type β-Ga2O3 in a power device provided in one embodiment of this application, under thermal equilibrium conditions.

[0052] Figure 14 A schematic diagram of the band contact between N-type GaN and N-type Ga2O3 in a power device provided in one embodiment of this application;

[0053] Figures 15-31 This is a partial structural schematic diagram of a method for manufacturing a power device according to an embodiment of this application. Detailed Implementation

[0054] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0055] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0056] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] As described in the background section, the performance of existing power devices needs to be improved.

[0058] It should be noted that in power device applications, Baliga's figure-of-merit (BFOM) is an indicator used to represent the suitability of semiconductor materials for power electronics. It is expressed as: BFOM = εμE³, where ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. The BFOM value is approximately positively correlated with the sixth power of the bandgap Eg. Therefore, a larger bandgap means that wide-bandgap semiconductors have lower power losses and higher conversion efficiency in power device applications, thus enabling better and more ideal power electronic applications.

[0059] Among wide-bandgap semiconductor materials, Ga2O3 possesses a bandgap of 4.8 eV, an ideal breakdown electric field strength of 8 MV / cm, and a BFOM value as high as 30700, approximately four times that of GaN and ten times that of SiC. Therefore, in today's power electronics applications demanding higher power density and lower power consumption, Ga2O3 materials hold significant research importance and have broader market application prospects.

[0060] However, there are currently no reports of successful p-type doping in Ga2O3, which limits the types of devices that Ga2O3 devices can be used in compared to Si and SiC. Regarding the active region of gallium oxide power devices, enhancement-mode or high-voltage devices can only be fabricated by using narrow fin structures to deplete the charge carriers in the conductive channels.

[0061] To fabricate enhanced and high-voltage gallium oxide (GaO) FET (Field Effect Transistor) devices, a multi-fin structure can be employed. This structure allows the mobile carriers in the channel between the two fins of the GaO FET to deplete each other, thereby generating a high-resistivity region. Consequently, when a voltage of 0V is applied to the gate of the GaO FET, it can achieve normal turn-off. Furthermore, the field plate structure formed by the multi-fin in the GaO FET can withstand the reverse electric field, reducing surface leakage current, thus forming an enhanced and high-voltage-resistant GaO FET device.

[0062] However, the above solution has the following technical problems:

[0063] First, the spacing between two adjacent trenches needs to be about 0.35 μm (i.e., the width of the fin needs to be about 0.35 μm). The reason is that there is a work function difference between the metal deposited on the sidewalls of the two trenches and gallium oxide. When the voltage applied to the gate is 0V, this power function difference will deplete the conductive channel with a small spacing to generate the channel depletion region, thereby realizing the fabrication of enhancement-mode devices. However, the fabrication of such a small conductive channel requires specific photoresist and photolithography machine, which increases the overall device fabrication cost and process difficulty.

[0064] Second, under reverse bias, the electric field is mainly concentrated at the corners of the sidewalls and bottom of the gate dielectric, which causes the gate dielectric deposited at the bottom of the trench to be subjected to a large electric field. Since the gate dielectric is usually thin, a large tunneling current may occur in the gate dielectric, increasing the leakage current of the device and affecting the long-term working stability of the device. In severe cases, it may cause the gate dielectric to break down and burn out, resulting in a high failure rate of the device, or even burn out the device.

[0065] In view of this, embodiments of this application provide a power device and a method for manufacturing the same, to reduce the process requirements and failure rate of the power device during application, and to improve performance. Optionally, the power device includes at least one field-effect transistor.

[0066] like Figure 2 As shown, the power device provided in this application embodiment includes:

[0067] Gallium oxide substrate 10;

[0068] An N-type gallium oxide epitaxial layer 20 is located on the first side surface of the gallium oxide substrate 10;

[0069] A gallium nitride epitaxial layer 30 is located on the surface of the gallium oxide epitaxial layer 20 away from the gallium oxide substrate 10. The gallium nitride epitaxial layer 30 includes a first p-type gallium nitride layer 301, a first n-type gallium nitride layer 302, and a second p-type gallium nitride layer 303 stacked together. The gallium nitride epitaxial layer 30 has trenches that penetrate the second p-type gallium nitride layer 303 and extend into the first n-type gallium nitride layer 302. The gallium nitride epitaxial layer 30 includes a first region and a second region parallel to the plane of the gallium oxide substrate 10. The first region is located between adjacent trenches, and the second region is located at the bottom of the trenches.

[0070] The second N-type gallium nitride layer 304, located in the first region of the gallium nitride epitaxial layer 30 and within the surface of the second P-type gallium nitride layer 303, and the third N-type gallium nitride layer 305, located in the second region of the gallium nitride epitaxial layer 30 and within the surface of the first P-type gallium nitride layer 301, have a thickness in a direction perpendicular to the plane of the gallium oxide substrate 10. The thickness of the second N-type gallium nitride layer 304 is less than the thickness of the second P-type gallium nitride layer 303, and the thickness of the third N-type gallium nitride layer 305 is equal to the thickness of the first P-type gallium nitride layer 301.

[0071] A gate dielectric layer 40 and a gate electrode layer 50 are located within the trench and at least cover a portion of the second N-type gallium nitride layer 304, wherein the gate dielectric layer 40 is located between the gate electrode layer 50 and the second N-type gallium nitride layer 304;

[0072] A source electrode layer 80 electrically connected to the second N-type gallium nitride layer 304, wherein the source electrode layer 80 is electrically insulated from the gate electrode layer 50;

[0073] A drain electrode layer 90 electrically connected to the side of the gallium oxide substrate 10 away from the gallium oxide epitaxial layer 20.

[0074] It should be noted that, in one embodiment of this application, the power device includes at least one repeating unit A, and one repeating unit may correspond to one field-effect transistor. This application does not limit this, and it depends on the specific circumstances.

[0075] Specifically, in one embodiment of this application, the gate dielectric layer at least covers the bottom and sidewalls of the trench. Optionally, the gate dielectric layer extends to cover a portion of the surface of the second N-type gallium nitride layer away from the gallium oxide substrate. The gate electrode layer fills the trench. Optionally, the gate electrode layer also extends to cover a portion of the surface of the second N-type gallium nitride layer away from the gallium oxide substrate, but this application does not limit this and it depends on the specific circumstances.

[0076] The power device provided in this application includes an N-type gallium oxide epitaxial layer on a gallium oxide substrate and a gallium nitride epitaxial layer on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer includes a stacked first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer, forming a PNP sandwich structure. This allows the gallium oxide epitaxial layer and the gallium nitride epitaxial layer to form an epitaxial structure with a heterojunction, solving the device construction problem caused by the lack of P-type doping in current gallium oxide materials. High-voltage devices can be fabricated using conventional processes. Furthermore, the power device provided in this application integrates GaN and Ga2O3 material systems, leveraging the advantages of Ga2O3's high critical electric field and low substrate cost, while also utilizing GaN's P-type material properties and high thermal conductivity, resulting in higher performance. Moreover, compared to P-type materials such as NiO and Cu2O, gallium nitride (GaN) does not decompose in high-temperature environments and has higher heat dissipation capabilities. In addition, the lattice mismatch rate between GaN and Ga2O3 can be as low as 2.6%, thus the N-type gallium oxide layer and the gallium nitride epitaxial layer form a better heterostructure interface with higher performance.

[0077] In addition, in the power device provided in this application embodiment, the power device forms an epitaxial structure with a heterojunction through the gallium oxide epitaxial layer and the gallium nitride epitaxial layer. Since there are fewer electrons in the gallium nitride epitaxial layer, when the voltage applied to the gate of the power device is 0V, it is not necessary to generate a depletion region by depleting electrons. This reduces the size requirements between adjacent trenches, allowing the size between adjacent trenches to be around 1μm, which significantly reduces the process requirements of the power device.

[0078] Furthermore, in the power device provided in this application embodiment, the second P-type gallium nitride layer is used to control the threshold voltage of the power device, and the first P-type gallium nitride layer is used to control the directional breakdown electric field of the power device. The first N-type gallium nitride layer is disposed between the first and second P-type gallium nitride layers, which decouples the threshold voltage and reverse breakdown voltage of the power device, reducing the correlation between them and making the design of the power device more flexible. Additionally, the power device provided in this application embodiment can also achieve a deep masking effect by controlling the thickness of the first P-type gallium nitride layer, reducing leakage current and resulting in higher device reliability.

[0079] It should be noted that in this embodiment, the gallium oxide substrate is also N-type doped. However, due to the growth process of the gallium oxide substrate, the doping concentration in the gallium oxide substrate is relatively high. If the subsequent gallium nitride epitaxial layer is directly formed on the gallium oxide substrate, the breakdown voltage of the power device will be poor. Therefore, in the power device provided in this application embodiment, a low-concentration N-type doped gallium oxide layer is formed on the gallium oxide substrate, and the gallium nitride epitaxial layer is formed on the surface of the N-type gallium oxide layer to improve the breakdown voltage performance of the power device.

[0080] Optionally, in one embodiment of this application, the doping concentration of the N-type gallium oxide epitaxial layer is 2E16cm⁻¹. -3 The thickness of the N-type gallium oxide epitaxial layer ranges from 5 μm to 10 μm; the concentration of the first P-type gallium nitride layer ranges from 1E18 cm⁻¹. -3 ~2E19 cm -3 The thickness ranges from 0.3 μm to 1 μm; the concentration of the first N-type gallium nitride layer is 1E18 cm⁻¹. -3 ~2E19 cm -3 The thickness is 0.3 μm to 1 μm; the concentration of the second p-type gallium nitride layer ranges from 1E16 cm⁻¹. -3 ~2E17cm -3 The thickness ranges from 0.3 μm to 0.5 μm. However, this application does not impose any limitations on this, and the specific value depends on the circumstances.

[0081] Based on any of the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the second P-type gallium nitride layer 303 does not have a second N-type gallium nitride layer 304 formed in the third region on the side away from the gallium oxide epitaxial layer 20. The second P-type gallium nitride layer 303 is also electrically connected to the source electrode layer 80 so that when a reverse voltage is applied to the power device, its electric field is concentrated at the contact surface between the gallium nitride epitaxial layer 30 and the gallium oxide epitaxial layer 20, reducing the electric field strength at the gate dielectric layer, reducing the risk of the gate dielectric layer being broken down or burned, thereby reducing the risk of power device failure and improving the stability of the power device.

[0082] Furthermore, the second P-type gallium nitride layer 303 is also electrically connected to the source electrode layer 80, which can improve the stability of the threshold voltage of the power device and improve the performance of the power device.

[0083] It should be noted that, in the above embodiments, the surface of the third region away from the gallium oxide substrate 10 may or may not be flush with the surface of the first region away from the gallium oxide substrate 10. This application does not limit this, and it depends on the specific circumstances.

[0084] Optionally, in one embodiment of this application, the following continues... Figure 2 As shown, the first region includes a first sub-region and a second sub-region. Within a plane parallel to the plane containing the gallium nitride epitaxial layer, the third region is located between the first sub-region and the second sub-region. However, this application does not limit this arrangement. In other embodiments of this application, the first region and the third region may be arranged side-by-side, such as the third region being located to one side of the first region, depending on the specific circumstances.

[0085] Based on any of the above embodiments, in one embodiment of this application, the power device includes at least one row of trenches arranged along a first direction, the row of trenches including at least one of the trenches, the first direction being parallel to the plane where the gallium oxide substrate is located.

[0086] Based on the above embodiments, in one embodiment of this application, a row of trenches includes a trench, the shape of the projection of the trench on the gallium oxide substrate is rectangular, its extension direction is a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

[0087] Specifically, in one embodiment of this application, such as Figure 2 and Figure 3 As shown, a trench 306 is provided with a third N-type gallium nitride layer 305 at the position corresponding to the first P-type gallium nitride layer 301. The extension direction of the third N-type gallium nitride layer 305 is the same as the extension direction of the trench 306, and the dimension of the third N-type gallium nitride layer 305 along its extension direction is the same as the dimension of the trench 306 along its extension direction, so as to increase the conduction current of the power device and make the power device have a smaller on-resistance.

[0088] In another embodiment of this application, such as Figure 2 and Figure 4 As shown, a trench 306 has multiple third N-type gallium nitride layers 305 disposed at the position corresponding to the first P-type gallium nitride layer 301. The extension direction of the third N-type gallium nitride layer 305 is the same as the extension direction of the trench 306, and the dimension of the third N-type gallium nitride layer 305 along its extension direction is smaller than the dimension of the trench 306 along its extension direction, so as to reduce the reverse leakage current of the power device and enable the power device to have better regulation capability and better robustness when a short circuit occurs.

[0089] It should be noted that, in the above embodiments, the following continues... Figure 2 and Figure 4As shown, when a trench 306 is provided with multiple third N-type gallium nitride layers at the position corresponding to the first P-type gallium nitride layer 301, the dimensions of the different third N-type gallium nitride layers along their extension direction can be the same or different, depending on the specific situation.

[0090] It should also be noted that the larger the dimension of the third N-type gallium nitride layer along its extension direction, the smaller the on-resistance of the power device and the larger the on-current; the smaller the dimension of the third N-type gallium nitride layer along its extension direction, the smaller the reverse leakage current of the power device. This application does not limit the dimension of the third N-type gallium nitride layer along its extension direction, but it depends on the specific circumstances.

[0091] In other embodiments of this application, such as Figure 2 and Figure 5 As shown, a third N-type gallium nitride layer may be provided at the position of the first P-type gallium nitride layer in some trenches, and multiple third N-type gallium nitride layers may be provided at the position of the first P-type gallium nitride layer in some trenches. This application does not limit this, and it depends on the specific situation.

[0092] In another embodiment of this application, a trench includes a plurality of trenches arranged along a second direction, the second direction being parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction being different; in this embodiment, a third N-type gallium nitride layer is disposed in one trench.

[0093] Optionally, in one embodiment of this application, the projected shape of the trench 306 on the gallium oxide substrate can be circular, such as... Figure 6 As shown, it can also be a polygon, such as a hexagon, or... Figure 7 As shown, it can also be a rounded rectangle, such as... Figure 8 As shown, in other embodiments of this application, the projection shape of the trench 306 on the gallium oxide substrate can also be other shapes. This application does not limit this, and it depends on the specific circumstances.

[0094] Based on any of the above embodiments, in one embodiment of this application, a third N-type gallium nitride layer can be disposed at the position of the first P-type gallium nitride layer corresponding to one of the trenches, and, in a plane parallel to the gallium oxide substrate, the third N-type gallium nitride layer can be located in the middle region of the bottom of the trench, continuing as follows. Figure 2 As shown, it can also be located in the non-middle area at the bottom of the trench, such as Figure 9 As shown; in another embodiment of this application, at least two third N-type gallium nitride layers can be disposed at the position of the first P-type gallium nitride layer corresponding to one of the trenches, such as... Figure 10As shown, optionally, the at least two third N-type gallium nitride layers are uniformly distributed at the bottom of the trench in a plane parallel to the gallium oxide substrate, but this application does not limit this and it depends on the specific circumstances.

[0095] Based on any of the above embodiments, in one embodiment of this application, the power device further includes: a source ohmic contact layer 70 located between the source electrode layer 80 and the second N-type gallium nitride layer 304, and a drain ohmic contact layer 91 located between the drain electrode layer 90 and the gallium oxide substrate 10.

[0096] Based on any of the above embodiments, in one embodiment of this application, the power device further includes a first insulating layer 60 located between the gate electrode layer 50 and the source electrode layer 80 to prevent the gate electrode layer 50 and the source electrode layer 80 from short-circuiting.

[0097] Based on any of the above embodiments, in one embodiment of this application, the following continues... Figure 2 As shown, the power device further includes: a gate ohmic contact layer 110 electrically connected to the gate electrode layer 50 and a gate lead 120 electrically connected to the gate ohmic contact layer 110. Optionally, the source electrode layer 80 and the gate lead 120 are formed simultaneously; the source ohmic contact layer 70 and the gate ohmic contact layer 110 are formed simultaneously; however, this application does not limit this, and it depends on the specific circumstances.

[0098] Based on any of the above embodiments, in one embodiment of this application, such as Figure 11 As shown, the power device further includes a second insulating layer 100 covering the source electrode layer 80 as a protective layer for the source electrode layer 80. The second insulating layer 100 has an opening that exposes a portion of the source electrode layer 80 to facilitate electrical connection between the source electrode layer 80 and the outside world, such as electrical connection between the source electrode layer 80 and a test terminal as a test lead.

[0099] like Figure 12 and Figure 13 As shown, Figure 12 The diagram shows the energy band structure of separated GaN and N-type β-Ga2O3. Figure 13 The diagram shows the energy band structures of p-type GaN and n-type β-Ga₂O₃ under thermal equilibrium conditions. The dashed line T represents the Fermi level, with T₁ being the Fermi level of p-type GaN and T₂ the Fermi level of n-type β-Ga₂O₃; χ represents the electron affinity (the difference between the conduction band bottom and the vacuum level), such as χ = 4.1 eV for p-type GaN; E gThis refers to the bandgap width, which is the width between the bottom of the conduction band and the top of the valence band, such as the bandgap width E of P-type GaN. g =3.4 eV; E F -E V This represents the difference between the Fermi level and the valence band peak of p-type GaN. The smaller the difference, the higher the p-type doping concentration. For example, the difference between the Fermi level and the valence band peak of p-type GaN is E. F -E V =0.12eV; ΔE F This represents the Fermi level difference between two semiconductors (P-type GaN and N-type β-Ga2O3). The larger the difference, the more severe the bending of the conduction and valence bands and the wider the depletion layer when the two semiconductors are in contact. ΔE V E represents the valence band difference between p-type GaN and n-type β-Ga2O3; C -E F The value represents the difference between the Fermi level and the conduction band bottom of N-type Ga2O3. The smaller the difference, the higher the N-type doping concentration; d is the depletion width, where d is the depletion width of P-type GaN. GaN =1.34μm, depletion width d of N-type β-Ga2O3 Ga2O3 =0.60μm.

[0100] from Figure 13 As can be seen, under thermal equilibrium, when the heterojunction is in reverse bias, the current in the heterojunction is generated by minority carrier conduction, so the leakage current is very small, and the reverse characteristics of the power device are good.

[0101] like Figure 14 As shown, Figure 14 This is a schematic diagram of the band contact between N-type GaN and N-type Ga2O3. Figure 14 The conduction band bottom ΔE of N-type GaN and N-type Ga2O3 can be seen from the data. C With a barrier height of only 0.1 eV, electrons can easily move from the N-type GaN side to the N-type Ga2O3 side under forward bias, thus enabling current conduction.

[0102] Therefore, in the power device provided in this application embodiment, the N-type GaN can provide an electronic channel when the power device is forward biased, thereby enabling the device to conduct normally; at the same time, when reverse biased, the P-type GaN on both sides of the N-type GaN can shield the electric field of the gate dielectric layer at the bottom of the trench, so that the power device can withstand a higher voltage.

[0103] Furthermore, this application also provides a method for manufacturing the power device provided in any of the above embodiments. Specifically, the method for manufacturing the power device provided in this application includes:

[0104] S1: As Figure 15 As shown, an N-type gallium oxide epitaxial layer 20 is formed on a gallium oxide substrate 10.

[0105] Optionally, in one embodiment of this application, forming an N-type gallium oxide epitaxial layer on a gallium oxide substrate includes: epitaxially growing an N-type gallium oxide epitaxial layer on a gallium oxide substrate using the HVPE (hydride vapor phase epitaxy) method.

[0106] It should be noted that in this embodiment, the gallium oxide substrate is also N-type doped. However, due to the growth process of the gallium oxide substrate, the doping concentration in the gallium oxide substrate is relatively high. If the subsequent P-type gallium nitride layer is directly formed on the gallium oxide substrate, the breakdown voltage of the power device will be poor. Therefore, the power device fabrication method provided in this application embodiment uses an epitaxial process to epitaxially grow a low-concentration N-type doped gallium oxide layer on the gallium oxide substrate before performing subsequent process steps to improve the breakdown voltage performance of the power device.

[0107] Specifically, in one embodiment of this application, the doping concentration of the N-type gallium oxide epitaxial layer can range from 1E16cm. -3 ~9E16cm -3 Available in 2E16cm -3 The thickness of the N-type gallium oxide epitaxial layer ranges from 3 μm to 15 μm, and can be selected as 5 μm to 10 μm, but this application does not limit it and it depends on the specific situation.

[0108] S2: A gallium nitride epitaxial layer is formed on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer includes a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together.

[0109] Optionally, in one embodiment of this application, forming a gallium nitride epitaxial layer on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate includes:

[0110] like Figure 16As shown, a first P-type gallium nitride layer 301, a first N-type gallium nitride layer 302, and a second P-type gallium nitride layer 303 are sequentially formed on the side of the N-type gallium oxide epitaxial layer 20 away from the gallium oxide substrate 10 using either HVPE (Hydride Vapor Phase Epitaxy) or MOCVD (Metal-organic Chemical Vapor Deposition). It should be noted that in this embodiment, the second P-type gallium nitride layer is used to control the threshold voltage of the power device, and the first P-type gallium nitride layer is used to control the directional breakdown electric field of the power device. The placement of the first N-type gallium nitride layer between the first P-type gallium nitride layer and the second P-type gallium nitride layer decouples the threshold voltage and reverse breakdown voltage of the power device, reducing the correlation between them.

[0111] Specifically, in one embodiment of this application, the concentration range of the first P-type gallium nitride layer is 1E18cm⁻¹. -3 ~2E19 cm -3 The thickness ranges from 0.3 μm to 1 μm; the concentration of the first N-type gallium nitride layer is 1E18 cm⁻¹. -3 ~2E19 cm -3 The thickness is 0.3 μm to 1 μm; the concentration of the second p-type gallium nitride layer ranges from 1E16 cm⁻¹. -3 ~2E17cm -3 The thickness ranges from 0.3 μm to 0.5 μm to ensure the normal operation of the power device and decouple the threshold voltage and reverse breakdown voltage of the power device, reducing the correlation between them. However, this application does not impose any limitations on this, and the specific thickness depends on the circumstances.

[0112] S3: In the first region of the gallium nitride epitaxial layer, a second N-type gallium nitride layer is formed within the surface of the second P-type gallium nitride layer, and in the second region of the gallium nitride epitaxial layer, a third N-type gallium nitride layer is formed within the surface of the first P-type gallium nitride layer. The gallium nitride epitaxial layer has trenches that penetrate the second P-type gallium nitride layer and extend into the first N-type gallium nitride layer. The gallium nitride epitaxial layer includes a first region and a second region parallel to the plane of the gallium oxide substrate. The first region is located between adjacent trenches, and the second region is located at the bottom of the trenches. In the direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer.

[0113] Optionally, in one embodiment of this application, in the first region of the gallium nitride epitaxial layer, a second N-type gallium nitride layer is formed within the surface of the second P-type gallium nitride layer, and in the second region of the gallium nitride epitaxial layer, a third N-type gallium nitride layer is formed within the surface of the first P-type gallium nitride layer. The gallium nitride epitaxial layer has trenches that penetrate the second P-type gallium nitride layer and extend into the first N-type gallium nitride layer. The gallium nitride epitaxial layer includes a first region and a second region parallel to the plane of the gallium oxide substrate. The first region is located between adjacent trenches, and the second region is located at the bottom of the trenches. In a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer, including:

[0114] S31: As Figure 17 As shown, the fourth region of the gallium nitride epitaxial layer 30 is doped, and a second N-type gallium nitride layer 304 is formed in the surface of the fourth region on the side of the second P-type gallium nitride layer 303 away from the gallium oxide substrate 10 in the gallium nitride epitaxial layer 30. The fourth region includes the first region.

[0115] Optionally, in one embodiment of this application, doping the fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer on the surface of the fourth region of the second P-type gallium nitride layer away from the gallium oxide substrate includes:

[0116] Ion implantation is performed on a fourth region of the gallium nitride epitaxial layer on the side away from the gallium oxide substrate to form a second N-type gallium nitride layer on the surface of the fourth region of the second P-type gallium nitride layer on the side away from the gallium oxide substrate.

[0117] Specifically, in one embodiment of this application, when ion implantation is performed on the fourth region of the gallium nitride epitaxial layer on the side away from the gallium oxide substrate to form a second N-type gallium nitride layer, the implantation element used can be silicon, germanium, iron, carbon, or vanadium, etc. This application does not limit this, and it depends on the specific circumstances.

[0118] Optionally, in one embodiment of this application, doping the fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer on the surface of the fourth region of the second P-type gallium nitride layer away from the gallium oxide substrate includes:

[0119] A first dielectric layer is formed on the surface of the gallium nitride epitaxial layer away from the gallium oxide substrate. Optionally, the first dielectric layer is a silicon oxide layer.

[0120] A first photoresist layer is formed on the surface of the first dielectric layer away from the gallium nitride epitaxial layer;

[0121] The first photoresist layer is exposed and developed to form a first opening in the first photoresist layer;

[0122] Using the first photoresist layer as a mask, the first dielectric layer is etched to expose the fourth region of the gallium nitride epitaxial layer, the fourth region including the first region;

[0123] Remove the first photoresist layer;

[0124] Using the first dielectric layer as a mask, silicon elements are implanted into the fourth region of the gallium nitride epitaxial layer, thereby forming a second N-type gallium nitride layer on the surface of the fourth region of the second P-type gallium nitride layer away from the gallium oxide substrate;

[0125] Remove the first dielectric layer.

[0126] It should be noted that, in this embodiment, the depth of the second N-type gallium nitride layer is less than the depth of the second P-type gallium nitride layer in the direction perpendicular to the plane of the gallium oxide substrate. The depth of the second N-type gallium nitride layer is its thickness in the direction perpendicular to the surface of the gallium oxide substrate; similarly, the depth of the second P-type gallium nitride layer is its thickness in the direction perpendicular to the surface of the gallium oxide substrate.

[0127] Optionally, in one embodiment of this application, the fourth region of the gallium nitride epitaxial layer is doped, and a second N-type gallium nitride layer is formed in the fourth region on the surface of the second P-type gallium nitride layer away from the gallium oxide substrate. The fourth region includes the first region and includes: doping the first region of the second P-type gallium nitride layer, retaining the third region of the second P-type gallium nitride layer, and forming the second N-type gallium nitride layer in the first region on the surface of the second P-type gallium nitride layer away from the gallium oxide substrate, so that the third region of the second P-type gallium nitride layer can be subsequently electrically connected to the source electrode layer.

[0128] It should be noted that the third region of the second P-type gallium nitride layer is subsequently electrically connected to the source electrode layer. When a reverse voltage is applied to the power device, the electric field is concentrated at the contact surface between the gallium nitride epitaxial layer 30 and the gallium oxide epitaxial layer 20, reducing the electric field strength at the gate dielectric layer. This lowers the risk of the gate dielectric layer being broken down or burned, thereby reducing the risk of power device failure and improving the stability of the power device. Furthermore, the electrical connection between the second P-type gallium nitride layer and the subsequently formed source electrode layer can also improve the stability of the threshold voltage of the power device, thus enhancing its performance.

[0129] S32: As Figure 18 As shown, the fifth region of the gallium nitride epitaxial layer 30 is etched to form a trench 306 in the gallium nitride epitaxial layer 30. The trench 306 penetrates the second p-type gallium nitride layer 303 and extends into the first n-type gallium nitride layer 302. The fifth region is different from the first region. It should be noted that the trench does not penetrate the first n-type gallium nitride layer. That is, in the direction perpendicular to the plane where the gallium oxide substrate is located, the depth of the trench is greater than the depth of the second p-type gallium nitride layer, but less than the sum of the depths of the second p-type gallium nitride layer and the first n-type gallium nitride layer.

[0130] Optionally, in one embodiment of this application, the fourth region includes the first region and the fifth region, and etching the fifth region of the gallium nitride epitaxial layer to form a trench in the gallium nitride epitaxial layer includes:

[0131] The region in the fourth region of the gallium nitride epitaxial layer excluding the first region is etched to form a trench in the gallium nitride epitaxial layer.

[0132] S33: A portion of the first P-type gallium nitride layer corresponding to the trench is doped to form a third N-type gallium nitride layer in the second region of the first P-type gallium nitride layer. In a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer.

[0133] Optionally, in one embodiment of this application, doping a portion of the first P-type gallium nitride layer corresponding to the trench to form a third N-type gallium nitride layer within the surface of the second region of the first P-type gallium nitride layer includes:

[0134] like Figure 19 As shown, a second photoresist layer 307 is formed on the surface of the second P-type gallium nitride layer 303 and the second N-type gallium nitride layer 304 away from the gallium oxide substrate 10 and on the surface of the trench.

[0135] The second photoresist layer 307 is etched to form a second opening, which exposes the bottom of the trench.

[0136] like Figure 20As shown, using the second photoresist layer 307 as a mask, ion implantation is performed on the first P-type gallium nitride layer 301 to form a third N-type gallium nitride layer 305 in the second region of the first P-type gallium nitride layer 301. It should be noted that in this embodiment, the ion implantation depth should penetrate the first P-type gallium nitride layer so that the thickness of the third N-type gallium nitride layer 305 is the same as the thickness of the first P-type gallium nitride layer 301, that is, the third N-type gallium nitride layer 305 is in contact with the gallium oxide epitaxial layer 10.

[0137] like Figure 21 As shown, a protective layer 308 is formed covering the second photoresist layer 307 and the surface of the trench. Optionally, the protective layer 308 is a silicon nitride (Si3N4) layer, and the thickness of the protective layer is about 300nm. This application does not limit this, and it depends on the specific situation.

[0138] The third N-type gallium nitride layer 305 is annealed to activate the doped ions in the third N-type gallium nitride layer 305. Optionally, the third N-type gallium nitride layer 305 is annealed in an annealing furnace at an annealing temperature of 1200°C for 5 minutes to activate the doped ions in the third N-type gallium nitride layer 305.

[0139] like Figure 22 As shown, the protective layer and the second photoresist layer are removed. Optionally, the protective layer can be removed using a hot phosphoric acid solution and the second photoresist layer can be removed using a BOE solution, but this application does not limit this and it depends on the specific circumstances.

[0140] It should be noted that atoms migrate or detach from the crystal at high temperatures, leaving an uneven surface. In this embodiment, the purpose of forming a protective layer before annealing the third N-type gallium nitride layer is to prevent atoms from detaching from the surface of the first N-type gallium nitride layer during the high-temperature activation process of the third N-type gallium nitride layer, thereby roughening the surface of the first N-type gallium nitride layer.

[0141] Optionally, in one embodiment of this application, the second photoresist layer is a film layer that is easy to remove and not easily decomposed at high temperatures, such as a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, or a carbon film layer; the thickness of the second photoresist layer ranges from 1 μm to 5 μm, but this application does not limit it and it depends on the specific circumstances.

[0142] Optionally, in one embodiment of this application, the power device includes at least one row of trenches arranged along a first direction, the row of trenches including at least one trench, the first direction being parallel to the plane where the gallium oxide substrate is located.

[0143] Based on the above embodiments, in one embodiment of this application, a row of trenches includes a trench, the shape of the projection of the trench on the gallium oxide substrate is rectangular, its extension direction is a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

[0144] Specifically, in one embodiment of this application, a third N-type gallium nitride layer is disposed at the position of the first P-type gallium nitride layer in a trench. The extension direction of the third N-type gallium nitride layer is the same as the extension direction of the trench, and the dimension of the third N-type gallium nitride layer along its extension direction is the same as the dimension of the trench along its extension direction, so as to increase the conduction current of the power device and make the power device have a smaller on-resistance.

[0145] In another embodiment of this application, a trench is provided with a plurality of third N-type gallium nitride layers at the position corresponding to the first P-type gallium nitride layer. The extension direction of the third N-type gallium nitride layers is the same as the extension direction of the trench, and the dimension of the third N-type gallium nitride layers along their extension direction is smaller than the dimension of the trench along their extension direction, so as to reduce the reverse leakage current of the power device and enable the power device to have better regulation capability and better robustness when a short circuit occurs.

[0146] It should be noted that in the above embodiments, when multiple third N-type gallium nitride layers are provided at the position of the first P-type gallium nitride layer in a trench, the dimensions of the different third N-type gallium nitride layers along their extension direction can be the same or different, depending on the specific situation.

[0147] It should also be noted that the larger the dimension of the third N-type gallium nitride layer along its extension direction, the smaller the on-resistance of the power device and the larger the on-current; the smaller the dimension of the third N-type gallium nitride layer along its extension direction, the smaller the reverse leakage current of the power device. This application does not limit the dimension of the third N-type gallium nitride layer along its extension direction, but it depends on the specific circumstances.

[0148] In other embodiments of this application, a third N-type gallium nitride layer may be provided at the position of the first P-type gallium nitride layer in some trenches, and multiple third N-type gallium nitride layers may be provided at the position of the first P-type gallium nitride layer in some trenches. This application does not limit this, and it depends on the specific situation.

[0149] In another embodiment of this application, a trench includes a plurality of trenches arranged along a second direction, the second direction being parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction being different; in this embodiment, a third N-type gallium nitride layer is disposed at the position of the first P-type gallium nitride layer corresponding to a trench.

[0150] Optionally, in one embodiment of this application, the projection shape of the trench on the gallium oxide substrate can be circular, polygonal, such as hexagonal, or rounded square. In other embodiments of this application, the projection shape of the trench on the gallium oxide substrate can also be other shapes. This application does not limit this and it depends on the specific circumstances.

[0151] S4: Form a gate dielectric layer and a gate electrode layer located within the trench, and at least covering a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer.

[0152] Optionally, in one embodiment of this application, forming a gate dielectric layer and a gate electrode layer located within the trench and at least covering a portion of the second N-type gallium nitride layer includes:

[0153] As shown in 23, a gate dielectric layer 40 is formed covering the second P-type gallium nitride layer 303, the second N-type gallium nitride layer 304 and the trench surface. Optionally, the gate dielectric layer 40 is formed by an epitaxial process.

[0154] like Figure 24 As shown, a gate electrode layer 50 is formed on the surface of the gate dielectric layer 40 away from the third N-type gallium nitride layer 305, and a self-aligned etching process is used to etch the gate electrode layer 50, retaining the portion of the gate electrode layer 50 located within the trench 306. Optionally, the gate electrode layer 50 further extends to cover a portion of the second N-type gallium nitride layer 304 away from the gallium oxide substrate 10. In the direction perpendicular to the plane of the gallium oxide substrate 10, the thickness of the gate electrode layer 50 is much greater than the thickness of the gate dielectric layer 40, and it completely fills the trench 306.

[0155] like Figure 25 As shown, a first insulating layer 60 is formed covering the gate dielectric layer 40 and the gate electrode layer 50. Optionally, the first insulating layer 60 is a silicon dioxide layer. Optionally, the formation process of the first insulating layer is a deposition process, and the thickness is about 1 μm. This application does not limit this, and it depends on the specific situation.

[0156] like Figure 26 As shown, the first insulating layer 60 and the gate dielectric layer 40 are etched to form an opening in the gate dielectric layer 40. The opening in the gate dielectric layer 40 exposes at least a portion of the surface of the second N-type gallium nitride layer 304 away from the gallium oxide substrate 10, so as to facilitate the electrical connection between the second N-type gallium nitride layer 304 and the subsequently formed source electrode layer.

[0157] Optionally, in one embodiment of this application, the gate dielectric layer is a silicon nitride layer, and the thickness of the gate dielectric layer ranges from 30nm to 100nm, optionally 50nm; the gate electrode layer is a polysilicon layer, and the thickness of the gate electrode layer ranges from 200nm to 1500nm; this application does not limit this, and it depends on the specific circumstances.

[0158] It should be noted that when the power device is working, a source voltage is applied to the second N-type gallium nitride layer and a gate voltage is applied to the gate electrode layer. Under the control of the source voltage and the gate voltage, electrons in the second N-type gallium nitride layer sequentially enter the first N-type gallium nitride layer along the contact surface between the gate dielectric layer and the second N-type gallium nitride layer, and the contact surface between the gate dielectric layer and the second P-type gallium nitride layer, and then enter the third N-type gallium nitride layer through the first N-type gallium nitride layer.

[0159] S5: Form a source electrode layer electrically connected to the second N-type gallium nitride layer, the source electrode layer being electrically insulated from the gate electrode layer, and form a drain electrode layer electrically connected to the side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

[0160] Optionally, in one embodiment of this application, forming a source electrode layer electrically connected to the second N-type gallium nitride layer and a drain electrode layer electrically connected to the side of the gallium oxide substrate away from the gallium oxide epitaxial layer includes:

[0161] like Figure 27 As shown, a source ohmic contact layer 70 is formed on the exposed portion of the second N-type gallium nitride layer 304 away from the gallium oxide substrate 10, and a gate ohmic contact layer 110 is formed on the exposed portion of the gate electrode layer 50 away from the gallium oxide substrate 10. Optionally, the source ohmic contact layer 70 and the gate ohmic contact layer 110 are formed simultaneously.

[0162] like Figure 28 As shown, a drain ohmic contact layer 91 is formed on the side of the gallium oxide substrate 10 away from the gallium oxide epitaxial layer 20;

[0163] like Figure 29 As shown, a source electrode layer 80 is formed on the side of the source ohmic contact layer 70 away from the second N-type gallium nitride layer 304, and a gate lead 120 is formed on the side of the gate ohmic contact layer 110 away from the gate electrode layer 50. Optionally, the source electrode layer 80 and the gate lead 120 are formed simultaneously.

[0164] like Figure 30 As shown, a drain electrode layer 90 is formed on the side of the drain ohmic contact layer 91 away from the gallium oxide substrate 10.

[0165] Specifically, in one embodiment of this application, the source ohmic contact layer includes a stacked Ti metal layer and an Au metal layer, wherein the thickness of the Ti metal layer in the source ohmic contact layer is 20 nm and the thickness of the Au metal layer is 20 nm; the drain ohmic contact layer includes a stacked Ti metal layer and an Au metal layer, wherein the thickness of the Ti metal layer in the drain ohmic contact layer is 20 nm and the thickness of the Au metal layer is 20 nm. This application does not limit the specific details, and the details depend on the specific circumstances.

[0166] It should be noted that the source ohmic contact layer, the gate ohmic contact layer, and the drain ohmic contact layer need to be annealed after formation to form ohmic contacts. In the embodiments of this application, the power device can be fabricated by annealing once after the source ohmic contact layer and the gate ohmic contact layer are formed, and then annealing once after the drain ohmic contact layer is formed. Alternatively, the source ohmic contact layer, the gate ohmic contact layer, and the drain ohmic contact layer can be annealed once. This application does not limit this method and it depends on the specific circumstances.

[0167] Specifically, in one embodiment of this application, forming a source ohmic contact layer on the exposed portion of the second N-type gallium nitride layer away from the gallium oxide substrate, forming a gate ohmic contact layer on the exposed portion of the gate electrode layer away from the gallium oxide substrate, and forming a drain ohmic contact layer on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer includes:

[0168] A first electrode layer is formed on the exposed portion of the second N-type gallium nitride layer away from the gallium oxide substrate and on the exposed portion of the gate electrode layer away from the gallium oxide substrate. Optionally, the first electrode layer is formed by vapor deposition.

[0169] A stripping process is used to remove the exposed portions of the first electrode layer that are not located on the side of the second N-type gallium nitride layer away from the gallium oxide substrate, as well as the exposed portions of the gate electrode layer that are away from the gallium oxide substrate.

[0170] A second electrode layer is formed on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer. Optionally, the second electrode layer is formed by vapor deposition.

[0171] The first electrode layer and the second electrode layer are tempered in an N2 atmosphere at a temperature range of 450° to 500° for 1 minute to form a source ohmic base layer, a gate ohmic contact layer and a drain ohmic contact layer.

[0172] Based on any of the above embodiments, in one embodiment of this application, the manufacturing method further includes:

[0173] like Figure 31As shown, a second insulating layer 100 is formed covering the source electrode layer 80. The second insulating layer 100 has an opening that exposes a portion of the source electrode layer 80 so that the source electrode layer 80 can be electrically connected to the outside world, such as being electrically connected to a test lead as a test lead.

[0174] The power device fabrication method provided in this application includes an N-type gallium oxide epitaxial layer on a gallium oxide substrate and a gallium nitride epitaxial layer on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer includes a stacked first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer, forming a PNP sandwich structure. This allows the gallium oxide epitaxial layer and the gallium nitride epitaxial layer to form an epitaxial structure with a heterojunction, solving the device construction problem caused by the lack of P-type doping in gallium oxide materials. High-voltage devices can be fabricated using conventional processes. Moreover, the power device provided in this application integrates the GaN and Ga2O3 material system, leveraging the advantages of Ga2O3's high critical electric field and low substrate cost, while also utilizing GaN's P-type material properties and high thermal conductivity, resulting in higher performance. Furthermore, compared to P-type materials such as NiO and Cu2O, gallium nitride (GaN) does not decompose in high-temperature environments and has higher heat dissipation capabilities. In addition, the lattice mismatch rate between GaN and Ga2O3 can be as low as 2.6%, thus the N-type gallium oxide layer and the gallium nitride epitaxial layer form a better heterostructure interface with higher performance.

[0175] Furthermore, in the method for fabricating the power device provided in this application embodiment, the power device forms an epitaxial structure with a heterojunction through the gallium oxide epitaxial layer and the gallium nitride epitaxial layer. Since there are fewer electrons in the gallium nitride epitaxial layer, when the voltage applied to the gate of the power device is 0V, it is not necessary to generate a depletion region by depleting electrons. This reduces the size requirements between adjacent trenches, allowing the size between adjacent trenches to be around 1μm, which significantly reduces the process requirements of the power device.

[0176] Furthermore, in the method for fabricating a power device provided in this application embodiment, the second P-type gallium nitride layer is used to control the threshold voltage of the power device, the first P-type gallium nitride layer is used to control the directional breakdown electric field of the power device, and the first N-type gallium nitride layer is disposed between the first P-type gallium nitride layer and the second P-type gallium nitride layer, which can decouple the threshold voltage and reverse breakdown voltage of the power device, reduce the connection between the two, and make the design of the power device more flexible.

[0177] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0178] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in an article or device comprising the aforementioned element.

[0179] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power device, characterized in that: include: Gallium oxide substrate; An N-type gallium oxide epitaxial layer located on a first side surface of the gallium oxide substrate; a gallium nitride epitaxial layer located on a surface of the gallium oxide epitaxial layer away from the gallium oxide substrate, the gallium nitride epitaxial layer comprising a stacked first P-type gallium nitride layer, a first N-type gallium nitride layer and a second P-type gallium nitride layer, the gallium nitride epitaxial layer comprising a groove, the groove penetrating the second P-type gallium nitride layer and extending into the first N-type gallium nitride layer, the gallium nitride epitaxial layer comprising a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region being located between adjacent grooves, and the second region being located at the bottom of the groove; a second N-type gallium nitride layer located in the first region of the gallium nitride epitaxial layer and located on the surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer located in the second region of the gallium nitride epitaxial layer and located on the surface of the first P-type gallium nitride layer, wherein in a direction perpendicular to the plane where the gallium oxide substrate is located, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer; a gate dielectric layer and a gate electrode layer located in the trench and covering at least a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer; a source electrode layer electrically connected to the second N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer; A drain electrode layer is electrically connected to a side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

2. The power device according to claim 1, characterized in that: The second N-type gallium nitride layer is not formed in a third region of the second P-type gallium nitride layer on a side away from the gallium oxide epitaxial layer, and the second P-type gallium nitride layer is also electrically connected to the source electrode layer.

3. The power device according to claim 2, characterized in that: The first region includes a first sub-region and a second sub-region. In a plane parallel to the plane where the gallium nitride epitaxial layer is located, the third region is located between the first sub-region and the second sub-region.

4. The power device according to claim 1, characterized in that: The power device includes at least one row of trenches arranged along a first direction, wherein one row of trenches includes at least one trench, and the first direction is parallel to a plane where the gallium oxide substrate is located.

5. The power device according to claim 4, characterized in that: A row of grooves includes a groove, the projection of the groove on the gallium oxide substrate is in a rectangular shape, and the extending direction is a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

6. The power device according to claim 5, characterized in that: A third N-type gallium nitride layer is disposed at a position of the groove corresponding to the first P-type gallium nitride layer, an extension direction of the third N-type gallium nitride layer is the same as an extension direction of the groove, and a size of the third N-type gallium nitride layer along the extension direction is the same as a size of the groove along the extension direction; Alternatively, a plurality of third N-type gallium nitride layers are disposed at positions of a trench corresponding to the first P-type gallium nitride layer, an extension direction of the third N-type gallium nitride layer is the same as an extension direction of the trench, and a size of the third N-type gallium nitride layer along the extension direction is smaller than a size of the trench along the extension direction.

7. The power device according to claim 6, characterized in that: When a plurality of third N-type gallium nitride layers are disposed at a position of a trench corresponding to the first P-type gallium nitride layer, sizes of different third N-type gallium nitride layers along their extension directions are the same or different.

8. The power device according to claim 4, characterized in that: A row of grooves includes a plurality of grooves arranged along a second direction, the second direction is parallel to a plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

9. The power device according to claim 8, characterized in that: The projection shape of the groove on the gallium oxide substrate is circular, polygonal or rounded square.

10. A method for manufacturing a power device, characterized in that: include: forming an N-type gallium oxide epitaxial layer on a gallium oxide substrate; Forming a gallium nitride epitaxial layer on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate, wherein the gallium nitride epitaxial layer includes a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked; A second N-type gallium nitride layer is formed in the first region of the gallium nitride epitaxial layer on the surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer is formed in the second region of the gallium nitride epitaxial layer on the surface of the first P-type gallium nitride layer, the gallium nitride epitaxial layer has a groove, the groove penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer, the gallium nitride epitaxial layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region is located between adjacent grooves, and the second region is located at the bottom of the groove, in a direction perpendicular to the plane where the gallium oxide substrate is located, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer; forming a gate dielectric layer and a gate electrode layer located in the trench and covering at least a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer; forming a source electrode layer electrically connected to the second N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer; A drain electrode layer is formed which is electrically connected to a side of the gallium oxide substrate away from the gallium oxide epitaxial layer.

11. The manufacturing method according to claim 10, characterized in that: A second N-type gallium nitride layer is formed in the first region of the gallium nitride epitaxial layer and on the surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer is formed in the second region of the gallium nitride epitaxial layer and on the surface of the first P-type gallium nitride layer, wherein the gallium nitride epitaxial layer has a groove, the groove penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer, the gallium nitride epitaxial layer includes a first region and a second region parallel to the plane where the gallium oxide substrate is located, the first region is located between adjacent grooves, and the second region is located at the bottom of the groove and includes: doping a fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer in a fourth region of the second P-type gallium nitride epitaxial layer on a side away from the gallium oxide substrate, wherein the fourth region includes the first region; Etching the fifth region of the gallium nitride epitaxial layer to form a trench in the gallium nitride epitaxial layer, wherein the trench penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer, and the fifth region is different from the first region; Doping a portion of the first P-type gallium nitride layer corresponding to the groove to form a third N-type gallium nitride layer in the second region surface of the first P-type gallium nitride layer, wherein in a direction perpendicular to a plane where the gallium oxide substrate is located, a thickness of the third N-type gallium nitride layer is equal to a thickness of the first P-type gallium nitride layer.

12. The manufacturing method according to claim 11, characterized in that: Doping a fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer in a fourth region on a surface of the second P-type gallium nitride layer away from the gallium oxide substrate, wherein the fourth region includes the first region: doping the fourth region of the first P-type gallium nitride layer in the gallium nitride epitaxial layer, retaining the third region of the first P-type gallium nitride layer in the gallium nitride epitaxial layer, and forming a second N-type gallium nitride layer in a first region in a surface of the first P-type gallium nitride layer away from the gallium oxide substrate; The third region of the first P-type gallium nitride layer is electrically connected to the source electrode layer.

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