Instruction processing method and device in ATE, Pattern program processing method and device and test system

Abstract

The invention relates to an instruction processing method and device in ATE, a Pattern program processing method and device and a test system. Comprising the following steps: in an ith period, performing address fetching processing on a next period prediction instruction determined in an (i-1) th period to obtain an address fetched instruction; according to the instruction jump prediction table, determining a next period prediction instruction and a next period prediction instruction corresponding to the current instruction; wherein the current instruction is a target instruction determined in the (i-1) th period; decoding the addressed instruction of the (i-1) th period to obtain a decoded instruction of the ith period; performing execution processing on one of the decoded instructions in the (i-1) th period according to the target instruction determined in the (i-1) th period; and determining a target instruction of the (i + 1) th period. By adopting the method, the Pattern instruction is processed through a multi-stage assembly line operation mode, the generation of a'cutoff 'period can be avoided, and the automatic test efficiency of the chip is improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip automated testing equipment, and in particular to an instruction processing method, a pattern program processing method, a device and a testing system in ATE. Background Art

[0002] At present, one of the core components of chip automated test equipment (ATE) is ALPG (Algorithmic pattern generator), which is a DSP (Digital Signal Processing) component that generates signals to communicate with the IC (Integrated Circuit) chip under test (for example, DDR memory chip). ALPG can run pattern programs containing instructions similar to CPU sequence, loop, jump, etc., so as to realize the output of various complex signal flows based on the short pattern programs written by the test personnel.

[0003] In order to adapt to the ever-increasing specifications of IC chips, the test equipment (ie, ATE) also needs to gradually increase the basic frequency of ALPG (for example, 300MHz), and then apply technologies such as multi-path interleaving to generate a signal flow that matches the high-frequency operation of the IC.

[0004] At present, the operating frequency of ALPG is generally increased by applying a multi-stage pipeline. Traditional multi-stage pipelines will produce instruction interruptions, commonly known as "bubbles" or "interruptions" in program execution. Traditional CPUs (Central Processing Units) use branch prediction and other methods to reduce "interruptions" to improve CPU operating efficiency, but they cannot completely eliminate "interruptions", and the field of traditional CPUs also allows fewer "interruptions" to occur. In the test machine, the "interruption" cycle means outputting unexpected signals, which will disrupt the normal signal flow of the DSP output. Therefore, the "interruption" cycle needs to be eliminated on the test machine. Summary of the invention

[0005] Based on this, it is necessary to provide an instruction processing method, Pattern program processing method, device and test system in ATE to address the above technical problems, which can process Pattern instructions through a multi-stage pipeline operation mode to avoid the generation of "broken flow" cycles.

[0006] In a first aspect, the present application provides an instruction processing method in ATE, comprising:

[0007] In the i-th cycle, the next cycle prediction instruction determined in the i-1th cycle is addressed to obtain the addressed instruction of the i-th cycle; and according to the instruction jump prediction table, the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction are determined; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each pattern instruction in the pattern program;

[0008] Decode the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle;

[0009] According to the target instruction determined in the i-1th cycle, one of the decoded instructions in the i-1th cycle is executed to form a current execution instruction; and after the current instruction is executed, the target instruction of the i+1th cycle is determined.

[0010] In one embodiment, the method further comprises:

[0011] Obtain the compiled Pattern program; the compiled Pattern program includes a register initialization list, a Pattern instruction, and an instruction jump prediction table;

[0012] Initialize the register space according to the register initialization list, load the Pattern instruction into the instruction storage space, and load the instruction jump prediction table into the table space.

[0013] In one embodiment, addressing the next cycle prediction instruction determined in the (i-1)th cycle is performed, including:

[0014] Obtaining an instruction count value from an addressing instruction set; the addressing instruction set stores the instruction count value of the next cycle prediction instruction determined in the i-1th cycle;

[0015] According to the instruction count value, address processing is performed on the next cycle prediction instruction determined in the i-1th cycle;

[0016] After determining the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table, the method further includes:

[0017] The instruction count value of the next cycle prediction instruction of the current instruction is stored in the next jump instruction set, and the instruction count value of the next cycle prediction instruction of the current instruction is stored in the next jump instruction set;

[0018] After determining the target instruction of the (i+1)th cycle, the method further includes:

[0019] After the i-th cycle, the data of the next-hop instruction set is transferred to the address instruction set, the data of the next-down-jump instruction set is transferred to the next-hop instruction set, and the next-down-jump instruction set is cleared.

[0020] In one embodiment, the method further comprises:

[0021] In the first cycle, the starting instruction of the Pattern program is used as the current address instruction for addressing processing to obtain the addressed instruction of the first cycle; according to the instruction jump prediction table, the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current address instruction are determined; and the next cycle prediction instruction corresponding to the current address instruction is used as the target instruction of the next cycle.

[0022] In a second aspect, the present application also provides a Pattern program processing method, including:

[0023] Get the original Pattern program; the original Pattern program includes multiple Pattern instructions;

[0024] Predict the next cycle instruction of each Pattern instruction, and determine the next cycle predicted instruction corresponding to each Pattern instruction;

[0025] Predict the next cycle instruction of each Pattern instruction, and determine the next cycle prediction instruction corresponding to each Pattern instruction;

[0026] Generate an instruction jump prediction table according to the next cycle prediction instructions and the next cycle prediction instructions corresponding to the multiple pattern instructions;

[0027] Generate a compiled Pattern program according to the original Pattern program and the instruction jump prediction table; transmit the compiled Pattern program to the chip automatic test equipment, wherein the chip automatic test equipment performs the following steps according to the compiled Pattern program: in the i-th cycle, address the next cycle prediction instruction determined in the i-1th cycle to obtain the addressed instruction of the i-th cycle; and determine the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; decode the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle; according to the target instruction determined in the i-1th cycle, execute one of the decoded instructions of the i-1th cycle to form the current execution instruction; and determine the target instruction of the i+1th cycle after the current instruction is executed.

[0028] In one embodiment, predicting the next cycle instruction of each Pattern instruction and determining the next cycle predicted instruction corresponding to each Pattern instruction includes:

[0029] For each Pattern instruction, if the current Pattern instruction is a sequential instruction, the instruction count value of the current Pattern instruction is incremented by one to obtain a first target count value; the Pattern instruction corresponding to the first target count value is determined as the next cycle prediction instruction corresponding to the current Pattern instruction;

[0030] If the current Pattern instruction is a jump loop instruction, the Pattern instruction corresponding to the first target count value and the jump target Pattern instruction of the jump loop instruction are determined as the next cycle prediction instruction corresponding to the current Pattern instruction.

[0031] In one embodiment, predicting the next cycle instruction of each Pattern instruction and determining the next cycle predicted instruction corresponding to each Pattern instruction includes:

[0032] Get the next cycle prediction instruction corresponding to each Pattern instruction;

[0033] For each Pattern instruction, if the next cycle predicted instruction of the current Pattern instruction is a sequential instruction, the instruction count value of the next cycle predicted instruction of the current Pattern instruction is increased by one to obtain a second target count value; the Pattern instruction corresponding to the second target count value is determined as the next cycle predicted instruction corresponding to the current Pattern instruction;

[0034] If the next cycle predicted instruction of the current Pattern instruction is a jump loop instruction, the Pattern instruction corresponding to the second target count value and the jump target Pattern instruction of the jump loop instruction are determined as the next cycle predicted instruction corresponding to the current Pattern instruction.

[0035] In a third aspect, the present application further provides an instruction processing device in ATE, comprising:

[0036] An instruction fetching module is used to fetch the next cycle predicted instruction determined in the i-1th cycle in the i-th cycle, and obtain the fetched instruction of the i-th cycle;

[0037] An instruction prefetch module is used to determine the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each pattern instruction in the pattern program;

[0038] An instruction decoding module is used to decode the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle;

[0039] The instruction execution module is used to execute one of the decoded instructions of the i-1th cycle according to the target instruction determined in the i-1th cycle to form a current execution instruction; and determine the target instruction of the i+1th cycle after the current instruction is executed.

[0040] In a fourth aspect, the present application further provides a test system, which includes a chip automation test device, and the chip automation test device includes an ALPG unit; the ALPG unit is used to execute the steps of the instruction processing method in the ATE described in the first aspect above.

[0041] In one embodiment, the test system further includes a computer device, which is connected to the chip automated test device, and is used to execute the steps of the Pattern program processing method described in the second aspect above.

[0042] The instruction processing method, pattern program processing method, device and test system in the above-mentioned ATE, in the i-th cycle, address the next cycle prediction instruction determined in the i-1th cycle to obtain the addressed instruction of the i-th cycle; and determine the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each pattern instruction in the pattern program; decode the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle; according to the target instruction determined in the i-1th cycle, execute one of the decoded instructions of the i-1th cycle to form the current execution instruction; and determine the target instruction of the i+1th cycle after the current instruction is executed. In the above manner, addressing, decoding and execution are performed in parallel in the same cycle, addressing the instruction predicted in the previous cycle, decoding the instruction already addressed in the previous cycle, and executing the instruction already decoded in the previous cycle, so as to realize the processing of Pattern instructions through the operation mode of multi-stage pipeline, improve the efficiency of generating test signals in ATE, and thus improve the efficiency of chip automatic testing. Based on the instruction jump prediction table, the addressing and decoding of the predicted instruction are completed in advance. On the one hand, the target instruction currently being processed has been decoded in the previous cycle. On the other hand, due to the advance derivation and prediction, the target instruction of the next cycle is determined to be one of the decoded instructions in the current cycle, which can avoid the generation of "broken flow" cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A schematic diagram of the basic principle of IC testing in one embodiment;

[0045] Figure 2 A schematic diagram of a pipeline including a "flow cut-off" cycle in one embodiment;

[0046] Figure 3 A flowchart of an instruction processing method in ATE in one embodiment;

[0047] Figure 4 A schematic diagram of components involved in an instruction processing method in ATE in one embodiment;

[0048] Figure 5 A schematic diagram of the composition of ALPG in one embodiment;

[0049] Figure 6 Schematic diagram of a process flow of a Pattern program processing method in one embodiment;

[0050] Figure 7 is a structural block diagram of an instruction processing device in ATE in one embodiment;

[0051] Figure 8 FIG. 1 is a schematic diagram of the structure of a test system in an embodiment. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0053] It is understandable that chip automated test equipment (ATE) is a device that performs quality inspection on the IC (Integrated Circuit) chips produced during the chip production process. Its main purpose is to distinguish qualified chips from unqualified chips to ensure product quality and reliability. With the rapid development of integrated circuits, their scale is getting larger and larger, and the requirements for circuit quality and reliability are further improved. The testing methods of integrated circuits are becoming more and more difficult. Therefore, it is of great significance to study and develop IC testing. As an important part of IC testing, it is increasingly important to study the generation method of test vectors.

[0054] Reference Figure 1 IC testing refers to providing test stimulus (X) to the device under test (DUT) based on its characteristics and functions, and comparing the DUT output response (Y) with the expected output to determine whether the DUT meets the specifications. The test vector is the input stimulus stream, which is the logic 1 and logic 0 data applied to the DUT device pins for testing or operation in each clock cycle.

[0055] The tester can write a Pattern program and provide it to the ATE device. The ATE device executes the Pattern program to generate the test vectors and expected responses required by the tester. The component that executes the Pattern program to generate output is called ALPG. In the Pattern program, the tester often needs to let the ATE device generate a series of random numbers as input stimuli for the DUT. For example, part of the pseudo code of the Pattern program is as follows:

[0056] PRANDOM LFSR 8; specifies the pseudo-random number generation algorithm LFSR and random number bit width

[0057] REGISTER; Register initialization list

[0058] RPINI1=#FF; Pseudo-random number generator initial value register setting

[0059] START #0 ...

[0061] NOP RP=RPINI1; Initial input value of pseudo-random number generator

[0062] ILOOP1 #FE D=RP RP=RP*2; loop, each loop RP=RP*2 generates a pseudo-random number ...

[0064] PATEND; Pattern program ends

[0065] In this example, each line of Pattern statement is an instruction for one cycle. This syntax is suitable for low-frequency ATE equipment.

[0066] It should be noted that ALPG is a DSP component that generates signals for communication with DDR (memory) chips. ALPG can run Pattern programs to output address, data, and control signals to DDR. Pattern programs contain instructions similar to CPU sequence, loop, jump, etc., which enables ALPG to output various complex signal flows based on short Pattern programs written by testers.

[0067] ALPG generally runs at a frequency of 100-200MHZ. As DDR chip specifications continue to improve, the test machine also needs to increase the basic frequency of ALPG to 300MHz, and then apply technologies such as multi-channel interleaving to generate a signal flow that matches the high-frequency operation of DDR.

[0068] In order to increase the operating frequency of ALPG, similar to general-purpose CPUs, a multi-stage pipeline is required to implement ALPG. For example, ALPG uses a three-stage pipeline for addressing, decoding, and execution for instructions. In the loop, jump, function call, function return, interrupt and other branch instructions of the Pattern program, only after the execution cycle can the target instruction to be executed in the next cycle be clearly known. At this time, the target instruction may not have entered the decoding stage. The instructions that have completed addressing and decoding on the pipeline can only be invalidated. The target instruction needs to go through addressing and decoding before it can be executed. Refer to Figure 2 , so the Pattern program introduces 2 cycles of waiting (i.e. Figure 2 The "bubbles" in the flow are called "bubbles" or "break-out" cycles.

[0069] On general-purpose CPU processors, the "break" cycle causes the CPU to idle, resulting in reduced program execution efficiency. Therefore, general-purpose processors generally try to predict the subsequent target instructions before the branch instruction is executed by adding "instruction branch prediction" technology, and perform addressing and decoding in advance. However, for CPU processors, "break" only affects the running speed and is not a fatal problem. The current "instruction branch prediction" cannot completely eliminate the "break" cycle, and can only improve program execution efficiency by reducing the break ratio.

[0070] However, for ATE equipment, the "break" cycle of ALPG will cause unexpected signals to be inserted into the signal flow interacting with the DUT, causing the output of the ATE equipment to the DUT to be inconsistent with expectations, which in turn causes the DUT interaction to fail or obtain incorrect test results. Therefore, ALPG must have zero tolerance for "break" cycles. Since programmers cannot predict which steps will cause "break" cycles, it is difficult to avoid them during coding, and manual avoidance requires a lot of programmers' energy, which prevents programmers from focusing on pattern programming, affecting test efficiency.

[0071] Based on this, the present application provides an instruction processing method, a pattern program processing method, a device and a test system. ALPG adopts multi-stage pipeline technology to achieve high-frequency operation without generating a "break" cycle during operation.

[0072] In an exemplary embodiment, Figure 3 As shown, a method for processing instructions in ATE is provided, and the method is applied to a digital signal processor in ATE that generates test vectors. The digital signal processor may be an ALPG or other components with the same function. The method for processing instructions in ATE includes:

[0073] Step 302, in the i-th cycle, address the next cycle prediction instruction determined in the i-1th cycle to obtain the addressed instruction of the i-th cycle; and determine the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each Pattern instruction in the Pattern program.

[0074] It should be noted that the embodiment of the present application is explained by taking the instruction processing method in the ATE as an example to be applied to ALPG. Wherein, i is an integer greater than. It can be understood that one pipeline stage occupies one clock cycle of ALPG, and the i-th cycle refers to any clock cycle after the ALPG is running. ALPG completes the function of the pipeline stage corresponding to the i-th cycle within the clock of the i-th cycle. The ALPG of this embodiment adopts multi-stage pipeline technology, which divides an instruction into three steps of addressing, decoding and execution. In the same clock cycle, the addressing stage, decoding stage and execution stage of ALPG are carried out in parallel.

[0075] In an optional implementation, after ALPG starts running, in the first cycle, the current instruction is initialized to the PC value (instruction count value) of the pattern program running start instruction, and starts running based on the current instruction. Specifically, ALPG performs address processing on the pattern program running start instruction, obtains the addressed instruction of the first cycle, and determines the next cycle predicted instruction and the next cycle predicted instruction corresponding to the current instruction according to the instruction jump prediction table, so as to prepare for the next pipeline stage (i.e., the addressing stage of the next cycle). ALPG does not need to perform decoding and execution processing in the first cycle.

[0076] In the addressing stage of the i-th cycle, the next cycle prediction instruction determined in the i-1th cycle (i.e., the previous cycle) (determined by pre-reading the instruction jump prediction table) is used as the current addressing instruction of the i-th cycle, and the current addressing instruction is addressed to obtain the addressed instruction of the i-th cycle, so as to be used in the decoding stage of the i+1th cycle (i.e., the next cycle). And through the PC value of the current instruction, the instruction jump prediction table is queried, and the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction are pre-read, so as to be used in the addressing stage of the i+1th cycle (i.e., the next cycle), wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle. It can be understood that since ALPG has not obtained the decoded instruction in the second cycle, there is no need to perform execution processing; the current instruction of the second cycle is the target instruction determined in the first cycle. It should be noted that the current instruction of the i-th cycle is one of the one or more next cycle prediction instructions determined in the i-3th cycle.

[0077] It is understandable that in the traditional pipeline, only one instruction is supported in the addressing stage and the decoding stage. Figure 2 It can be seen that this method may produce a "broken flow" cycle. Considering that the jump or loop instruction in the Pattern program has two directions: executing the next jump instruction, or executing the jump target instruction. The next cycle prediction instruction corresponding to the same Pattern instruction in the instruction jump prediction table may be one or more. In other words, the current instruction of the i-th cycle may be multiple, and in the addressing stage, multiple instructions can be addressed in parallel. Addressing the target instructions that may be executed in subsequent cycles in advance can avoid the generation of "broken flow" cycles.

[0078] In an optional implementation, ALPG performs address processing on the current address instruction in the i-th cycle to obtain the addressed instruction of the i-th cycle; and determines the next cycle predicted instruction and the next cycle predicted instruction corresponding to the current address instruction according to the instruction jump prediction table; wherein the current address instruction is the next cycle predicted instruction determined in the i-1th cycle. That is, in each cycle, ALPG pre-reads the next cycle predicted instruction and the next cycle predicted instruction of the current address instruction for use in the addressing stage of the i+1th cycle (i.e., the next cycle).

[0079] In an optional implementation, ALPG performs address processing on the current address instruction in the i-th cycle to obtain the addressed instruction of the i-th cycle; the current address instruction is the predicted instruction of the next cycle corresponding to the current instruction in the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle. It can be understood that the predicted instruction of the next cycle of the instruction to be executed in the current cycle is addressed in advance for use in the addressing stage of the i+1th cycle (i.e., the next cycle).

[0080] Step 304, decoding the addressed instruction of the (i-1)th cycle to obtain the decoded instruction of the i-th cycle.

[0081] Among them, in the decoding stage, the addressed instruction of the i-1th cycle (i.e., the previous cycle) is decoded to obtain the decoded instruction of the i-th cycle, so as to be used in the execution stage of the i+1th cycle. It can be understood that the decoding stage of this embodiment also supports decoding multiple instructions in parallel, for example, in the addressing stage of the i-1th cycle, multiple current addressed instructions are addressed to obtain multiple addressed instructions; in the decoding stage of the i-th cycle, multiple addressed instructions are decoded.

[0082] Step 306, according to the target instruction determined in the i-1th cycle, one of the decoded instructions of the i-1th cycle is executed to form a current execution instruction; and after the current instruction is executed, the target instruction of the i+1th cycle is determined.

[0083] Among them, after the instruction is executed in the i-1th cycle, the target instruction of the next cycle (i.e., the i-th cycle) will be clarified. Since the addressing and decoding of the predicted instruction have been completed based on the instruction jump prediction table before the i-th cycle, the target instruction to be executed in the i-th cycle must appear in the decoded instruction of the i-1th cycle. Based on this, in the execution stage of the i-th cycle, ALPG directly executes the target instruction decoded in the i-1th cycle, which can avoid the generation of "broken flow" cycles. After completing the execution process, the target instruction of the next cycle (i.e., the i+1th cycle) is clarified for use in the execution stage of the i+1th cycle. It can be understood that the decoded instructions of the i-1th cycle are one or more, including the target instruction determined in the i-1th cycle, and the instruction executed in the i-th cycle is the target instruction clarified after the result of the execution of the i-1th cycle instruction.

[0084] It can be understood that ALPG completes the execution processing of the instruction in the i-th cycle, generates a test vector and inputs it to the chip under test, and ATE compares and judges based on the output response of the chip under test and the expected response to obtain the test result.

[0085] For example, the Pattern program is shown in Table 1 below, which includes multiple Pattern instructions. Assuming the number of loops is 3, the expected ideal execution order of the program is shown in Table 2, the ideal ALPG pipeline execution order is shown in Table 3, and the instruction jump prediction table corresponding to the Pattern program is shown in Table 4.

[0086] Table 1:

[0087]

[0088] Table 2:

[0089]

[0090] Table 3:

[0091]

[0092] Table 4:

[0093]

[0094] For the Pattern programs shown in Tables 1 to 4, the instruction processing process of ALPG in each cycle is shown in the following Tables 5 to 15 using the method of the embodiment of the present application.

[0095] Table 5:

[0096]

[0097] Table 6:

[0098]

[0099] Table 7:

[0100]

[0101] Table 8:

[0102]

[0103] Table 9:

[0104]

[0105] Table 10:

[0106]

[0107] Table 11:

[0108]

[0109] Table 12:

[0110]

[0111] Table 13:

[0112]

[0113] Table 14:

[0114]

[0115] Table 15:

[0116]

[0117] For example, the Pattern program is shown in Table 16 below, which includes multiple Pattern instructions. The expected ideal execution order of the program is shown in Table 17, the ideal ALPG pipeline execution order is shown in Table 18, and the instruction jump prediction table corresponding to the Pattern program is shown in Table 19.

[0118] Table 16:

[0119]

[0120] Table 17:

[0121]

[0122] Table 18:

[0123]

[0124] Table 19:

[0125]

[0126] For the Pattern programs shown in Tables 16 to 19, the instruction processing process of ALPG in each cycle is shown in Tables 20 to 26 below using the method of the embodiment of the present application.

[0127] Table 20:

[0128]

[0129] Table 21:

[0130]

[0131] Table 22:

[0132]

[0133] Table 23:

[0134]

[0135] Table 24:

[0136]

[0137] Table 25:

[0138]

[0139] Table 26:

[0140]

[0141] In the instruction processing method in the above ATE, in the i-th cycle, the next cycle prediction instruction determined in the i-1th cycle is addressed to obtain the addressed instruction of the i-th cycle; and according to the instruction jump prediction table, the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction are determined; wherein, the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each Pattern instruction in the Pattern program; the addressed instruction of the i-1th cycle is decoded to obtain the decoded instruction of the i-th cycle; according to the target instruction determined in the i-1th cycle, one of the decoded instructions of the i-1th cycle is executed to form the current execution instruction; and the target instruction of the i+1th cycle is determined after the current instruction is executed. In the above manner, addressing, decoding and execution are performed in parallel in the same cycle, addressing the instruction predicted in the previous cycle, decoding the instruction already addressed in the previous cycle, and executing the instruction already decoded in the previous cycle, so as to realize the processing of Pattern instructions through the operation mode of multi-stage pipeline, improve the efficiency of generating test signals in ATE, and thus improve the efficiency of chip automatic testing. Based on the instruction jump prediction table, the addressing and decoding of the predicted instruction are completed in advance. On the one hand, the target instruction currently being processed has been decoded in the previous cycle. On the other hand, due to the advance derivation and prediction, the target instruction of the next cycle is determined to be one of the decoded instructions in the current cycle, which can avoid the generation of "broken flow" cycle.

[0142] In an exemplary embodiment, the method further includes: obtaining a compiled Pattern program; the compiled Pattern program includes a register initialization list, a Pattern instruction, and an instruction jump prediction table; initializing a register space according to the register initialization list, loading the Pattern instruction into an instruction storage space, and loading the instruction jump prediction table into a table space.

[0143] Among them, refer to Figure 4The test machine is an ATE device. The test machine includes ALPG. ALPG includes register space, IM space (Instruction Memory, instruction storage space), instruction jump prediction table JumpTab space, program sequence controller (Program Sequence Controller) and address / data / control signal generator (Address / Data / Controller Signalling Generator). The Pattern compiler compiles the original Pattern program and outputs the compiled Pattern program, including a register initialization list, compiled Pattern instructions and instruction jump prediction table JumpTab. The compiled Pattern program is imported into the test machine. The test machine interacts with ALPG and performs the following steps: initialize the register space, load the Pattern instruction into the instruction storage space, load the instruction jump prediction table JumpTab into the table space, and control the operation of ALPG.

[0144] In an optional implementation, the compiled Pattern program is loaded into the test machine by the operator to prepare for subsequent testing. The operator loads the compiled Pattern program into ALPG through the test machine programming control path. Before running the compiled Pattern program, the test machine initializes the register space of ALPG according to the Pattern program. The test machine loads the compiled Pattern instructions into the IM space of ALPG. The test machine loads the instruction jump prediction table JumpTab and writes it into the "instruction jump prediction table JumpTab" table space of ALPG. After the running preparation is completed, ALPG starts to execute the compiled Pattern program.

[0145] In this embodiment, by initializing the register space, loading the instruction storage space and the table space, data support is provided for the subsequent instruction processing process, which can ensure the orderly processing of instructions and improve the instruction processing efficiency.

[0146] In an exemplary embodiment, the addressing process of the next cycle prediction instruction determined in the i-1th cycle includes: obtaining an instruction count value from an addressing instruction set; the addressing instruction set stores the instruction count value of the next cycle prediction instruction determined in the i-1th cycle; and addressing the next cycle prediction instruction determined in the i-1th cycle according to the instruction count value;

[0147] After determining the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table, the method further comprises: storing the instruction count value of the next cycle prediction instruction of the current instruction into the next jump instruction set, and storing the instruction count value of the next cycle prediction instruction of the current instruction into the next jump instruction set;

[0148] After determining the target instruction of the i+1th cycle, the method also includes: after the i-th cycle, transferring the data of the next jump instruction set into the address instruction set, transferring the data of the next-down jump instruction set into the next jump instruction set, and clearing the next-down jump instruction set.

[0149] Among them, refer to Figure 5, the ALPG program sequence controller includes an instruction prefetch module, an instruction addressing module, an instruction decoding module and an instruction execution module, and is provided with an addressing instruction set, a next jump instruction set and a next jump instruction set. After ALPG starts running, the "addressing instruction set" of ALPG is initialized to the PC value of the start instruction of the Pattern program. The instruction prefetching steps are as follows: 1. During ALPG operation, the "instruction addressing module" of the "program sequence controller" of ALPG performs addressing processing on the instructions in the "addressing instruction set". For each instruction in the "addressing instruction set", the "instruction addressing module" calls the "instruction prefetching module" to check the "instruction jump prediction table JumpTab". 2. The "instruction prefetching module" checks the "instruction jump prediction table JumpTab": the PC value of the current instruction is input as the table lookup index value. The structure of the "instruction jump prediction table JumpTab" is shown in the above-mentioned Table 4 and Table 19. 3. The "instruction jump prediction table JumpTab" outputs the next cycle prediction instruction and the next cycle prediction instruction of the current instruction. 4. The predicted instructions for the next cycle are stored in the "next jump instruction set" table. If the added instruction already exists in the set, it will not be added repeatedly. The predicted instructions for the next cycle are stored in the "next jump instruction set" table. If the added instruction already exists in the set, it will not be added repeatedly. 5. The "instruction addressing module" obtains the "next jump instruction set" table and the "next jump instruction set" table for each instruction in the "addressing instruction set". 6. Because there will be one or more instructions in the "next jump instruction set" table and the "next jump instruction set" table, the ALPG "addressing" and "decoding" stages must support the addressing and decoding of multiple instructions in parallel. The "instruction decoding module" and the "instruction addressing module" operate in parallel to complete the decoding of the addressing instructions that have been taken in the previous cycle. The "instruction execution module" and the "instruction addressing module" operate in parallel to complete the execution of the decoded instructions in the previous cycle, and according to the instruction execution, the target instruction of the next cycle is clarified. As a result, the previous advance instruction predicts addressing and decoding, and the next cycle target instruction specified by the "instruction execution module" must appear in one or more instructions that have been decoded before, thus avoiding the generation of "broken flow cycle". 7. After the current cycle is over, the content of the "next jump instruction set" table is transferred to the "addressing instruction set" table; the "next jump instruction set" table is transferred to the "next jump instruction set"; the "next jump instruction set" is cleared; go to step 1, and repeat this cycle until the Pattern program ends (the "PATEND" instruction is encountered).

[0150] In this embodiment, multiple instruction sets are set to store the next cycle prediction instruction and the next cycle prediction instruction of the current instruction, and data is updated after the instruction is completed, so as to provide data support for subsequent cycles. In the address fetching stage, there is no need to query data again from the instruction jump prediction table, and data can be directly obtained from the address fetching instruction set, which simplifies the processing logic.

[0151] In an exemplary embodiment, the method further includes: in the first cycle, taking the starting instruction of the Pattern program as the current address instruction for addressing processing to obtain the addressed instruction of the first cycle; determining the next cycle predicted instruction and the next cycle predicted instruction corresponding to the current address instruction according to the instruction jump prediction table; and taking the next cycle predicted instruction corresponding to the current address instruction as the target instruction of the next cycle.

[0152] Among them, referring to the above Tables 1 to 26, in the first cycle (i.e., i=1), ALPG has not yet obtained the addressed instruction and the decoded instruction, and cannot perform decoding and addressing processing; when i=1, there is no i-1th cycle. At this time, ALPG initializes the current addressed instruction to the PC value (instruction count value) of the Pattern program running start instruction, and starts running based on the current instruction. Specifically, ALPG performs addressing processing on the Pattern program running start instruction, obtains the addressed instruction of the first cycle, and determines the next cycle predicted instruction and the next cycle predicted instruction corresponding to the current instruction according to the instruction jump prediction table, so as to prepare for the next pipeline stage (i.e., the addressing stage of the next cycle) to use.

[0153] In the first cycle, the next cycle prediction instruction corresponding to the current addressed instruction is used as the target instruction of the next cycle. In the addressing stage of the second cycle, ALPG performs addressing processing on the next cycle prediction instruction determined in the first cycle to obtain the addressed instruction of the second cycle; and determines the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the target instruction determined in the first cycle; the addressed instruction of the first cycle is decoded to obtain the decoded instruction of the second cycle; no execution processing is required.

[0154] Starting from the third cycle, ALPG enters the execution cycle according to the aforementioned steps 302 to 306, executes the target instruction determined in the previous cycle in the execution stage, and determines the target instruction of the next cycle.

[0155] In an exemplary embodiment, Figure 6 As shown, a Pattern program processing method is provided, the method comprising:

[0156] Step 602, obtaining an original Pattern program; the original Pattern program includes a plurality of Pattern instructions.

[0157] It can be understood that the Pattern program processing method is applied to a computer device, which is connected to a chip automated test equipment (ie, ATE) to send the compiled Pattern program to the ATE. Figure 4The computer device is provided with a Pattern compiler, and each Pattern instruction in the original Pattern program is compiled and processed by the Pattern compiler.

[0158] Step 604 , predict the next cycle instruction of each Pattern instruction, and determine the next cycle predicted instruction corresponding to each Pattern instruction.

[0159] Step 606 , predict the next-next-cycle instruction of each Pattern instruction, and determine the next-next-cycle predicted instruction corresponding to each Pattern instruction.

[0160] The compilation process includes: for each Pattern instruction in the original Pattern program, deriving and predicting the possible instructions of the instruction in the next cycle to obtain the predicted instructions for the next cycle; deriving and predicting the possible instructions of the instruction in the next cycle to obtain the predicted instructions for the next cycle.

[0161] Step 608 , generating an instruction jump prediction table according to the next cycle prediction instructions and the next cycle prediction instructions corresponding to the plurality of Pattern instructions.

[0162] Among them, the "instruction jump prediction table JumpTab" of the Pattern program is formed according to the next cycle prediction instruction and the next cycle prediction instruction of each Pattern instruction derived by the compilation process, and the result is shown in Table 27 below.

[0163] Table 27:

[0164]

[0165] Step 610, generating a compiled Pattern program according to the original Pattern program and the instruction jump prediction table; transmitting the compiled Pattern program to the chip automatic test equipment, wherein the chip automatic test equipment performs the following steps according to the compiled Pattern program: in the i-th cycle, addressing the next cycle prediction instruction determined in the i-1th cycle to obtain the addressed instruction of the i-th cycle; and determining the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; decoding the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle; executing one of the decoded instructions of the i-1th cycle according to the target instruction determined in the i-1th cycle to form the current execution instruction; and determining the target instruction of the i+1th cycle after the current instruction is executed.

[0166] Among them, referring to the aforementioned Figure 4 As shown, the compiled Pattern program includes a register initialization list, a Pattern instruction, and an instruction jump prediction table. The Pattern compiler transmits the compiled Pattern program to the ATE device, which executes the Pattern program and tests the chip under test based on the execution result. The specific execution method of the chip automated test equipment refers to the explanation of the instruction processing method in the ATE in the aforementioned embodiment, which will not be repeated here.

[0167] In this embodiment, by compiling the original Pattern program, a Pattern program including an instruction jump prediction table is generated and transmitted to the chip automatic test equipment, so that the chip automatic test equipment can: perform addressing, decoding and execution in parallel in the same cycle, address the instructions predicted in the previous cycle, decode the instructions addressed in the previous cycle, and execute the instructions decoded in the previous cycle, so as to realize the processing of Pattern instructions through the operation mode of the multi-stage pipeline, improve the generation efficiency of test signals in ATE, and thus improve the chip automatic test efficiency. Based on the instruction jump prediction table, the addressing and decoding of the predicted instructions are completed in advance. On the one hand, the target instruction currently being processed has been decoded in the previous cycle. On the other hand, due to the advance derivation and prediction, the target instruction of the next cycle determined is one of the decoded instructions in the current cycle, which can avoid the generation of the "broken flow" cycle.

[0168] In an exemplary embodiment, step 604 includes: for each Pattern instruction, if the current Pattern instruction is a sequential instruction, the instruction count value of the current Pattern instruction is increased by one to obtain a first target count value; the Pattern instruction corresponding to the first target count value is determined as the next cycle prediction instruction corresponding to the current Pattern instruction; if the current Pattern instruction is a jump loop instruction, the Pattern instruction corresponding to the first target count value and the jump target Pattern instruction of the jump loop instruction are determined as the next cycle prediction instruction corresponding to the current Pattern instruction.

[0169] Among them, for each Pattern instruction, if the current Pattern instruction is a sequential instruction, the instruction corresponding to the current instruction PC+1 is used as the next cycle prediction instruction of the current Pattern instruction. Referring to the aforementioned Table 34, "Next jump prediction 1" and "Next jump prediction 2" are filled with the same PC value (i.e., current instruction PC+1).

[0170] If the current pattern instruction is a jump loop instruction, the instruction corresponding to the current instruction PC+1 and the jump target instruction of the jump loop instruction are used as the next cycle prediction instruction of the current pattern instruction. Referring to the aforementioned Table 34, "Next jump prediction 1" is filled with the PC value of the jump target instruction, and "Next jump prediction 2" is filled with the current instruction PC+1.

[0171] In an exemplary embodiment, step 606 includes: obtaining the next cycle prediction instruction corresponding to each Pattern instruction; for each Pattern instruction, if the next cycle prediction instruction of the current Pattern instruction is a sequential instruction, then adding one to the instruction count value of the next cycle prediction instruction of the current Pattern instruction to obtain a second target count value; determining the Pattern instruction corresponding to the second target count value as the next cycle prediction instruction corresponding to the current Pattern instruction; if the next cycle prediction instruction of the current Pattern instruction is a jump loop instruction, then determining the Pattern instruction corresponding to the second target count value and the jump target Pattern instruction of the jump loop instruction as the next cycle prediction instruction corresponding to the current Pattern instruction.

[0172] Among them, for each Pattern instruction, if the next cycle prediction instruction of the current Pattern instruction is a sequential instruction, the instruction corresponding to the next cycle prediction instruction PC+1 is used as the next cycle prediction instruction of the current Pattern instruction. Referring to the aforementioned Table 34, "PCNXT0" and "PCNXT1" are filled with the same PC value (i.e., the next cycle prediction instruction PC+1).

[0173] If the next cycle prediction instruction of the current Pattern instruction is a jump loop instruction, the instruction corresponding to the next cycle prediction instruction PC+1 and the jump target instruction of the jump loop instruction are used as the next cycle prediction instruction of the current Pattern instruction. Referring to the aforementioned Table 34, "PCNXT0" is filled with the PC value of the jump target instruction, and "PCNXT1" is filled with the next cycle prediction instruction PC+1.

[0174] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0175] Based on the same inventive concept, the embodiment of the present application also provides an instruction processing device in ATE for implementing the instruction processing method in ATE involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of one or more instruction processing devices in ATE provided below can refer to the limitations of the instruction processing method in ATE above, and will not be repeated here.

[0176] In an exemplary embodiment, Figure 7 As shown, an instruction processing device in ATE is provided, comprising:

[0177] The instruction addressing module 702 is used to perform addressing processing on the next cycle prediction instruction determined in the (i-1)th cycle in the i-th cycle to obtain the addressed instruction of the i-th cycle;

[0178] The instruction prefetch module 704 is used to determine the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1-th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each Pattern instruction in the Pattern program.

[0179] The instruction decoding module 706 is used to decode the addressed instruction of the (i-1)th cycle to obtain the decoded instruction of the (i)th cycle.

[0180] The instruction execution module 708 is used to execute one of the decoded instructions of the i-1th cycle according to the target instruction determined in the i-1th cycle to form a current execution instruction; and determine the target instruction of the i+1th cycle after the current instruction is executed.

[0181] In the instruction processing device in the above ATE, addressing, decoding and execution are performed in parallel in the same cycle, addressing the instruction predicted in the previous cycle, decoding the instruction already addressed in the previous cycle, and executing the instruction already decoded in the previous cycle, so as to realize the processing of Pattern instructions through the operation mode of the multi-stage pipeline, improve the efficiency of generating test signals in ATE, and thus improve the efficiency of chip automatic testing. Based on the instruction jump prediction table, the addressing and decoding of the predicted instruction are completed in advance. On the one hand, the target instruction currently being processed has been decoded in the previous cycle. On the other hand, due to the advance derivation and prediction, the target instruction of the next cycle is determined to be one of the decoded instructions in the current cycle, which can avoid the generation of "broken flow" cycles.

[0182] In an exemplary embodiment, the instruction processing device in the ATE also includes a loading module, which is used to obtain a compiled Pattern program; the compiled Pattern program includes a register initialization list, a Pattern instruction and an instruction jump prediction table; initialize the register space according to the register initialization list, load the Pattern instruction into the instruction storage space, and load the instruction jump prediction table into the table space.

[0183] In an exemplary embodiment, the instruction processing device in the ATE further includes an update module;

[0184] The instruction addressing module 702 is further used to obtain an instruction count value from an addressing instruction set; the addressing instruction set stores the instruction count value of the next cycle prediction instruction determined in the i-1th cycle; according to the instruction count value, perform addressing processing on the next cycle prediction instruction determined in the i-1th cycle; store the instruction count value of the next cycle prediction instruction of the current instruction in the next jump instruction set, and store the instruction count value of the next cycle prediction instruction of the current instruction in the next jump instruction set;

[0185] The update module is used to transfer the data of the next jump instruction set into the address instruction set, transfer the data of the next jump instruction set into the next jump instruction set, and clear the next jump instruction set after the i-th cycle.

[0186] In an exemplary embodiment, the instruction addressing module 702 is further used to perform addressing processing on the start instruction of the Pattern program as the current addressing instruction in the first cycle to obtain the addressed instruction of the first cycle;

[0187] The instruction prefetch module 704 is also used to determine the next cycle predicted instruction and the next cycle predicted instruction corresponding to the current address instruction according to the instruction jump prediction table; and use the next cycle predicted instruction corresponding to the current address instruction as the target instruction of the next cycle.

[0188] Each module in the instruction processing device in the above ATE can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0189] In an exemplary embodiment, referring to Figure 8 , provides a test system, the test system includes a chip automatic test device 802, the chip automatic test device 802 includes an ALPG unit 804; the ALPG unit 804 is used to execute the steps of the instruction processing method in the ATE described in any one of the above embodiments.

[0190] In an exemplary embodiment, the ALPG unit 804 is used to perform the following steps: in the i-th cycle, address the next cycle prediction instruction determined in the i-1th cycle to obtain the addressed instruction of the i-th cycle; and determine the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each Pattern instruction in the Pattern program; decode the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle; according to the target instruction determined in the i-1th cycle, execute one of the decoded instructions of the i-1th cycle to form the current execution instruction; and determine the target instruction of the i+1th cycle after the current instruction is executed.

[0191] In an exemplary embodiment, the ALPG unit 804 is used to perform the following steps: obtain a compiled Pattern program; the compiled Pattern program includes a register initialization list, a Pattern instruction, and an instruction jump prediction table; initialize the register space according to the register initialization list, load the Pattern instruction into the instruction storage space, and load the instruction jump prediction table into the table space.

[0192] In an exemplary embodiment, the ALPG unit 804 is used to perform the following steps: obtain an instruction count value from an addressed instruction set; the addressed instruction set stores the instruction count value of the next cycle predicted instruction determined in the i-1th cycle; according to the instruction count value, perform addressing processing on the next cycle predicted instruction determined in the i-1th cycle; store the instruction count value of the next cycle predicted instruction of the current instruction in the next jump instruction set, and store the instruction count value of the next cycle predicted instruction of the current instruction in the next next jump instruction set; after the i-th cycle, transfer the data of the next jump instruction set to the addressed instruction set, transfer the data of the next next jump instruction set to the next jump instruction set, and clear the next next jump instruction set.

[0193] In an exemplary embodiment, the ALPG unit 804 is used to perform the following steps: in the first cycle, the starting instruction of the Pattern program is used as the current address instruction for addressing processing to obtain the addressed instruction of the first cycle; according to the instruction jump prediction table, the next cycle predicted instruction and the next cycle predicted instruction corresponding to the current address instruction are determined; and the next cycle predicted instruction corresponding to the current address instruction is used as the target instruction of the next cycle.

[0194] In an exemplary embodiment, the computer device 806 is connected to the chip automatic testing device 802, and the computer device 806 is used to execute the steps of the Pattern program processing method described in any one of the above embodiments.

[0195] In an exemplary embodiment, the computer device 806 is used to perform the following steps: obtaining an original pattern program; the original pattern program includes multiple pattern instructions; predicting the next cycle instruction of each pattern instruction, and determining the next cycle prediction instruction corresponding to each pattern instruction; predicting the next cycle instruction of each pattern instruction, and determining the next cycle prediction instruction corresponding to each pattern instruction; generating an instruction jump prediction table according to the next cycle prediction instructions and the next cycle prediction instructions corresponding to the multiple pattern instructions; generating a compiled pattern program according to the original pattern program and the instruction jump prediction table; transmitting the compiled pattern program to the chip automatic test equipment 8 02, wherein the chip automatic test equipment 802 performs the following steps according to the compiled Pattern program: in the i-th cycle, addressing the next cycle prediction instruction determined in the i-1th cycle to obtain the addressed instruction of the i-th cycle; and determining the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; decoding the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle; according to the target instruction determined in the i-1th cycle, executing one of the decoded instructions of the i-1th cycle to form the current execution instruction; and determining the target instruction of the i+1th cycle after the current instruction is executed.

[0196] In an exemplary embodiment, the computer device 806 is used to perform the following steps: for each Pattern instruction, if the current Pattern instruction is a sequential instruction, the instruction count value of the current Pattern instruction is increased by one to obtain a first target count value; the Pattern instruction corresponding to the first target count value is determined as the next cycle prediction instruction corresponding to the current Pattern instruction; if the current Pattern instruction is a jump loop instruction, the Pattern instruction corresponding to the first target count value and the jump target Pattern instruction of the jump loop instruction are determined as the next cycle prediction instruction corresponding to the current Pattern instruction.

[0197] In an exemplary embodiment, the computer device 806 is used to perform the following steps: obtain the next cycle prediction instruction corresponding to each Pattern instruction; for each Pattern instruction, if the next cycle prediction instruction of the current Pattern instruction is a sequential instruction, then add one to the instruction count value of the next cycle prediction instruction of the current Pattern instruction to obtain a second target count value; determine the Pattern instruction corresponding to the second target count value as the next cycle prediction instruction corresponding to the current Pattern instruction; if the next cycle prediction instruction of the current Pattern instruction is a jump loop instruction, then determine the Pattern instruction corresponding to the second target count value and the jump target Pattern instruction of the jump loop instruction as the next cycle prediction instruction corresponding to the current Pattern instruction.

[0198] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0199] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the memory, database or other medium mentioned in each embodiment provided by the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0200] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0201] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for processing instructions in ATE, characterized in that: The method comprises: In the i-th cycle, address processing is performed on the next cycle prediction instruction determined in the i-1th cycle to obtain the addressed instruction of the i-th cycle; and according to the instruction jump prediction table, the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction are determined; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each pattern instruction in the pattern program; Decode the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle; According to the target instruction determined in the i-1th cycle, one of the decoded instructions in the i-1th cycle is executed to form a current execution instruction; and after the current instruction is executed, the target instruction of the i+1th cycle is determined.

2. The method according to claim 1, characterized in that: The method further comprises: Obtaining a compiled Pattern program; the compiled Pattern program includes a register initialization list, a Pattern instruction, and an instruction jump prediction table; Initialize the register space according to the register initialization list, load the Pattern instruction into the instruction storage space, and load the instruction jump prediction table into the table space.

3. The method according to claim 1, characterized in that The addressing process of the next cycle prediction instruction determined in the (i-1)th cycle includes: Acquire an instruction count value from an addressing instruction set; the addressing instruction set stores the instruction count value of the next cycle prediction instruction determined in the i-1th cycle; According to the instruction count value, address processing is performed on the next cycle prediction instruction determined in the (i-1)th cycle; After determining the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table, the method further includes: The instruction count value of the next cycle prediction instruction of the current instruction is stored in the next jump instruction set, and the instruction count value of the next cycle prediction instruction of the current instruction is stored in the next jump instruction set; After determining the target instruction of the (i+1)th cycle, the method further includes: After the i-th cycle, the data of the next-hop instruction set is transferred into the address instruction set, the data of the next-down-jump instruction set is transferred into the next-hop instruction set, and the next-down-jump instruction set is cleared.

4. The method according to claim 1, characterized in that The method further comprises: In the first cycle, the starting instruction of the Pattern program is used as the current address instruction for addressing processing to obtain the addressed instruction of the first cycle; according to the instruction jump prediction table, the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current address instruction are determined; and the next cycle prediction instruction corresponding to the current address instruction is used as the target instruction of the next cycle.

5. A Pattern program processing method, characterized in that: The method comprises: Obtaining an original Pattern program; the original Pattern program includes a plurality of Pattern instructions; Predict the next cycle instruction of each Pattern instruction, and determine the next cycle predicted instruction corresponding to each Pattern instruction; Predict the next cycle instruction of each Pattern instruction, and determine the next cycle prediction instruction corresponding to each Pattern instruction; Generate an instruction jump prediction table according to the next cycle prediction instructions and the next cycle prediction instructions corresponding to the multiple pattern instructions; Generate a compiled Pattern program according to the original Pattern program and the instruction jump prediction table; transmit the compiled Pattern program to the chip automatic test equipment, wherein the chip automatic test equipment performs the following steps according to the compiled Pattern program: in the i-th cycle, address the next cycle prediction instruction determined in the i-1th cycle to obtain the addressed instruction of the i-th cycle; and determine the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; decode the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle; according to the target instruction determined in the i-1th cycle, execute one of the decoded instructions of the i-1th cycle to form the current execution instruction; and determine the target instruction of the i+1th cycle after the current instruction is executed.

6. The method according to claim 5, characterized in that The predicting the next cycle instruction of each Pattern instruction and determining the next cycle predicted instruction corresponding to each Pattern instruction includes: For each Pattern instruction, if the current Pattern instruction is a sequential instruction, the instruction count value of the current Pattern instruction is incremented by one to obtain a first target count value; the Pattern instruction corresponding to the first target count value is determined as the next cycle prediction instruction corresponding to the current Pattern instruction; If the current Pattern instruction is a jump loop instruction, the Pattern instruction corresponding to the first target count value and the jump target Pattern instruction of the jump loop instruction are determined as the next cycle prediction instruction corresponding to the current Pattern instruction.

7. The method according to claim 5, characterized in that The predicting the next cycle instruction of each Pattern instruction and determining the next cycle predicted instruction corresponding to each Pattern instruction includes: Get the next cycle prediction instruction corresponding to each Pattern instruction; For each Pattern instruction, if the next cycle predicted instruction of the current Pattern instruction is a sequential instruction, the instruction count value of the next cycle predicted instruction of the current Pattern instruction is increased by one to obtain a second target count value; the Pattern instruction corresponding to the second target count value is determined as the next cycle predicted instruction corresponding to the current Pattern instruction; If the next cycle predicted instruction of the current Pattern instruction is a jump loop instruction, the Pattern instruction corresponding to the second target count value and the jump target Pattern instruction of the jump loop instruction are determined as the next cycle predicted instruction corresponding to the current Pattern instruction.

8. An instruction processing device in ATE, characterized in that: The device comprises: An instruction fetching module is used to fetch the next cycle predicted instruction determined in the i-1th cycle in the i-th cycle, and obtain the fetched instruction of the i-th cycle; An instruction prefetch module is used to determine the next cycle prediction instruction and the next cycle prediction instruction corresponding to the current instruction according to the instruction jump prediction table; wherein the current instruction is the instruction to be executed in the i-th cycle, that is, the target instruction determined in the i-1th cycle; the instruction jump prediction table includes the next cycle prediction instruction and the next cycle prediction instruction corresponding to each pattern instruction in the pattern program; An instruction decoding module is used to decode the addressed instruction of the i-1th cycle to obtain the decoded instruction of the i-th cycle; The instruction execution module is used to execute one of the decoded instructions of the i-1th cycle according to the target instruction determined in the i-1th cycle to form a current execution instruction; and determine the target instruction of the i+1th cycle after the current instruction is executed.

9. A testing system, characterized in that: The test system comprises a chip automated test device, and the chip automated test device comprises an ALPG unit; the ALPG unit is used to execute the steps of the method according to any one of claims 1 to 4.

10. The system according to claim 9, characterized in that The test system further comprises a computer device, which is connected to the chip automated test device and is used to execute the steps of the method according to any one of claims 5 to 7.

Images