Self-voltage-sharing MMC sub-module topology system with direct-current fault clearing capability
By designing a self-equalization dual-port parallel submodule with DC fault blocking capability, the problem of half-bridge MMC being unable to self-clear the fault current on the DC side and the capacitance voltage equalization of the submodule is solved, and the rapid fault clearance and self-equalization functions are realized, reducing the design difficulty of the MMC controller.
Patent Information
- Application Number
- CN202411837078.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-03-14
AI Technical Summary
Half-bridge MMC cannot rely on itself to clear the DC-side fault current and the submodule capacitance voltage equalization problems.
A self-equalization dual-port parallel submodule (SBDPSM) with DC fault blocking capability is proposed. This submodule has both fault self-clearing capability and capacitance self-equalization capability of the submodule in the bridge arm.
It realizes rapid DC fault clearance under the premise of ensuring economicality, reduces the fault recovery time, ensures rapid restart after troubleshooting, and does not require complex voltage equalization control through the self-equalization function, reducing the design difficulty of the MMC controller.
Smart Images
Figure CN119628392A_ABST
Abstract
Description
Technical Field
[0001] The invention discloses a self-balanced MMC submodule topology system with direct current fault clearing capability, which relates to the technical field of flexible direct current power transmission. Summary of the invention
[0002] In the flexible DC transmission system, the two-level and three-level voltage source converters or modular multilevel converters (MMC) currently used, when a short circuit fault occurs on the DC side, even if all the sub-modules of the MMC are locked, the converter station will still feed current to the fault through the diodes because the IGBT is connected in parallel with the freewheeling diode. In view of the above defects, the MMC can be equipped with the fault self-clearing capability by improving the sub-module topology of the MMC, such as using the MMC with a full-bridge sub-module (FBSM). At present, an important direction of flexible DC transmission technology is to develop MMC sub-modules with the DC side fault self-clearing capability.
[0003] FBSM has strong fault current blocking capability and the ability to output negative level, but it requires twice as many fully controlled devices per unit level as HBSM. In recent years, many scholars at home and abroad have proposed many new sub-modules with DC fault blocking capabilities. These new sub-modules have improved the use of unit level devices compared to FBSM, but have abandoned other aspects, such as not having negative level output capability, more complex structure, high control difficulty, and slow DC fault clearing speed.
[0004] The modular design makes it impossible to keep the capacitor voltage of each submodule of MMC balanced if it is not controlled. The current control method is generally implemented based on various sorting algorithms. There are many submodules of high-voltage modular multi-level converters in actual projects. Sorting a large number of submodules in a very short control cycle places extremely high requirements on the processor. At present, the control methods for submodule capacitor voltage balance can be divided into three categories, namely, the voltage balancing method based on submodule capacitor voltage sorting, the voltage balancing method based on hardware circuit, and the submodule capacitor voltage self-balancing control strategy that does not require capacitor voltage sampling. The traditional sorting voltage balancing calculation is large, the controller requirements are high, and it may increase the delay of the control link, which affects the current dynamic tracking characteristics of MMC. The voltage balancing method based on hardware circuit enables the submodule to have self-voltage balancing capability, and no voltage balancing sorting calculation is required, which effectively reduces the requirements for the MMC controller. Therefore, it is necessary to design a new solution to meet the actual usage needs. Summary of the invention
[0005] The present invention aims to solve the problem that the half-bridge MMC cannot rely on itself to clear the DC side fault current and balance the sub-module capacitor voltage. A self-balancing dual-port parallel sub-module (voltage self-balancing dual-port sub-module, SBDPSM) with DC fault blocking capability is proposed, which has both fault self-clearing capability and sub-module capacitor self-balancing capability in the bridge arm, providing a new option for the configuration of MMC sub-module types.
[0006] In view of the deficiencies in the prior art, the present invention provides an MMC submodule topology structure with self-clearing of DC faults and self-voltage equalization. The submodule has a simple structure and can quickly clear DC faults and reduce fault recovery time while ensuring good economy. It ensures rapid restart after fault elimination and realizes self-voltage equalization. There is no need to use a controller to control the voltage equalization of the submodules within a limited control cycle, which effectively reduces the design difficulty of the MMC controller.
[0007] To achieve the above object, the present invention adopts the following technical solutions: A self-balanced voltage dual-port parallel submodule topology with DC fault blocking capability, comprising a terminal, b terminal, c terminal, d terminal, an upper left insulated gate bipolar transistor T1, an upper right insulated gate bipolar transistor T2, a lower left insulated gate bipolar transistor T3, a lower right insulated gate bipolar transistor T4, a middle lower insulated gate bipolar transistor T5, an upper left anti-parallel diode D1, an upper right anti-parallel diode D2, a lower left anti-parallel diode D3, a lower right anti-parallel diode D4, a middle lower anti-parallel diode D5, and a capacitor C; The collector of the upper left insulated gate bipolar transistor T1 is connected to the positive electrode of the capacitor C, the emitter is led to the a terminal, and the upper left anti-parallel diode D1 is anti-parallel to the upper left insulated gate bipolar transistor T1; The emitter of the upper right insulated gate bipolar transistor T2 is connected to the negative electrode of the capacitor C, the collector is led out as the b terminal, and the upper right anti-parallel diode D2 is anti-parallel connected to the upper right insulated gate bipolar transistor T2; The collector of the lower left insulated gate bipolar transistor T3 is connected to the positive electrode of the capacitor C, the emitter is connected to the c terminal, and the lower left anti-parallel diode D3 is anti-parallel to the lower left insulated gate bipolar transistor T3; The emitter of the lower right insulated gate bipolar transistor T4 is connected to the negative electrode of the capacitor C, the collector is led out as the d terminal, and the lower right anti-parallel diode D4 is anti-parallel connected to the lower right insulated gate bipolar transistor T4; The collector of the lower middle insulated gate bipolar transistor T5 is connected to the emitter of the lower left insulated gate bipolar transistor T3, and the emitter is connected to the collector of the lower right insulated gate bipolar transistor T4. The lower middle anti-parallel diode D5 is anti-parallel connected to the lower middle insulated gate bipolar transistor T5.
[0008] To optimize the above technical solutions, the specific measures taken also include: Furthermore, a working control method based on the self-balanced dual-port parallel submodule topology with DC fault blocking capability includes: The working modes of the submodule topology structure include two conditions: normal working and DC fault. The self-balanced dual-port parallel submodule topology with DC fault blocking capability is hereinafter referred to as submodule; In normal working mode, according to the switching state of the insulated gate bipolar transistor, the submodule can operate in positive, negative and cut-off states, and output any one of the three levels of one capacitance voltage, negative one capacitance voltage and zero voltage.
[0009] Furthermore, the positive investment working state of the submodule is divided into two modes: series positive investment and parallel positive investment. The parallel positive investment is further divided into three states: parallel positive investment starting module, parallel positive investment middle module, and parallel positive investment termination module. When the submodule is working in the parallel positive investment state, the MMC bridge arm where it is located starts from a module in the state of parallel positive investment starting and ends at a module in the state of parallel positive investment termination. In the middle are several modules in the state of parallel positive investment middle (which can be 0). The submodules in this section are in the parallel working state, and the submodule capacitors are connected in parallel and connected in series into the bridge arm in a forward manner, and the output voltage is one times the capacitor voltage. At the same time, since the submodule capacitors are connected in parallel, the electric energy automatically flows from the capacitor with high voltage to the capacitor with low voltage, and the voltage will automatically tend to balance, realizing the self-equalizing voltage capability of the submodule. The series positive investment can be regarded as a special case in which the number of submodules in the parallel working submodule section is 1.
[0010] Specifically: When the insulated gate bipolar transistors T1, T4, and T5 of the submodule are turned on and T2 and T3 are turned off, the working state is series forward, and the submodule outputs one times the capacitor voltage; When the insulated gate bipolar transistors T1, T3, and T4 of the submodule are turned on and T2 and T5 are turned off, the working state is a series positive-throw start module, which outputs one-time capacitance voltage together with the parallel submodule; When the insulated gate bipolar transistors T1, T2, T3, and T4 of the submodule are turned on and T5 is turned off, the working state is the series positive-throw intermediate module, and the parallel submodule outputs one-time capacitance voltage together. It should be noted that the insulated gate bipolar transistors of the parallel negative-throw intermediate module, the parallel cut-off intermediate module, and the parallel blocking intermediate module are exactly the same as those of the series positive-throw intermediate module; When the insulated gate bipolar transistors T1, T2, T4, and T5 of the submodule are turned on and T3 is turned off, the working state is a series positive termination module, which outputs one times the capacitor voltage together with the parallel submodule; Furthermore, the negative throw working state of the submodule is divided into two modes: series negative throw and parallel negative throw. The negative throw is further divided into three states: parallel negative throw starting module, parallel negative throw intermediate module, and parallel negative throw termination module. When the submodule works in the parallel negative throw state, the MMC bridge arm where it is located starts from a module in the state of parallel negative throw starting and ends at a module in the state of parallel negative throw termination. In between are several modules in the state of parallel intermediate (can be 0). The submodule in this section is in the parallel working state, and its submodule capacitors are connected in parallel and then reversely connected in series into the bridge arm, and the output voltage is negative one times the capacitor voltage. Similarly, the parallel capacitors will automatically complete the voltage equalization process.
[0011] Specifically: When the insulated gate bipolar transistors T2, T3, and T5 of the submodule are turned on and T1 and T4 are turned off, the working state is series negative input, and the submodule outputs a negative voltage of one times the capacitance; When the insulated gate bipolar transistors T2, T3, and T4 of the submodule are turned on and T1 and T5 are turned off, the working state is a series negative input start module, which outputs a negative one-time capacitance voltage together with the parallel submodule; When the insulated gate bipolar transistors T1, T2, T3, and T5 of the submodule are turned on and T4 is turned off, the working state is a series negative-throw termination module, which outputs a negative one-time capacitance voltage together with the parallel submodule; Furthermore, the submodule's removal working state is divided into two modes: series removal and parallel removal. Series removal is further divided into series removal 1 and series removal 2, and parallel removal is further divided into parallel removal termination 1 and parallel removal termination 2. When the starting module state of the parallel removal submodule section is the parallel positive start module state, the termination submodule needs to be set to the parallel negative end module state or the parallel removal termination module state 1. When the starting module state of the parallel removal submodule section is the parallel negative start module state, the termination submodule needs to be set to the parallel positive end module state or the parallel removal termination module state 2. When the submodule works in the parallel removal state, the MMC bridge arm in which it is located starts from a module in the state of parallel removal start and ends at a module in the state of parallel removal termination, with several modules in the middle of the state (which can be 0). The submodules in this section are in parallel working state, and the submodule capacitors are bypassed out of the bridge arm after being connected in parallel, and the output voltage is zero. Similarly, the parallel capacitors will automatically complete the voltage equalization process.
[0012] Specifically: When the insulated gate bipolar transistors T1 and T3 of the submodule are turned on, T2 and T4 are turned off, and T5 is in any state, the working state is series removal 1, and the submodule outputs zero voltage; When the insulated gate bipolar transistors T2 and T4 of the submodule are turned on, T1 and T3 are turned off, and T5 is in any state, the working state is series removal 2, and the submodule outputs zero voltage; When the insulated gate bipolar transistors T1, T2, and T3 of the submodule are turned on and T4 and T5 are turned off, the working state is the parallel removal termination module state 1, and the submodule outputs zero voltage; When the insulated gate bipolar transistors T1, T2, and T4 of the submodule are turned on and T3 and T5 are turned off, the working state is the parallel removal termination module state 2, and the submodule outputs zero voltage; In the DC fault mode, the submodule is locked so that the submodule works in the locked state. The capacitor in the submodule outputs a capacitor voltage in the opposite direction of the fault current in the submodule, so that the fault DC is offset. The locking working state of the submodule is divided into two modes: series locking and parallel locking. The parallel locking is further divided into three states: parallel locking starting module, parallel locking intermediate module, and parallel locking termination module. When the submodule works in the parallel locking state, the MMC bridge arm where it is located starts from a module with a state of parallel locking starting and ends at a module with a state of parallel locking termination. In the middle are several modules with a state of parallel intermediate (can be 0). The submodule in this section is in a parallel working state. After the submodule capacitor is connected in parallel, it is connected in series into the bridge arm. The direction is always opposite to the fault current of the bridge arm, and the output is a capacitor voltage that is twice the opposite to the fault current. Similarly, the parallel capacitors will automatically complete the voltage equalization process.
[0013] Specifically: When all the insulated gate bipolar transistors of the submodule are turned off, the working state is series blocking, and the submodule outputs a capacitor voltage that is one times the voltage in the opposite direction of the fault current; When the insulated gate bipolar transistors T3 and T4 of the submodule are turned on and T1, T2 and T5 are turned off, the working state is the parallel blocking start module, which together with the parallel submodule outputs a capacitor voltage that is one time the opposite of the fault current; When the insulated gate bipolar transistors T1 and T2 of the submodule are turned on and T3, T4 and T5 are turned off, the working state is a parallel blocking termination module, which outputs a capacitor voltage that is one time the opposite of the fault current together with the parallel submodule.
[0014] Furthermore, the modulation and voltage balancing method based on the submodule includes: The bridge arm connection of the modular multilevel converter is constructed based on the submodule topology, specifically: the modular multilevel converter includes three-phase bridge arms A', B', and C', each phase bridge arm is composed of an upper bridge arm and a lower bridge arm, a total of six bridge arms, the submodules are connected in parallel, that is, the a and b ends of the submodules are respectively connected to the c and d ends of the upper submodule of the bridge arm, the a and b ends of the uppermost submodule of the bridge arm are short-circuited as the positive pole of the bridge arm, the c and d ends of the lowermost submodule of the bridge arm are short-circuited, and T5 is deleted as the negative pole of the bridge arm, so as to complete the bridge arm connection of the modular multilevel converter; In order to ensure a better voltage balancing effect and lower conduction loss, when formulating the voltage balancing strategy, it is necessary to ensure that all sub-modules of the bridge arm are fully connected in parallel, and the number of parallel sub-modules in each section should be kept consistent as much as possible; After calculating the number of bridge arm submodules Non put into operation according to the nearest level approximation modulation, when the number of bridge arm submodules N can be divided by the number of inputs Non, the bridge arm submodules are evenly divided into Non sections, and each section is connected in parallel with N / Non submodules. When the number of bridge arm submodules N cannot be divided by the number of inputs Non, let the remainder be R, and the number of parallel submodules in the R section is selected to be one more than that in other parallel sections. In order to make the switching frequency of the submodules lower and take into account the voltage balancing effect, the number of parallel submodules in the front R or rear R section can be fixedly selected to be one more than that in the others, to ensure that the states of more submodules do not change; The submodule has the ability to output negative level. When the submodule needs negative input, this method is also applicable. You only need to change the status of the parallel start and end modules to negative input.
[0015] Further, in order to reduce the hardware cost of MMC, it can be mixed with other sub-modules without fault-through capability to form a hybrid sub-module type MMC. The traditional half-bridge sub-module has no self-equalizing function. After mixed use, it will still bring difficulties to the MMC in sampling, sorting and equalizing the sub-module capacitor voltage. In order to ensure that the bridge arm of the hybrid sub-module still has the self-equalizing function, the sub-module is simplified. A simplified self-equalizing two-port parallel sub-module topology is obtained, hereinafter referred to as a simplified sub-module, and its structure is to short-circuit the collector and emitter of the upper left insulated gate bipolar transistor T1 and the lower right insulated gate bipolar transistor T4 of the sub-module, and delete T1, T4, D1, D4, and the positions of T2, T3, T5, D2, D3, D5, and C remain unchanged. The simplified sub-module reduces the cost and retains the original self-equalizing function, but loses the negative level output capability and DC fault clearing capability, and can be used to form a hybrid sub-module MMC system with other sub-modules with self-equalizing function.
[0016] The submodule has good DC fault blocking capability and self-voltage balancing function. The hybrid submodule solution using simplified submodules can retain the self-voltage balancing characteristics and DC fault blocking capability of the submodule while reducing the cost of the converter. The submodule does not need to sample and sort the capacitor voltage in real time, reducing the requirements of the MMC on the controller, sensor and communication system. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 The topological diagram of the self-balanced MMC submodule with DC fault clearing capability of the present invention is shown.
[0018] Figure 2 The figure is a schematic diagram of the working state of the self-voltage-equalizing MMC submodule with DC fault clearing capability of the present invention.
[0019] Figure 3 The invention provides a blocking current path for the self-balanced MMC submodule with direct current fault clearing capability.
[0020] Figure 4 It is a schematic diagram of the basic topological structure of the three-phase modular multilevel converter of the present invention.
[0021] Figure 5 This is a schematic diagram of the parallel working principle of the submodules of the present invention.
[0022] Figure 6 It is a schematic diagram of the flow chart of the modulation and voltage equalization method of the submodule of the present invention.
[0023] Figure 7 This is a simplified topological diagram of a self-equalizing dual-port parallel submodule according to the present invention.
[0024] Figure 8 This is a simplified schematic diagram of the self-equalizing dual-port parallel submodules forming the MMC bridge arm of the present invention.
[0025] Fig. 9 This is a hybrid MMC steady-state output waveform diagram consisting of the submodule of the present invention and its simplified version with no fault clearing capability, wherein the ratio of the submodule to the simplified submodule is 1:1.
[0026] Fig.10 This is the AC output voltage waveform of the three-phase MMC constructed by the present invention when the modulation ratio is 1.25.
[0027] Fig.11 It is a schematic diagram comparing the effects of the submodule self-voltage balancing function of the present invention and the traditional sorting voltage balancing function.
[0028] Fig.12 It is a schematic diagram of simulation verification of DC fault blocking capability of the submodule of the present invention.
[0029] Fig.13It is a schematic diagram for simulation verification of the DC fault blocking capability of the hybrid MMC composed of the submodule of the present invention and the simplified submodule. DETAILED DESCRIPTION
[0030] The specific implementation plan of this program is as follows: In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the following reference is made to the attached Figure 1-13 It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the protection scope of the present invention.
[0031] Now combine with Figure 1-13 The present invention is described in further detail.
[0032] Example 1, reference Figure 1 , is a topological schematic diagram of a self-equalizing MMC submodule with DC fault clearing capability of the present invention. The submodule of the present invention can be formed by combining five insulated gate bipolar transistors, five diodes and a capacitor in a specific manner as shown in the figure.
[0033] Example 2, reference Figure 2 , which is a schematic diagram of the working state of the self-balanced MMC submodule with DC fault clearing capability of the present invention. By inputting the control signal in the table to each insulated gate bipolar transistor of the submodule, the submodule can be made to work in a specific working state.
[0034] Example 3, reference Figure 3 , which is a self-equalizing MMC submodule with DC fault clearing capability of the present invention, and blocks the current path. After all the insulated gate bipolar transistors of the submodule are locked, the submodule can always output a voltage opposite to the direction of the fault current regardless of the current direction. The diode withstands the reverse voltage and blocks, thereby quickly blocking the short-circuit current.
[0035] Example 4, reference Figure 4 , is a schematic diagram of the basic topological structure of the three-phase modular multilevel converter of the present invention. The submodules are connected as shown to form a bridge arm, and then six bridge arms are connected as shown to form a three-phase MMC.
[0036] Example 5, reference Figure 5, is a schematic diagram of the parallel working principle of the submodules of the present invention. When the submodules are put into operation in parallel, the capacitors of each bridge arm section submodule put into operation in parallel are first connected in parallel and then connected in series to the bridge arm. When the submodules are removed in parallel, the capacitors of each bridge arm section submodule removed in parallel are first connected in parallel and then bypassed out of the bridge arm. When the submodules are blocked in parallel, the capacitors of each bridge arm section submodule blocked in parallel are first connected in parallel and then connected to the bridge arm. Due to the effect of the diode, the submodule access direction is always opposite to the fault current direction, and the DC side fault current is quickly blocked. The energy in the capacitors connected in parallel will automatically flow from the capacitor with high voltage to the capacitor with low voltage, and the automatic voltage balancing function can be realized.
[0037] Example 6, reference Figure 6 , which is a flow chart of the modulation and voltage balancing method of the submodule of the present invention. It should be noted that, when designing the MMC, the working state of the submodule corresponding to the number of inputs of each bridge arm can be obtained through this process, and the control signal is generated and stored. When the MMC is working, each control cycle only needs to calculate the number of inputs of the bridge arm according to the nearest level approximation modulation, and select the corresponding control signal according to the number of inputs, which greatly reduces the calculation amount of the submodule voltage balancing process and effectively reduces the requirements for the MMC controller.
[0038] Example 7, reference Figure 7 , which is a simplified schematic diagram of the topology of the self-equalizing two-port parallel submodule of the present invention. The simplified submodule can be obtained by simplifying the upper left insulated gate bipolar transistor T1 and the lower right insulated gate bipolar transistor T4 and their anti-parallel diodes D1 and D4 of the self-equalizing MMC submodule with DC fault clearing capability of the present invention into short-circuit lines. The simplified submodule effectively reduces the usage during power electronics, reduces hardware costs and operating losses, has no fault self-clearing capability and negative level output capability, but retains the self-equalizing capability, and can be used to form a hybrid MMC with the submodule of the present invention to reduce hardware costs. If the submodule of the present invention and the traditional half-bridge submodule with no fault self-clearing capability form a hybrid MMC, the half-bridge submodule in the bridge arm still needs to be subjected to voltage equalization control. Therefore, the mixed use of simplified submodules and submodules with self-equalizing capability has great advantages.
[0039] Embodiment 8, reference 8, is a schematic diagram of the simplified self-equalizing dual-port parallel submodules of the present invention forming an MMC bridge arm. The simplified submodule can be placed above or below the self-equalizing MMC submodule with DC fault clearing capability in the bridge arm. To ensure that the simplified submodule section can be bypassed when a fault occurs, the T4 tube of the last submodule in the simplified submodule section needs to be retained. At the same time, when the simplified submodule is located at the bottom of the bridge arm, the insulated gate bipolar transistor T5 and its anti-parallel diode D5 can also be omitted.
[0040] Example 9, reference Fig. 9, is a hybrid MMC steady-state output waveform diagram consisting of the submodule of the present invention and a simplified version of its fault-free clearing capability, wherein the ratio of the submodule to the simplified submodule is 1:1. It can be seen that without the need to sort and balance the submodule capacitor voltages in real time, the submodule capacitor voltages still tend to be balanced, the output power quality of the MMC is relatively high, and the submodule of the present invention has the ability to balance the voltages between the submodules in the bridge arm.
[0041] Example 10, reference Fig.10 , is the AC output voltage waveform of the three-phase MMC constructed by the present invention when the modulation ratio is 1.25. Since the submodule of the present invention has the ability to output negative levels, it can realize the operation mode with the modulation ratio m greater than 1, so that the output AC phase voltage peak value is greater than the DC unipolar voltage. Although the mixed simplified submodule has no negative level output capability, the mixed atomic module can still output negative levels normally. As shown in the figure, this is the AC output voltage waveform when the modulation ratio is 1.25. The number of levels of the MMC output voltage has increased, which improves the quality of the output voltage waveform.
[0042] Example 11, reference 11, is a schematic diagram comparing the effects of the submodule self-equalizing function of the present invention and the traditional sorting equalizing function. In order to compare the effects of the submodule self-equalizing and the fully sorted equalizing function of the present invention, only the equalizing mode of the simulation system is changed to insertion sorting equalizing, and the other system parameters remain unchanged. The controller cycle is 200 ms, and the comparison of the equalizing effect is shown in the figure. It can be seen that under the same control cycle, the self-equalizing control can achieve the same equalizing effect as the fully sorted equalizing.
[0043] Example 12, reference 12, is a schematic diagram for simulation verification of the DC fault blocking capability of the present invention. The most serious bipolar short-circuit fault of the DC system is simulated, and the fault is set when the system runs to 0.500 s. Considering the time for the system to detect the fault, the converter is locked after a delay of 1 ms, that is, at 0.501 s. The changes in the DC side voltage, DC side current, AC side current and submodule capacitor voltage value before and after the converter is locked are shown in the figure. It can be seen that after the bipolar short-circuit fault occurs, before the MMC is locked, the submodule capacitor and the AC system discharge to the short circuit, the submodule capacitor voltage drops rapidly, and the DC current instantly increases to several times the rated value. After the MMC is locked, the submodule capacitor absorbs the energy of the DC network, the voltage rises, and then remains unchanged. The AC current first rises, and then the DC voltage and DC current are quickly suppressed and maintained at zero. The simulation results show that the reverse electromotive force provided by the submodule plays a role in isolating AC and DC, and verify that the submodule of the present invention has good DC fault blocking capability.
[0044] Example 13, reference 13, is a schematic diagram of simulation verification of the DC fault blocking capability of a hybrid MMC composed of a submodule of the present invention and a simplified submodule. The submodule capacitor absorbs DC network energy and the voltage rises, but the simplified submodule is bypassed, the capacitor voltage value remains unchanged, and the DC voltage and DC current are quickly suppressed to zero. It can be seen that the submodule of the present invention retains its self-voltage balancing function and DC fault blocking capability by mixing with its simplified version, reducing the investment cost of the converter.
[0045] The present invention provides an MMC submodule topology structure with self-clearing of DC faults and self-voltage equalization. The submodule has a simple structure and can quickly clear DC faults and reduce fault recovery time while ensuring good economy. It ensures rapid restart after fault elimination and realizes the self-voltage equalization function. There is no need to perform voltage equalization control on the submodules through a controller within a limited control cycle, which effectively reduces the design difficulty of the MMC controller.
Claims
1. A self-equalizing dual-port parallel submodule topology with DC fault blocking capability, characterized in that: Including terminal a, terminal b, terminal c, terminal d, upper left insulated gate bipolar transistor T1, upper right insulated gate bipolar transistor T2, lower left insulated gate bipolar transistor T3, lower right insulated gate bipolar transistor T4, lower middle insulated gate bipolar transistor T5, upper left anti-parallel diode D1, upper right anti-parallel diode D2, lower left anti-parallel diode D3, lower right anti-parallel diode D4, lower middle anti-parallel diode D5, capacitor C; The collector of the upper left insulated gate bipolar transistor T1 is connected to the positive electrode of the capacitor C, the emitter is led to the a terminal, and the upper left anti-parallel diode D1 is anti-parallel to the upper left insulated gate bipolar transistor T1; The emitter of the upper right insulated gate bipolar transistor T2 is connected to the negative electrode of the capacitor C, the collector is led out as the b terminal, and the upper right anti-parallel diode D2 is anti-parallel connected to the upper right insulated gate bipolar transistor T2; The collector of the lower left insulated gate bipolar transistor T3 is connected to the positive electrode of the capacitor C, the emitter is connected to the c terminal, and the lower left anti-parallel diode D3 is anti-parallel to the lower left insulated gate bipolar transistor T3; The emitter of the lower right insulated gate bipolar transistor T4 is connected to the negative electrode of the capacitor C, the collector is led out as the d terminal, and the lower right anti-parallel diode D4 is anti-parallel connected to the lower right insulated gate bipolar transistor T4; The collector of the lower middle insulated gate bipolar transistor T5 is connected to the emitter of the lower left insulated gate bipolar transistor T3, and the emitter is connected to the collector of the lower right insulated gate bipolar transistor T4. The lower middle anti-parallel diode D5 is anti-parallel connected to the lower middle insulated gate bipolar transistor T5.
2. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 1, characterized in that: The working control method based on the self-balanced dual-port parallel submodule topology with DC fault blocking capability includes: The working modes of the submodule topology structure include two conditions: normal working and DC fault. The self-balanced dual-port parallel submodule topology with DC fault blocking capability is hereinafter referred to as submodule; In normal working mode, according to the switching state of the insulated gate bipolar transistor, the submodule can operate in positive, negative and cut-off states, and output any one of the three levels of one capacitance voltage, negative one capacitance voltage and zero voltage.
3. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 2, characterized in that: The positive throw working state of the submodule is divided into two modes: series positive throw and parallel positive throw. The parallel positive throw is further divided into three states: parallel positive throw starting module, parallel positive throw intermediate module, and parallel positive throw termination module. When the submodule works in the parallel positive throw state, the MMC bridge arm where it is located starts from a module in the state of parallel positive throw starting and ends at a module in the state of parallel positive throw termination. In between are several modules in the state of parallel positive throw intermediate. The submodules in this section are in the parallel working state. After the submodule capacitors are connected in parallel, they are connected in series in the bridge arm in a positive manner, and the output voltage is one times the capacitor voltage. At the same time, since the submodule capacitors are connected in parallel, the electric energy automatically flows from the capacitor with high voltage to the capacitor with low voltage, and their voltages will automatically tend to balance, realizing the self-equalizing voltage capability of the submodule. The series positive throw can be regarded as a special case where the number of submodules in the parallel working submodule section is 1.
4. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 3 is characterized in that: When the insulated gate bipolar transistors T1, T4, and T5 of the submodule are turned on and T2 and T3 are turned off, the working state is series forward, and the submodule outputs one times the capacitor voltage; When the insulated gate bipolar transistors T1, T3, and T4 of the submodule are turned on and T2 and T5 are turned off, the working state is a series positive-throw start module, which outputs one-time capacitance voltage together with the parallel submodule; When the insulated gate bipolar transistors T1, T2, T3, and T4 of the submodule are turned on and T5 is turned off, the working state is the series positive-throw intermediate module, and the parallel submodule outputs one-time capacitance voltage together. It should be noted that the insulated gate bipolar transistors of the parallel negative-throw intermediate module, the parallel cut-off intermediate module, and the parallel blocking intermediate module are exactly the same as those of the series positive-throw intermediate module; When the insulated gate bipolar transistors T1, T2, T4 and T5 of the sub-module are turned on and T3 is turned off, the working state is a series positive termination module, which outputs one times the capacitor voltage together with the parallel sub-module.
5. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 2, characterized in that: The negative throw working state of the submodule is divided into two modes: series negative throw and parallel negative throw. The negative throw is further divided into three states: parallel negative throw starting module, parallel negative throw intermediate module, and parallel negative throw termination module. When the submodule works in the parallel negative throw state, the MMC bridge arm where it is located starts from a module in the state of parallel negative throw starting and ends at a module in the state of parallel negative throw termination. In between are several modules in the state of parallel intermediate. The submodule in this section is in the parallel working state. After the submodule capacitors are connected in parallel, they are reversely connected in series into the bridge arm, and the output voltage is negative one times the capacitor voltage. Similarly, the parallel capacitors will automatically complete the voltage equalization process.
6. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 5, characterized in that: When the insulated gate bipolar transistors T2, T3, and T5 of the submodule are turned on and T1 and T4 are turned off, the working state is series negative input, and the submodule outputs a negative voltage of one times the capacitance; When the insulated gate bipolar transistors T2, T3, and T4 of the submodule are turned on and T1 and T5 are turned off, the working state is a series negative input start module, which outputs a negative one-time capacitance voltage together with the parallel submodule; When the insulated gate bipolar transistors T1, T2, T3, and T5 of the sub-module are turned on and T4 is turned off, the working state is a series negative-throw termination module, which outputs a negative one-time capacitor voltage together with the parallel sub-module.
7. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 2, characterized in that: The submodule's removal working state is divided into two modes: series removal and parallel removal. Series removal is further divided into series removal 1 and series removal 2, and parallel removal is further divided into parallel removal termination 1 and parallel removal termination 2. When the starting module state of the parallel removal submodule section is the parallel positive start module state, the termination submodule needs to be set to the parallel negative end module state or the parallel removal termination module state 1. When the starting module state of the parallel removal submodule section is the parallel negative start module state, the termination submodule needs to be set to the parallel positive end module state or the parallel removal termination module state 2. When the submodule works in the parallel removal state, the MMC bridge arm where it is located starts from a module with a state of parallel removal start and ends at a module with a state of parallel removal termination, with several modules in the middle of the state in parallel. The submodules in this section are in parallel working state, and the submodule capacitors are bypassed out of the bridge arm after being connected in parallel, and the output voltage is zero. Similarly, the parallel capacitors will automatically complete the voltage equalization process.
8. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 2, characterized in that: Specifically: When the insulated gate bipolar transistors T1 and T3 of the submodule are turned on, T2 and T4 are turned off, and T5 is in any state, the working state is series removal 1, and the submodule outputs zero voltage; When the insulated gate bipolar transistors T2 and T4 of the submodule are turned on, T1 and T3 are turned off, and T5 is in any state, the working state is series removal 2, and the submodule outputs zero voltage; When the insulated gate bipolar transistors T1, T2, and T3 of the submodule are turned on and T4 and T5 are turned off, the working state is the parallel removal termination module state 1, and the submodule outputs zero voltage; When the insulated gate bipolar transistors T1, T2, and T4 of the submodule are turned on and T3 and T5 are turned off, the working state is the parallel removal termination module state 2, and the submodule outputs zero voltage.
9. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 2, characterized in that: In the DC fault mode, the submodule is locked so that the submodule works in the locked state. The capacitor in the submodule outputs a capacitor voltage in the opposite direction of the fault current in the submodule, so that the fault DC is offset. The locking working state of the submodule is divided into two modes: series locking and parallel locking. The parallel locking is further divided into three states: parallel locking starting module, parallel locking intermediate module, and parallel locking termination module. When the submodule works in the parallel locking state, the MMC bridge arm where it is located starts from a module in the state of parallel locking starting and ends at a module in the state of parallel locking termination. In the middle are several modules in the state of parallel intermediate. The submodule in this section is in the parallel working state. The submodule capacitor is connected in parallel and then connected in series to the bridge arm. The direction is always opposite to the fault current of the bridge arm, and the output is one times the capacitor voltage opposite to the fault current. Similarly, the parallel capacitors will automatically complete the voltage equalization process.
10. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 9, characterized in that: Specifically: When all the insulated gate bipolar transistors of the submodule are turned off, the working state is series blocking, and the submodule outputs a capacitor voltage that is one times the voltage in the opposite direction of the fault current; When the insulated gate bipolar transistors T3 and T4 of the submodule are turned on and T1, T2 and T5 are turned off, the working state is the parallel blocking start module, which together with the parallel submodule outputs a capacitor voltage that is one time the opposite of the fault current; When the insulated gate bipolar transistors T1 and T2 of the submodule are turned on and T3, T4 and T5 are turned off, the working state is a parallel blocking termination module, which outputs a capacitor voltage that is one time the opposite of the fault current together with the parallel submodule.
11. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 2, characterized in that: The modulation and voltage balancing method based on the submodule includes: The bridge arm connection of the modular multilevel converter is constructed based on the submodule topology, specifically: the modular multilevel converter includes three-phase bridge arms A', B', and C', each phase bridge arm is composed of an upper bridge arm and a lower bridge arm, a total of six bridge arms, the submodules are connected in parallel, that is, the a and b ends of the submodules are respectively connected to the c and d ends of the upper submodule of the bridge arm, the a and b ends of the uppermost submodule of the bridge arm are short-circuited as the positive pole of the bridge arm, the c and d ends of the lowermost submodule of the bridge arm are short-circuited, and T5 is deleted as the negative pole of the bridge arm, so as to complete the bridge arm connection of the modular multilevel converter; In order to ensure a better voltage balancing effect and lower conduction loss, when formulating the voltage balancing strategy, it is necessary to ensure that all sub-modules of the bridge arm are fully connected in parallel, and the number of parallel sub-modules in each section should be kept consistent as much as possible; After calculating the number of bridge arm submodules Non put into operation according to the nearest level approximation modulation, when the number of bridge arm submodules N is divisible by the number of inputs Non, the bridge arm submodules are evenly divided into Non sections, and each section is connected in parallel with N / Non submodules; when the number of bridge arm submodules N is not divisible by the number of inputs Non, the remainder is set to R, and the number of parallel submodules in the R section is selected to be one more than that in other parallel sections; in order to make the switching frequency of the submodules lower and take into account the voltage balancing effect, the number of parallel submodules in the front R or rear R section is fixedly selected to be one more than that in other sections, so as to ensure that the states of more submodules do not change; The submodule has the ability to output negative level. When the submodule needs negative input, this method is also applicable. You only need to change the state of the parallel start and end modules to negative input.
12. The self-voltage-equalizing dual-port parallel submodule topology with DC fault blocking capability according to claim 2, characterized in that: In order to reduce the hardware cost of MMC, it is mixed with other sub-modules without fault ride-through capability to form a hybrid sub-module type MMC. The traditional half-bridge sub-module has no self-equalizing function. After mixed use, it will still bring difficulties to the MMC in sampling, sorting and equalizing the sub-module capacitor voltage. In order to ensure that the hybrid sub-module bridge arm still has the self-equalizing function, the sub-module is simplified; A simplified self-equalizing two-port parallel submodule topology is obtained, hereinafter referred to as the simplified submodule, whose structure is that the collector and emitter of the upper left insulated gate bipolar transistor T1 and the lower right insulated gate bipolar transistor T4 of the submodule are short-circuited, and T1, T4, D1, D4 are deleted, and the positions of T2, T3, T5, D2, D3, D5, and C remain unchanged; the simplified submodule reduces the cost and retains the original self-equalizing function, but loses the negative level output capability and DC fault clearing capability, and can be used to form a hybrid submodule MMC system with other submodules with self-equalizing function.