Nine-pin single-fiber bidirectional low-speed long-distance optical module

Abstract

The utility model relates to a nine-pin single-fiber bidirectional low-speed long-distance optical module, which comprises a shell, and a high-speed signal modulation / demodulation circuit, a high-speed signal driving circuit, a laser, a detector, a high-speed signal receiving circuit and a J3 which are arranged in the shell, the high-speed signal modulation / demodulation circuit is arranged on the FPGA; a pin 2 of the J3 is connected with a pin 25 of the FPGA, a pin 3 of the J3 is connected with a pin 28 of the FPGA, a pin 4 of the J3 is connected with a pin 24 of the FPGA, a pin 5 of the J3 is connected with a pin 27 of the FPGA, and a pin 6 of the J3 is connected with the pin 25 of the FPGA through an R4; a high-speed signal modulation / demodulation circuit is arranged on a small-size FPGA and integrated into the 9-pin optical module, the light receiving sensitivity of the optical module is improved through the high-speed signal modulation / demodulation circuit, long-distance transmission of low-speed signals through optical signals is achieved through a high-speed circuit optical module scheme, and the small-size advantage of the FPGA is utilized, so that the high-speed signal modulation / demodulation circuit is integrated into the 9-pin optical module. And a high-speed signal modulation / demodulation circuit is integrated into the 9-pin optical module, so that the equipment volume is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of optical communication, in particular to a 9-pin single-fiber bidirectional low-speed long-distance optical module. Background Art

[0002] At present, the transmission distance of low-speed 9-pin transceiver optical modules for communication is about 20km, which cannot meet the application requirements of transmission over 40km. Specifically, the circuits used in existing low-speed transceiver optical modules have low light receiving sensitivity, which limits the transmission distance of optical signals; on the other hand, the circuits occupy a large area and the equipment is large. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a 9-pin single-fiber bidirectional low-speed long-distance optical module to overcome the deficiencies in the above-mentioned prior art.

[0004] The utility model solves the above technical problems with the following technical solutions: a 9-pin single-fiber bidirectional low-speed long-distance optical module, comprising a housing, and a high-speed signal modulation / demodulation circuit, a high-speed signal driving circuit, a laser, a detector, a high-speed signal receiving circuit and J3 built into the housing; the high-speed signal modulation / demodulation circuit is arranged on the FPGA; the pin 2 of J3 is connected to the pin 25 of the FPGA, the pin 3 of J3 is connected to the pin 28 of the FPGA, the pin 4 of J3 is connected to the pin 24 of the FPGA, the pin 5 of J3 is connected to the pin 27 of the FPGA, and the pin 6 of J3 is connected to the pin 25 of the FPGA through R4;

[0005] It also includes 9 pins arranged on the outside of the shell, the 9 pins include two GND pins, two NC pins, two VCCT pins, one RD1 pin, one SD1 pin and one TD1 pin; the GND pin is connected to pin 3 of the FPGA, the RD1 pin is connected to pin 22 of the FPGA, the SD1 pin is connected to pin 26 of the FPGA, and the TD1 pin is connected to pin 27 of the FPGA.

[0006] The beneficial effects of the utility model are as follows: a high-speed signal modulation / demodulation circuit is arranged on a small-sized FPGA and integrated into a 9-pin optical module, the sensitivity of the optical module light reception is improved by the high-speed signal modulation / demodulation circuit, and a high-speed circuit optical module solution is used to realize long-distance transmission of low-speed signals through optical signals, and the small size advantage of the FPGA is utilized to integrate the high-speed signal modulation / demodulation circuit into the 9-pin optical module to reduce the volume of the device.

[0007] On the basis of the above technical solution, the present invention can also be improved as follows.

[0008] Furthermore, it also includes OSCF, LDO1, LDO2, C8, C9, C10, C11 and C3; Pin 1 of OSCF is connected to Pin 17 of FPGA, Pin 2 of OSCF is grounded, Pin 3 of OSCF is connected to Pin 21 of FPGA, Pin 3 of OSCF is also connected in series with R14 and then connected to the GND pin, and Pin 3 of OSCF is connected to one end of R12; Pin 1 of LDO1 is grounded, and Pin 3 of LDO1 is connected to the VCCT pin; Pin 1 of LDO2 is grounded, and Pin 2 of LDO2 is connected to one end of L1; C8, C9, C10, and C11 are connected in parallel, and one end of the parallel connection is connected to the other end of R12, Pin 2 of LDO1, Pin 3 of LDO2, Pin 1 of J3, and Pin 6, Pin 7, Pin 15, Pin 19 and Pin 31 of FPGA, and the other end of the parallel connection is grounded, and one end of C3 is connected in series, and the other end of C3 is connected to the other end of L1, and Pin 2 and Pin 18 of FPGA.

[0009] Further, the high-speed signal driving circuit includes R2, R5, R10, R11, R27, C1, C2, C5 and a signal feedback module;

[0010] One end of R11 is connected to one end of R10, one end of R2, one end of R27 and pin 1 of the laser, the other end of R2 is connected to one end of the signal feedback module, the other end of R27 is connected to pin 3 of the FPGA, the other end of the signal feedback module is connected to one end of R5, one end of C5 and pin 2 of the laser, the other ends of C5 and R5 are connected to pin 3 of the FPGA;

[0011] Pin 3 of the laser is connected to one end of C1 and one end of C2, the other end of C1 and the other end of C2 are connected to pin 3 of FPGA, and pin 4 of the laser is connected to pin 3 of FPGA;

[0012] The other end of R11 is connected to pin 1 of the FPGA, and the other end of R10 is connected to pin 8 of the FPGA.

[0013] Further, the high-speed signal receiving circuit includes R21, R24, R25, R26, C13, C14, C15, C17, C18 and a comparator;

[0014] Pin 1 of the comparator is connected to pin 16 of the FPGA, pin 1 of the comparator is connected to one end of R24, and the other end of R24 is connected to pin 20 of the FPGA; the other end of R24 is connected to one end of C18, and the other end of C18 is connected to pin 3 of the FPGA;

[0015] Pin 5 of the comparator is connected to one end of R25, one end of C15, one end of C14 and one end of R21; the other end of R21 is connected to one end of C13 and pin 1 of the detector; pin 3 of the detector is connected to one end of C17 and pin 3 of the comparator, and pin 4 of the detector is connected to the other end of C17 and pin 4 of the comparator;

[0016] The other end of C13, the other end of C14, the other end of C15, pin 2 of the detector and pin 2 of the comparator are all connected to pin 3 of the FPGA; the other end of R25 is connected to one end of R26, and the other end of R26 is connected to pin 3 of the FPGA.

[0017] Furthermore, it also includes R17, R18, C12 and XT; FPGA pin 9 and FPGA pin 10 are connected to one end of R17 and one end of R18, FPGA pin 11 is connected to the other end of R17, one end of C12 and one end of XT, the other end of R18 is connected to the other end of XT, and the other end of C12 is grounded. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a circuit diagram of the utility model. DETAILED DESCRIPTION

[0019] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0020] like Figure 1 As shown, in Example 1, a 9-pin single-fiber bidirectional low-speed long-distance optical module includes a housing, and a high-speed signal modulation / demodulation circuit, a high-speed signal driving circuit, a laser, a detector, a high-speed signal receiving circuit and J3 built into the housing; the high-speed signal modulation / demodulation circuit is arranged on the FPGA; pin 2 of J3 (burner) is connected to pin 25 of the FPGA, pin 3 of J3 is connected to pin 28 of the FPGA, pin 4 of J3 is connected to pin 24 of the FPGA, pin 5 of J3 is connected to pin 27 of the FPGA, and pin 6 of J3 is connected to pin 25 of the FPGA through R4;

[0021] It also includes 9 pins arranged on the outside of the shell, the 9 pins include two GND pins (grounding), two NC pins (not connected), two VCCT pins (power supply), one RD1 pin (data output), one SD1 pin (no light alarm, low level alarm) and one TD1 pin (data input); the GND pin is connected to pin 3 of the FPGA, the RD1 pin is connected to pin 22 of the FPGA, the SD1 pin is connected to pin 26 of the FPGA, and the TD1 pin is connected to pin 27 of the FPGA.

[0022] The high-speed signal modulation / demodulation circuit is set on a small-sized FPGA and integrated into a 9-pin optical module. The high-speed signal modulation / demodulation circuit is used to improve the sensitivity of the optical module's light reception, and the high-speed circuit optical module solution is used to realize long-distance transmission of low-speed signals through optical signals. Taking advantage of the small size of FPGA, the high-speed signal modulation / demodulation circuit is integrated into the 9-pin optical module to reduce the size of the equipment.

[0023] Embodiment 2: This embodiment is a further improvement on the basis of embodiment 1, and its details are as follows:

[0024] It also includes OSCF (filter), LDO1 (voltage regulator), LDO2 (voltage regulator), C8, C9, C10, C11 and C3; Pin 1 of OSCF is connected to Pin 17 of FPGA, Pin 2 of OSCF is grounded, Pin 3 of OSCF is connected to Pin 21 of FPGA, Pin 3 of OSCF is connected to GND pin after being connected in series with R14, Pin 3 of OSCF is connected to one end of R12; Pin 1 of LDO1 is grounded, Pin 3 of LDO1 is connected to VCCT pin. Pin 1 of LDO2 is connected to ground, and pin 2 of LDO2 is connected to one end of L1; C8, C9, C10, and C11 are connected in parallel, and one end of the parallel connection is connected to the other end of R12, pin 2 of LDO1, pin 3 of LDO2, pin 1 of J3, and pins 6, 7, 15, 19, and 31 of FPGA. The other end of the parallel connection is connected to ground, and one end of C3 is connected in series, and the other end of C3 is connected to the other end of L1, and pins 2 and 18 of FPGA. Provide a stable operating voltage for the optical module.

[0025] Embodiment 3, this embodiment is a further improvement on the basis of embodiment 1, and its details are as follows:

[0026] The high-speed signal driving circuit includes R2, R5, R10, R11, R27, C1, C2, C5 and a signal feedback module;

[0027] One end of R11 is connected to one end of R10, one end of R2, one end of R27 and pin 1 of the laser, the other end of R2 is connected to one end of the signal feedback module, the other end of R27 is connected to pin 3 of the FPGA, the other end of the signal feedback module is connected to one end of R5, one end of C5 and pin 2 of the laser, the other ends of C5 and R5 are connected to pin 3 of the FPGA;

[0028] Pin 3 of the laser is connected to one end of C1 and one end of C2, the other end of C1 and the other end of C2 are connected to pin 3 of FPGA, and pin 4 of the laser is connected to pin 3 of FPGA;

[0029] The other end of R11 is connected to pin 1 of the FPGA, and the other end of R10 is connected to pin 8 of the FPGA.

[0030] Embodiment 4: This embodiment is a further improvement on the basis of embodiment 1, and its details are as follows:

[0031] The high-speed signal receiving circuit includes R21, R24, R25, R26, C13, C14, C15, C17, C18 and a comparator;

[0032] Pin 1 of the comparator is connected to pin 16 of the FPGA, pin 1 of the comparator is connected to one end of R24, and the other end of R24 is connected to pin 20 of the FPGA; the other end of R24 is connected to one end of C18, and the other end of C18 is connected to pin 3 of the FPGA;

[0033] Pin 5 of the comparator is connected to one end of R25, one end of C15, one end of C14 and one end of R21; the other end of R21 is connected to one end of C13 and pin 1 of the detector; pin 3 of the detector is connected to one end of C17 and pin 3 of the comparator, and pin 4 of the detector is connected to the other end of C17 and pin 4 of the comparator;

[0034] The other end of C13, the other end of C14, the other end of C15, pin 2 of the detector and pin 2 of the comparator are all connected to pin 3 of the FPGA; the other end of R25 is connected to one end of R26, and the other end of R26 is connected to pin 3 of the FPGA.

[0035] Embodiment 5: This embodiment is a further improvement based on any one of Embodiments 1 to 4, and its details are as follows:

[0036] It also includes R17, R18, C12 and XT; FPGA pin 9 and FPGA pin 10 are connected to one end of R17 and one end of R18, FPGA pin 11 is connected to the other end of R17, one end of C12 and one end of XT, the other end of R18 is connected to the other end of XT, and the other end of C12 is grounded.

[0037] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A 9-pin single-fiber bidirectional low-speed long-distance optical module, characterized in that: It includes a shell, and a high-speed signal modulation / demodulation circuit, a high-speed signal driving circuit, a laser, a detector, a high-speed signal receiving circuit and J3 built in the shell; the high-speed signal modulation / demodulation circuit is arranged on the FPGA; the pin 2 of the J3 is connected to the pin 25 of the FPGA, the pin 3 of the J3 is connected to the pin 28 of the FPGA, the pin 4 of the J3 is connected to the pin 24 of the FPGA, the pin 5 of the J3 is connected to the pin 27 of the FPGA, and the pin 6 of the J3 is connected to the pin 25 of the FPGA through R4; It also includes 9 pins arranged on the outside of the shell, and the 9 pins include two GND pins, two NC pins, two VCCT pins, one RD1 pin, one SD1 pin and one TD1 pin; the GND pin is connected to pin 3 of the FPGA, the RD1 pin is connected to pin 22 of the FPGA, the SD1 pin is connected to pin 26 of the FPGA, and the TD1 pin is connected to pin 27 of the FPGA.

2. According to claim 1, a 9-pin single-fiber bidirectional low-speed long-distance optical module is characterized in that: It also includes OSCF, LDO1, LDO2, C8, C9, C10, C11 and C3; Pin 1 of the OSCF is connected to Pin 17 of the FPGA, Pin 2 of the OSCF is grounded, Pin 3 of the OSCF is connected to Pin 21 of the FPGA, Pin 3 of the OSCF is connected to the GND pin after being connected in series with R14, and Pin 3 of the OSCF is connected to one end of R12; Pin 1 of the LDO1 is grounded, and Pin 3 of the LDO1 is connected to the VCCT pin; the LD Pin 1 of O2 is grounded, and pin 2 of LDO2 is connected to one end of L1; C8, C9, C10, and C11 are connected in parallel, and one end of the parallel connection is connected to the other end of R12, pin 2 of LDO1, pin 3 of LDO2, pin 1 of J3, and pins 6, 7, 15, 19, and 31 of the FPGA, and the other end of the parallel connection is grounded, and one end of C3 is connected in series, and the other end of C3 is connected to the other end of L1, and pins 2 and 18 of the FPGA.

3. According to claim 1, a 9-pin single-fiber bidirectional low-speed long-distance optical module is characterized in that: The high-speed signal driving circuit includes R2, R5, R10, R11, R27, C1, C2, C5 and a signal feedback module; One end of the R11 is connected to one end of the R10, one end of the R2, one end of the R27 and the pin 1 of the laser, the other end of the R2 is connected to one end of the signal feedback module, the other end of the R27 is connected to the pin 3 of the FPGA, the other end of the signal feedback module is connected to one end of the R5, one end of the C5 and the pin 2 of the laser, and the other ends of the C5 and the R5 are connected to the pin 3 of the FPGA; Pin 3 of the laser is connected to one end of C1 and one end of C2, the other end of C1 and the other end of C2 are connected to pin 3 of the FPGA, and pin 4 of the laser is connected to pin 3 of the FPGA; The other end of R11 is connected to pin 1 of the FPGA, and the other end of R10 is connected to pin 8 of the FPGA.

4. The 9-pin single-fiber bidirectional low-speed long-distance optical module according to claim 1 is characterized in that: The high-speed signal receiving circuit includes R21, R24, R25, R26, C13, C14, C15, C17, C18 and a comparator; Pin 1 of the comparator is connected to pin 16 of the FPGA, pin 1 of the comparator is connected to one end of R24, and the other end of R24 is connected to pin 20 of the FPGA; the other end of R24 is connected to one end of C18, and the other end of C18 is connected to pin 3 of the FPGA; Pin 5 of the comparator is connected to one end of R25, one end of C15, one end of C14 and one end of R21; the other end of R21 is connected to one end of C13 and pin 1 of the detector; pin 3 of the detector is connected to one end of C17 and pin 3 of the comparator, and pin 4 of the detector is connected to the other end of C17 and pin 4 of the comparator; The other end of C13, the other end of C14, the other end of C15, pin 2 of the detector and pin 2 of the comparator are all connected to pin 3 of the FPGA; the other end of R25 is connected to one end of R26, and the other end of R26 is connected to pin 3 of the FPGA.

5. A 9-pin single-fiber bidirectional low-speed long-distance optical module according to any one of claims 1 to 4, characterized in that: It also includes R17, R18, C12 and XT; pin 9 of the FPGA and pin 10 of the FPGA are connected to one end of the R17 and one end of the R18, pin 11 of the FPGA is connected to the other end of the R17, one end of the C12 and one end of the XT, the other end of the R18 is connected to the other end of the XT, and the other end of the C12 is grounded.

Images