LED chip and display device

Abstract

The embodiment of the utility model belongs to the display technology, and provides an LED chip and a display device. The LED chip comprises a substrate, an epitaxial layer, an isolation layer and an electric connection structure. The epitaxial layer is disposed on the substrate. The epitaxial layer comprises an N-type semiconductor layer and a P-type semiconductor layer which are arranged in a stacked mode. The N-type semiconductor layer is located between the substrate and the P-type semiconductor layer. The N-type semiconductor layer is provided with a first channel. The P-type semiconductor layer is provided with a second channel. The first channel exposes part of the substrate along the thickness direction of the LED chip; the second channel exposes a portion of the N-type semiconductor layer. The first channel and the second channel correspond to each other in position and are communicated with each other, and the epitaxial layer is divided into a first unit cell and a second unit cell. The isolation layer is at least located in the first channel. The surface, away from the substrate, of the isolation layer is not lower than the surface, away from the substrate, of the N-type semiconductor layer. The electric connection structure is arranged on the surface of the isolation layer away from the substrate. The first unit cell and the second unit cell are electrically connected by an electrical connection structure. According to the invention, the reliability of the LED chip is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to display technology, and more particularly to an LED chip and a display device. Background Art

[0002] LED chips are the core components of LED lights. When the LED chip is powered on, the holes and electrons in the LED chip recombine under the action of the electric field, and the energy is emitted in the form of photons to form light. LED lights are widely used in indoor and outdoor display screens, landscape lighting, advertising, traffic signs and other fields.

[0003] In the prior art, LED chips have gradually developed from 3V chips to high-voltage chips such as 6V, 9V, 12V, and 18V. In the preparation process of LED high-voltage chips, an epitaxial layer is first formed on the substrate, and then a channel is etched on the epitaxial layer through an etching process, so that the epitaxial layer becomes a plurality of unit cells divided by the channel. A "concave" structure is formed between adjacent unit cells; then, a connection layer is formed in the channel, and the connection layer electrically connects two adjacent unit cells to prepare a high-voltage LED chip.

[0004] However, existing high-voltage LED chips have the problem of low reliability. Utility Model Content

[0005] The embodiments of the present application provide an LED chip and a display device, which improve the reliability of the LED chip and the display effect of the display device.

[0006] The first aspect of the present application provides an LED chip, comprising a substrate, an epitaxial layer, an isolation layer and an electrical connection structure. The epitaxial layer is arranged on the substrate. The epitaxial layer comprises an N-type semiconductor layer and a P-type semiconductor layer arranged in a stacked manner. The N-type semiconductor layer is located between the substrate and the P-type semiconductor layer.

[0007] A first channel is provided on the N-type semiconductor layer. A second channel is provided on the P-type semiconductor layer. Along the thickness direction of the LED chip, the first channel exposes a portion of the substrate; the second channel exposes a portion of the N-type semiconductor layer. The first channel and the second channel correspond to each other and are connected, and divide the epitaxial layer into a first unit cell and a second unit cell.

[0008] The isolation layer is at least located in the first channel. The surface of the isolation layer facing away from the substrate is not lower than the surface of the N-type semiconductor layer facing away from the substrate.

[0009] The electrical connection structure is disposed on a surface of the isolation layer facing away from the substrate and electrically connects the first unit cell and the second unit cell.

[0010] The beneficial effects of the present application are as follows: the isolation layer located in the first channel provides support for the electrical connection structure, which is beneficial to the formation of the electrical connection structure and improves the bonding stability between the electrical connection structure and the N-type semiconductor layer and the P-type semiconductor layer. In addition, the provision of the isolation layer improves the flatness of the LED chip, avoids the accumulation of water and abnormal elements in the first channel, reduces the reaction rate of corrosion in the first channel, and improves the reliability of the LED chip. The electrical connection structure connects the first unit cell and the second unit cell in series, so that the LED chip has two light-emitting unit cells, which increases the brightness of the LED chip.

[0011] In a possible implementation manner, a surface of the isolation layer facing away from the substrate is not higher than a surface of the P-type semiconductor layer facing away from the substrate.

[0012] In a possible implementation manner, a surface of the isolation layer facing away from the substrate and a surface of the P-type semiconductor layer facing away from the substrate are flush.

[0013] In a possible implementation, the orthographic projection of the edge of the second channel on the surface where the N-type semiconductor layer is located is arranged around the periphery of the first channel.

[0014] There is a distance between at least a portion of the edge of the second channel and the isolation layer located in the first channel, so that there is a distance between at least a portion of the first unit cell and the isolation layer.

[0015] In a possible implementation manner, the thickness of the isolation layer gradually increases along the direction from the first unit cell to the second unit cell.

[0016] In a possible implementation, the electrical connection structure includes a conductive layer and an insulating layer. The insulating layer is connected to at least a portion of the surface of the P-type semiconductor layer facing away from the substrate. At least a portion of the conductive layer is covered on the insulating layer. The conductive layer is connected to the surface of the P-type semiconductor layer facing away from the substrate.

[0017] The first end of the conductive layer is electrically connected to the first unit cell, and the second end of the conductive layer is electrically connected to the second unit cell.

[0018] In a possible implementation manner, the first end of the conductive layer is located at a gap between the first unit cell and the isolation layer, and is electrically connected to the N-type semiconductor layer of the first unit cell.

[0019] In a possible implementation manner, the second end of the conductive layer extends to a surface of the P-type semiconductor layer of the second unit cell facing away from the substrate, and is electrically connected to the P-type semiconductor layer of the second unit cell.

[0020] In a possible implementation, the substrate and the isolation layer are made of the same material and are an integrally formed part.

[0021] In a possible implementation, the LED chip further includes an active layer, and the active layer is located between the N-type semiconductor layer and the P-type semiconductor layer.

[0022] In a possible implementation manner, the surface of the substrate is uneven; and / or the surface of the isolation layer facing away from the substrate is uneven.

[0023] In a possible implementation, the number of the first channel and the number of the second channel are both multiple. The multiple first channels and the multiple second channels are arranged at intervals along the thickness direction crossing the LED chip, and correspond one to one. The multiple first channels and the multiple second channels divide the epitaxial layer into multiple unit cells.

[0024] A second aspect of the present application provides a display device, comprising a circuit substrate and the above-mentioned LED chip, wherein the LED chip is arranged on the circuit substrate.

[0025] The present application provides an LED chip and a display device, which effectively divides the epitaxial layer by placing an isolation layer in the first channel, and divides the epitaxial layer into a first unit cell and a second unit cell, thereby avoiding interference and cross-influence of charges or signals between the first unit cell and the second unit cell. At the same time, the isolation layer can provide support for the electrical connection structure, which is beneficial to the preparation of the electrical connection structure and improves the bonding stability of the electrical connection structure with the N-type semiconductor layer and the P-type semiconductor layer. In addition, the provision of the isolation layer improves the flatness of the LED chip, avoids the accumulation of water and abnormal elements in the first channel, reduces the reaction rate of corrosion in the first channel, and improves the reliability of the LED chip. The electrical connection structure connects the first unit cell and the second unit cell in series, so that the LED chip has two light-emitting units, achieving higher brightness and power output of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the implementation methods in the embodiments of the present application or the related technologies, the following is a brief introduction to the drawings required for use in the embodiments or the related technology descriptions. Obviously, the drawings described below are some embodiments of the present application, and a person skilled in the art can also obtain other drawings based on these drawings.

[0027] Figure 1 It is a structural schematic diagram of an LED chip in the prior art;

[0028] Figure 2 A schematic diagram of the structure of an LED chip provided in an embodiment of the present application;

[0029] Figure 3 A schematic structural diagram of a substrate in an embodiment of an LED chip provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of a structure for forming an epitaxial layer in an embodiment of an LED chip provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of a structure in which a first channel and a second channel are formed in an embodiment of an LED chip provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of a structure in which an isolation layer is formed in an embodiment of an LED chip provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of a structure of an insulating layer in an electrical connection structure formed in an embodiment of an LED chip provided in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of a structure of a conductive layer in an electrical connection structure formed in an embodiment of an LED chip provided in an embodiment of the present application;

[0035] Fig. 9 A schematic diagram of a structure of a protective layer in an electrical connection structure formed in an embodiment of an LED chip provided in an embodiment of the present application;

[0036] Fig.10 A schematic structural diagram of another embodiment of the LED chip provided in the embodiment of the present application in which the substrate and the isolation layer are an integrally formed part;

[0037] Fig.11 A schematic diagram of the structure of another embodiment of the LED chip provided in the embodiment of the present application after the epitaxial layer is formed;

[0038] Fig.12 A schematic diagram of the structure of another embodiment of the LED chip provided in the embodiment of the present application after a portion of the epitaxial layer is removed;

[0039] Fig.13 A schematic diagram of a structure in which a second channel is formed in another embodiment of the LED chip provided in the embodiment of the present application;

[0040] Fig.14 A schematic diagram of a structure of an insulating layer in an electrical connection structure formed in another embodiment of an LED chip provided in an embodiment of the present application;

[0041] Fig.15 A schematic diagram of a structure of a conductive layer in an electrical connection structure formed in another embodiment of an LED chip provided in an embodiment of the present application;

[0042] Fig.16 A schematic diagram of a structure of a protective layer in an electrical connection structure formed in another embodiment of an LED chip provided in an embodiment of the present application;

[0043] Fig.17 A schematic structural diagram of another embodiment of the LED chip provided in the embodiment of the present application.

[0044] Reference numerals:

[0045] 10: connection layer;

[0046] 100: substrate;

[0047] 200: epitaxial layer; 210: N-type semiconductor layer; 220: active layer; 230: P-type semiconductor layer; 240: first channel; 250: second channel;

[0048] 300: Isolation layer;

[0049] 400: electrical connection structure; 410: insulating layer; 420: conductive layer; 421: first electrode; 422: second electrode; 430: protective layer;

[0050] 500: first unit cell; 600: second unit cell. DETAILED DESCRIPTION

[0051] LED lights are widely used in indoor and outdoor display screens, landscape lighting, advertising, traffic signs and other fields. LED chips are the core components of LED lights. When the LED chip is powered on, the holes and electrons in the LED chip recombine under the action of the electric field, and the energy is emitted in the form of photons to form light.

[0052] Figure 1 The structure of an LED chip in the prior art is schematically shown.

[0053] In the prior art, LED chips have gradually developed from 3V chips to 6V, 9V, 12V, 18V and other high-voltage LED chips. High-voltage LED chips refer to light-emitting diode chips that are formed by dividing the epitaxial layer of a large-size chip into multiple single-particle cells by etching isolation channels during the production process of LED chips, and then connecting the corresponding electrodes of adjacent cells in series. In the preparation process of high-voltage LED chips, an epitaxial layer is first formed on a substrate, and then a channel is etched on the epitaxial layer through an etching process. In this way, the epitaxial layer becomes multiple cells divided by channels. Figure 1 As shown, the epitaxial layer between adjacent unit cells forms a "concave" structure. By forming a connection layer 10 in the channel, two adjacent unit cells are electrically connected to prepare a high-voltage LED chip.

[0054] However, under high temperature and high humidity environment, water vapor will enter the lamp bead and condense and gather at the "concave" structure of the LED chip. At the same time, abnormal elements such as fluorine ions, sodium elements, potassium elements, halogen elements, sulfur elements and other abnormal elements that should not exist in the design and production process of LED chips may also invade the LED chip. Under the combined action of water and abnormal elements, the LED chip will be corroded, especially at the groove of the "concave" structure. Corrosion can occur at any position of the groove of the "concave" structure. In addition, the adjacent crystal cells of the high-voltage LED chip are "concave", so that the connection layer 10 connecting the two crystal cells is also "concave". In the preparation process of the connection layer 10 of the "concave" structure, the vertical thickness of the connection layer 10 of the "concave" structure is about 30% thinner than the horizontal thickness. Therefore, the connection layer 10 of the "concave" structure is difficult to form. Moreover, the bonding force between the "concave" structure connection layer 10 and the N-type semiconductor layer and the P-type semiconductor layer is poor, and the "concave" structure connection layer 10 reduces the reliability of the LED chip. In summary, the design of multiple unit cells connected in series makes the structure of high-voltage LED chips more complex than that of 3V chips, and high-voltage LED chips have the problem of low reliability.

[0055] In view of this, the present application provides an LED chip and a display device, wherein the LED chip includes a substrate, an epitaxial layer, an isolation layer and an electrical connection structure. The epitaxial layer is arranged on the substrate. The epitaxial layer includes an N-type semiconductor layer and a P-type semiconductor layer which are stacked. The N-type semiconductor layer is located between the substrate and the P-type semiconductor layer. A first channel is arranged on the N-type semiconductor layer. A second channel is arranged on the P-type semiconductor layer. Along the thickness direction of the LED chip, the first channel exposes a portion of the substrate; the second channel exposes a portion of the N-type semiconductor layer. The first channel and the second channel correspond to each other and are connected, and divide the epitaxial layer into a first unit cell and a second unit cell. The isolation layer is at least located in the first channel. The surface of the isolation layer facing away from the substrate is not lower than the surface of the N-type semiconductor layer facing away from the substrate. The electrical connection structure is arranged on the surface of the isolation layer facing away from the substrate. The electrical connection structure electrically connects the first unit cell and the second unit cell. By placing the isolation layer in the first channel, the epitaxial layer is divided into the first unit cell and the second unit cell, which effectively divides the epitaxial layer and avoids interference and cross-influence of charges or signals between the first unit cell and the second unit cell. At the same time, the isolation layer can provide support for the electrical connection structure, which is conducive to the formation of the electrical connection structure and improves the bonding stability between the electrical connection structure and the N-type semiconductor layer and the P-type semiconductor layer. In addition, the provision of the isolation layer improves the flatness of the LED chip, avoids the accumulation of water and abnormal elements in the first channel, reduces the reaction rate of corrosion in the first channel, and improves the reliability of the LED chip. The electrical connection structure connects the first unit cell and the second unit cell in series, so that the LED chip has two light-emitting unit cells, achieving higher brightness and power output of the LED chip.

[0056] In order to make the purpose, implementation mode and advantages of the present application clearer, the exemplary implementation mode of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0057] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and common meanings.

[0058] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such products or devices.

[0059] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0060] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0061] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0062] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0063] The embodiment of the present application provides a display device. The display device provided in the embodiment of the present application can have various implementation forms, for example, it can be a smart TV, a laser projection device, a monitor, an electronic whiteboard (electronic bulletin board), an electronic table (electronic table), etc. The display device includes a circuit substrate and the above-mentioned LED chip, and the LED chip is arranged on the circuit substrate.

[0064] Specifically, the structure and beneficial effects of the LED chip will be described in the following content.

[0065] Figure 2 The structural diagram of the LED chip provided in the embodiment of the present application is schematically shown.

[0066] Reference Figure 2 As shown, an embodiment of the present application provides an LED chip, including a substrate 100, an epitaxial layer 200, an isolation layer 300 and an electrical connection structure 400. The epitaxial layer 200 is disposed on the substrate 100. The epitaxial layer 200 includes an N-type semiconductor layer 210 and a P-type semiconductor layer 230 which are stacked. The P-type semiconductor layer 230 is a semiconductor material layer doped with holes. The N-type semiconductor layer 210 is a semiconductor material layer doped with electrons. The N-type semiconductor layer 210 is located between the substrate 100 and the P-type semiconductor layer 230. When the LED chip is powered on, the N-type semiconductor layer 210 absorbs holes from the P-type semiconductor layer 230, and free electrons move in the N-type semiconductor layer 210. These free electrons and holes meet and recombine at the interface between the N-type semiconductor layer 210 and the P-type semiconductor layer 230, releasing energy, thereby generating photons to achieve the light-emitting effect of the LED.

[0067] A first channel 240 is provided on the N-type semiconductor layer 210. A second channel 250 is provided on the P-type semiconductor layer 230. Along the thickness direction of the LED chip, the first channel 240 exposes a portion of the substrate 100; the second channel 250 exposes a portion of the N-type semiconductor layer 210. The first channel 240 and the second channel 250 correspond to each other and are connected, and divide the epitaxial layer 200 into a first unit cell 500 and a second unit cell 600. The design of the first channel 240 and the second channel 250 effectively separates the first unit cell 500 and the second unit cell 600.

[0068] The isolation layer 300 is at least located in the first channel 240. The surface of the isolation layer 300 facing away from the substrate 100 is not lower than the surface of the N-type semiconductor layer 210 facing away from the substrate 100. The electrical connection structure 400 is arranged on the surface of the isolation layer 300 facing away from the substrate 100. The electrical connection structure 400 electrically connects the first unit cell 500 and the second unit cell 600. Placing the isolation layer 300 in the first channel 240 can effectively separate the first unit cell 500 and the second unit cell 600 to avoid interference and cross-influence of charges or signals. At the same time, the isolation layer 300 can provide support for the electrical connection structure 400, which is beneficial to the formation of the electrical connection structure 400 and improves the bonding stability of the electrical connection structure 400 with the N-type semiconductor layer 210 and the P-type semiconductor layer 230. In addition, the provision of the isolation layer 300 improves the flatness of the LED chip, and avoids the accumulation of water and abnormal elements in the first channel 240, the electrical connection structure 400, the connection between the electrical connection structure 400 and the P-type semiconductor layer 230, and the connection between the electrical connection structure 400 and the N-type semiconductor layer 210. The LED chip provided by the present application avoids corrosion at the isolation layer 300 located at the first channel 240, avoids corrosion at the connection between the electrical connection structure 400 and the P-type semiconductor layer 230, and the connection between the electrical connection structure 400 and the N-type semiconductor layer 210, and improves the reliability of the LED chip.

[0069] The electrical connection structure 400 connects the first unit cell 500 and the second unit cell 600 in series, so that the LED chip has two light-emitting unit cells, which increases the operating voltage of the LED chip to achieve higher brightness and power output of the LED chip.

[0070] In some possible implementations, referring to Figure 2 As shown, the LED chip further includes an active layer 220 . The active layer 220 is located between the N-type semiconductor layer 210 and the P-type semiconductor layer 230 .

[0071] Exemplarily, when the LED chip is powered on, electrons are injected from the N-type semiconductor layer 210 into the active layer 220, and holes are injected from the P-type semiconductor layer 230 into the active layer 220. In the active layer 220, the electrons and holes recombine to release energy, which is released in the form of photons to make the LED chip emit light.

[0072] Figure 3 The structural diagram of the substrate 100 in one embodiment of the LED chip provided in the embodiment of the present application is schematically shown. Figure 4 The schematic diagram of the structure of forming the epitaxial layer 200 in one embodiment of the LED chip provided in the embodiment of the present application is schematically shown. Figure 5The schematic diagram of the structure of forming the first channel 240 and the second channel 250 in one embodiment of the LED chip provided in the embodiment of the present application is schematically shown. Figure 6 The schematic diagram of the structure of forming the isolation layer 300 in one embodiment of the LED chip provided in the embodiment of the present application is schematically shown. Figures 7 to 9 The schematic diagram of the structure of forming an electrical connection structure 400 in one embodiment of the LED chip provided in the embodiment of the present application is schematically shown.

[0073] In some embodiments, reference Figures 3 to 9 As shown, the preparation process of the LED chip is: first, an epitaxial layer 200 is formed on a planar substrate 100. The epitaxial layer 200 includes an N-type semiconductor layer 210, an active layer 220, and a P-type semiconductor layer 230 which are stacked in sequence. Then, the P-type semiconductor layer 230 is etched to form a second channel 250, and the second channel 250 exposes a portion of the N-type semiconductor layer 210. The N-type semiconductor layer 210 is further etched to form a first channel 240, and the first channel 240 exposes a portion of the substrate 100. Subsequently, an isolation layer 300 is formed in the first channel 240. Then, an electrical connection structure 400 is prepared on the surface of the isolation layer 300 away from the substrate 100.

[0074] Fig.10 A schematic diagram schematically shows the structure of another embodiment of the LED chip provided by the embodiment of the present application, in which the substrate and the isolation layer are an integrally formed part.

[0075] In some feasible implementations, the substrate 100 and the isolation layer 300 are made of the same material and are an integrally formed part.

[0076] Exemplarily, the substrate 100 and the isolation layer 300 are both sapphire layers. The sapphire layer has high transparency and excellent optical properties, and can effectively transmit the light emitted by the LED chip, thereby improving the optical efficiency and brightness of the LED chip. At the same time, the sapphire layer has good chemical stability, is not susceptible to chemical corrosion, and can protect the LED chip from the influence of the external environment. Moreover, the sapphire layer has high thermal conductivity, can effectively dissipate heat, helps to reduce the operating temperature of the LED chip, and improves the performance and stability of the LED chip.

[0077] The substrate 100 and the isolation layer 300 of the LED chip can be an integrally formed part. Fig.10As shown, this design can ensure the structural consistency and stability of the LED chip, reduce the electrical and optical losses at the interface between the substrate 100 and the isolation layer 300, and help improve the performance and reliability of the LED chip. At the same time, the same material of the substrate 100 and the isolation layer 300 is also conducive to simplifying the manufacturing process and reducing production costs. This one-piece design can effectively reduce the interface stress and lattice mismatch problems between the substrate 100 and the isolation layer 300, and improve the quality and long-term stability of the LED chip.

[0078] Fig.11 The schematic diagram schematically shows the structure of another embodiment of the LED chip provided by the embodiment of the present application after the epitaxial layer 200 is formed. Fig.12 The schematic diagram schematically shows the structure of another embodiment of the LED chip provided in the embodiment of the present application after a portion of the epitaxial layer 200 is removed. Fig.13 The schematic diagram of the structure of forming the second channel 250 in another embodiment of the LED chip provided in the embodiment of the present application is schematically shown. Figures 14 to 16 The schematic diagram of the structure of forming an electrical connection structure 400 in another embodiment of the LED chip provided in the embodiment of the present application is schematically shown.

[0079] In other embodiments, referring to Figures 11 to 16 As shown, when the substrate 100 and the isolation layer 300 of the LED chip are an integrally formed part, the preparation process of the LED chip is: an epitaxial layer 200 is formed on the integrally formed substrate 100 and the isolation layer 300. The epitaxial layer 200 includes an N-type semiconductor layer 210, an active layer 220, and a P-type semiconductor layer 230 stacked in sequence. Subsequently, the epitaxial layer 200 on the surface of the isolation layer 300 away from the substrate 100 is removed. Then, the P-type semiconductor layer 230 is etched to form a second channel 250, and the second channel 250 exposes a portion of the N-type semiconductor layer 210. Finally, an electrical connection structure 400 is prepared on the surface of the isolation layer 300 away from the substrate 100.

[0080] In some feasible implementations, the orthographic projection of the edge of the second channel 250 on the surface where the N-type semiconductor layer 210 is located is arranged around the outer periphery of the first channel 240 .

[0081] There is a distance between at least a portion of the edge of the second trench 250 and the isolation layer 300 located in the first trench 240 , so that there is a distance between at least a portion of the first unit cell 500 and the isolation layer 300 .

[0082] For example, refer to Figure 5 and Fig. 9 As shown, Figure 5The left side of the figure is the first unit cell 500. The right side of the first unit cell 500 is the second channel 250, and the right side of the second channel 250 is connected to the first channel 240. The isolation layer 300 is located in the first channel 240. The right side of the isolation layer 300 is the second unit cell 600. The structure in which the first channel 240 and the second channel 250 are connected effectively divides the first unit cell 500 and the second unit cell 600.

[0083] The isolation layer 300 forms an electrical isolation region in the first channel 240 to prevent the currents between the first unit cell 500 and the second unit cell 600 from interfering with each other, thereby improving the stability and reliability of the LED chip. At the same time, the isolation layer 300 forms a thermal isolation region in the first channel 240 to help reduce the operating temperature of the LED chip, reduce the conduction of heat inside the LED chip, and help improve the photoelectric conversion efficiency and life of the LED chip. In addition, the isolation layer 300 forms an optical isolation region in the first channel 240 to prevent the light between the first unit cell 500 and the second unit cell 600 from interfering with each other, thereby improving the photoelectric performance of the LED chip and the stability of the light output.

[0084] Exemplarily, at least part of the edge of the second trench 250 is spaced from the isolation layer 300 in the first trench 240 , so that at least part of the first unit cell 500 is spaced from the isolation layer 300 , so as to electrically connect the first unit cell 500 and the second unit cell 600 through the electrical connection structure 400 .

[0085] In some achievable embodiments, the surface of the isolation layer 300 facing away from the substrate 100 is not higher than the surface of the P-type semiconductor layer 230 facing away from the substrate 100 .

[0086] Exemplarily, the surface of the isolation layer 300 facing away from the substrate 100 is not lower than the surface of the N-type semiconductor layer 210 facing away from the substrate 100, and is not higher than the surface of the P-type semiconductor layer facing away from the substrate 100. The isolation layer 300 divides the first unit cell 500 and the second unit cell 600. Compared with the traditional LED chip, the isolation structure between adjacent units of the traditional LED chip is "concave", and the connecting layer 10 is also a "concave" structure. The present application fills the isolation layer 300 in the first trench 240, changes the structure between adjacent units of the traditional LED chip, improves the flatness of the LED chip, avoids the accumulation of water and abnormal elements in the first trench 240, and avoids the accumulation of water and abnormal elements in the "concave" electrical connection structure 400, thereby avoiding the corrosion problem that may occur between adjacent units of the LED chip, and also facilitates the molding of the electrical connection structure 400.

[0087] In some achievable embodiments, the surface of the isolation layer 300 facing away from the substrate 100 and the surface of the P-type semiconductor layer 230 facing away from the substrate 100 are flush.

[0088] For example, refer to Fig.16 As shown, the surface of the isolation layer 300 facing away from the substrate 100 is defined as the top surface of the isolation layer 300. The top surface of the isolation layer 300 is a horizontal surface. At this time, there is a step between the first end of the top surface of the isolation layer 300 and the N-type semiconductor layer 210 of the first unit cell 500, and the second end of the isolation layer 300 is flush with the P-type semiconductor layer 230 of the second unit cell 600. During the preparation process of the electrical connection structure 400, most of the electrical connection structure 400 is located on the top surface of the isolation layer 300 and extends horizontally to the P-type semiconductor layer 230 of the second unit cell 600. When the electrical connection structure 400 is formed on a horizontal plane, the electrical connection structure 400 can evenly cover the entire top surface of the isolation layer 300 to form a flat layered structure. In this case, the formation process of the electrical connection structure 400 is relatively simple, and the thickness of each part of the electrical connection structure 400 is uniform, which is conducive to improving the electrical connection stability of the first unit cell 500 and the second unit cell 600. In addition, a small portion of the electrical connection structure 400 is connected to the N-type semiconductor layer 210 of the first unit cell 500 through the step. The electrical connection structure 400 has only one corner at the step, which simplifies the electrical connection structure 400. At the same time, water and abnormal elements will not accumulate at the electrical connection structure 400, avoiding corrosion of water and abnormal elements at the electrical connection structure 400.

[0089] Fig.17 The structural diagram of the LED chip provided in the embodiment of the present application is schematically shown.

[0090] In some achievable embodiments, the surface of the isolation layer 300 facing away from the substrate 100 and the surface of the N-type semiconductor layer 210 facing away from the substrate 100 are flush.

[0091] For example, refer to Fig.17As shown, the surface of the isolation layer 300 facing away from the substrate 100 is defined as the top surface of the isolation layer. The top surface of the isolation layer is a horizontal surface. At this time, the first end of the isolation layer 300 is flush with the N-type semiconductor layer 210 of the first unit cell 500, and there is a step between the second end of the isolation layer 300 and the P-type semiconductor layer 230 of the second unit cell 600. During the preparation process of the electrical connection structure 400, most of the electrical connection structure 400 is located on the top surface of the isolation layer 300 and extends horizontally to the N-type semiconductor layer 210 of the first unit cell 500. When the electrical connection structure 400 is formed on the horizontal plane, the electrical connection structure 400 can evenly cover the entire top surface of the isolation layer 300 to form a flat layered structure. In this case, the formation process of the electrical connection structure 400 is relatively simple, and the thickness of each part of the electrical connection structure 400 is uniform, which is conducive to improving the electrical connection stability between the first unit cell 500 and the second unit cell 600. In addition, a small part of the electrical connection structure 400 is connected to the P-type semiconductor layer 230 of the second unit cell 600 through the step. The electrical connection structure 400 has only one corner at the step, which simplifies the electrical connection structure 400. At the same time, water and abnormal elements will not accumulate at the electrical connection structure 400, thus preventing water and abnormal elements from corroding the electrical connection structure 400.

[0092] In some achievable embodiments, the thickness of the isolation layer 300 gradually increases along the direction from the first unit cell 500 to the second unit cell 600 .

[0093] For example, refer to Fig. 9 As shown, the surface of the isolation layer 300 facing away from the substrate 100 is defined as the top surface of the isolation layer. The first end of the top surface of the isolation layer is connected to the N-type semiconductor layer 210 of the first unit cell 500. The second end of the top surface of the isolation layer is connected to the P-type semiconductor layer 230 of the second unit cell 600. The thickness of the isolation layer 300 gradually increases along the direction from the first unit cell 500 to the second unit cell 600. At this time, there is a smooth transition between the first end of the isolation layer 300 and the N-type semiconductor layer 210 of the first unit cell 500, and there is a smooth transition between the second end of the isolation layer 300 and the P-type semiconductor layer 230 of the second unit cell 600. The electrical connection structure 400 is formed on the top surface of the isolation layer 300, which is a flat layered structure, and the electrical connection structure 400 does not have a large-angle corner. In this case, the formation process of the electrical connection structure 400 is relatively simple, and the thickness of each part of the electrical connection structure 400 is uniform. At the same time, the isolation layer 300 with a flat layer structure is not conducive to the accumulation of water and abnormal elements, thereby preventing the water and abnormal elements from corroding the electrical connection structure 400 .

[0094] In some possible implementations, referring to Figures 7 to 9As shown, the electrical connection structure 400 includes a conductive layer 420 and an insulating layer 410. The insulating layer 410 is connected to at least a portion of the surface of the P-type semiconductor layer 230 facing away from the substrate 100. At least a portion of the conductive layer 420 is covered on the insulating layer 410. And the conductive layer 420 is connected to the surface of the P-type semiconductor layer 230 facing away from the substrate 100.

[0095] A first end of the conductive layer 420 is electrically connected to the first unit cell 500 , and a second end of the conductive layer 420 is electrically connected to the second unit cell 600 .

[0096] For example, due to the different conductivity of different layers of materials in the LED chip, when the current density of the P-type semiconductor layer 230 is too large, the current density vertically injected into the active layer 220 will be uneven, resulting in current congestion, which will cause discharge breakdown of the LED chip. To avoid the above phenomenon, the present application forms an insulating layer 410 on the P-type semiconductor layer 230 during the manufacturing process of the LED chip, and the insulating layer 410 is connected to at least a portion of the surface of the P-type semiconductor layer 230 facing away from the substrate 100. The insulating layer 410 has a blocking effect on the current.

[0097] After the insulating layer 410 is grown on the P-type semiconductor layer 230, a conductive layer 420 having a current diffusion function is then formed on the insulating layer 410 and the P-type semiconductor layer 230, and at least a portion of the conductive layer 420 covers the insulating layer 410. The conductive layer 420 is connected to the surface of the P-type semiconductor layer 230 that is away from the substrate 100. By providing the insulating layer 410 and the conductive layer 420, the first end of the conductive layer 420 is electrically connected to the first unit cell 500, and the second end of the conductive layer 420 is electrically connected to the second unit cell 600. There is a conductive layer 420 between the insulating layer 410 and the P-type semiconductor layer 230. After the current on the P-type semiconductor layer 230 is blocked by the insulating layer 410, it is injected into the P-type semiconductor layer 230 directly below the insulating layer 410 under the diffusion effect of the conductive layer 420, so that current is injected into the entire P-type semiconductor layer 230, thereby increasing the effective area of ​​the P-type semiconductor layer 230, and further improving the uniformity of current injection into the active layer 220, thereby improving the light extraction efficiency of the LED chip and the brightness of the chip.

[0098] Exemplarily, the LED chip further includes a first electrode 421 and a second electrode 422. While a conductive layer 420 having a current diffusion function is formed on the insulating layer 410 and the P-type semiconductor layer 230, the first electrode 421 is formed on the P-type semiconductor layer 230 of the first unit cell 500. The second electrode 422 is formed on the N-type semiconductor layer 210 of the second unit cell 600. The first electrode 421 and the second electrode 422 are used to connect to an external power source to provide power to the LED chip.

[0099] Exemplarily, the LED chip further includes a protection layer 430 .

[0100] Exemplarily, the insulating layer 410 may be a silicon dioxide layer.

[0101] For example, the conductive layer 420 may be a gold layer, the first electrode 421 may be a gold layer, and the second electrode 422 may be a gold layer.

[0102] Exemplarily, the protection layer 430 may be a silicon dioxide layer.

[0103] In some achievable embodiments, the first end of the conductive layer 420 is located at the gap between the first unit cell 500 and the isolation layer 300, and is electrically connected to the N-type semiconductor layer 210 of the first unit cell 500. The second end of the conductive layer 420 extends to the surface of the P-type semiconductor layer 230 of the second unit cell 600 away from the substrate 100, and is electrically connected to the P-type semiconductor layer 230 of the second unit cell 600.

[0104] Exemplarily, the first end of the conductive layer 420 is located at the gap between the first unit cell 500 and the isolation layer 300, and is electrically connected to the N-type semiconductor layer 210 of the first unit cell 500; and the second end of the conductive layer 420 extends to the P-type semiconductor layer 230 of the second unit cell 600, and is electrically connected to the P-type semiconductor layer 230 of the second unit cell 600. The conductive layer 420 electrically connects the first unit cell 500 and the second unit cell 600, realizing the series connection of adjacent units to prepare a high-voltage LED chip. Among them, the conductive layer 420 is used for functions such as signal transmission or power connection in the circuit.

[0105] In some achievable embodiments, the surface of the substrate 100 is uneven; and / or the surface of the isolation layer 300 facing away from the substrate 100 is uneven. Such an uneven surface of the substrate 100 can help increase the surface area, improve the light extraction efficiency, reduce the reflection and refraction loss of light, and thus improve the luminous efficiency and brightness of the LED chip. The uneven surface of the substrate 100 can also help evenly distribute the light source, reduce the hot spots and uneven light spots of the light source, and improve the optical performance and visual effect of the LED chip.

[0106] In some achievable embodiments, there are multiple first channels 240 and multiple second channels 250. The multiple first channels 240 and multiple second channels 250 are arranged at intervals along the thickness direction crossing the LED chip, and correspond one to one. The multiple first channels 240 and multiple second channels 250 divide the epitaxial layer 200 into multiple unit cells.

[0107] Exemplarily, the LED chip of the present application includes a plurality of first channels 240 and a plurality of second channels 250, and the plurality of first channels 240 and the plurality of second channels 250 divide the epitaxial layer 200 into a plurality of unit cells. Adjacent unit cells are connected by an electrical connection structure 400. In this way, the LED chip has a plurality of unit cells connected in series and electrically connected in sequence. By dividing the LED chip into a plurality of unit cells. These unit cells can work independently, thereby achieving higher power output and better thermal stability. Dividing into a plurality of unit cells also helps to reduce current density, reduce photon loss and improve photoelectric conversion efficiency. In addition, a plurality of unit cells connected in series in sequence no longer need to be tested, cut and packaged separately, saving testing, cutting and packaging costs. Moreover, the structure of a plurality of unit cells connected in series in sequence enables the LED chip to work at a relatively high voltage.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0109] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the above embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. An LED chip, characterized in that: include: substrate; An epitaxial layer, the epitaxial layer is arranged on the substrate; the epitaxial layer comprises an N-type semiconductor layer and a P-type semiconductor layer which are stacked; the N-type semiconductor layer is located between the substrate and the P-type semiconductor layer; A first channel is provided on the N-type semiconductor layer, and a second channel is provided on the P-type semiconductor layer. Along the thickness direction of the LED chip, the first channel exposes a portion of the substrate, and the second channel exposes a portion of the N-type semiconductor layer. The first channel and the second channel correspond to each other and are connected, and divide the epitaxial layer into a first unit cell and a second unit cell. an isolation layer, the isolation layer being located at least in the first channel, and a surface of the isolation layer away from the substrate being not lower than a surface of the N-type semiconductor layer away from the substrate; An electrical connection structure is disposed on a surface of the isolation layer facing away from the substrate, and the electrical connection structure electrically connects the first unit cell and the second unit cell.

2. The LED chip according to claim 1, characterized in that: A surface of the isolation layer facing away from the substrate is not higher than a surface of the P-type semiconductor layer facing away from the substrate.

3. The LED chip according to claim 1, characterized in that: A surface of the isolation layer facing away from the substrate and a surface of the P-type semiconductor layer facing away from the substrate are flush.

4. The LED chip according to claim 2, characterized in that: The orthographic projection of the edge of the second channel on the surface where the N-type semiconductor layer is located is arranged around the periphery of the first channel; There is a distance between at least a portion of the edge of the second channel and the isolation layer located in the first channel, so that there is a distance between at least a portion of the first unit cell and the isolation layer.

5. The LED chip according to claim 4, characterized in that: The thickness of the isolation layer gradually increases along a direction from the first unit cell to the second unit cell.

6. The LED chip according to any one of claims 1 to 5, characterized in that: The electrical connection structure comprises a conductive layer and an insulating layer, the insulating layer is connected to at least a portion of a surface of the P-type semiconductor layer facing away from the substrate, at least a portion of the conductive layer is covered on the insulating layer, and the conductive layer is connected to a surface of the P-type semiconductor layer facing away from the substrate; The first end of the conductive layer is electrically connected to the first unit cell, and the second end of the conductive layer is electrically connected to the second unit cell.

7. The LED chip according to claim 6, characterized in that: The first end of the conductive layer is located at a gap between the first unit cell and the isolation layer, and is electrically connected to the N-type semiconductor layer of the first unit cell; And / or, the second end of the conductive layer extends to the P-type semiconductor layer of the second unit cell away from the substrate surface, and is electrically connected to the P-type semiconductor layer of the second unit cell.

8. The LED chip according to claim 6, characterized in that: The substrate and the isolation layer are made of the same material and are an integrally formed part; And / or, the LED chip further comprises an active layer, wherein the active layer is located between the N-type semiconductor layer and the P-type semiconductor layer; and / or, the surface of the substrate is uneven; And / or, the surface of the isolation layer facing away from the substrate is uneven.

9. The LED chip according to claim 6, characterized in that: The number of the first channel and the number of the second channel are both multiple; the multiple first channels and the multiple second channels are arranged at intervals along the thickness direction intersecting the LED chip, and correspond one to one; The plurality of first channels and the plurality of second channels divide the epitaxial layer into a plurality of unit cells.

10. A display device, characterized in that: The invention comprises a circuit substrate and the LED chip according to any one of claims 1 to 9, wherein the LED chip is arranged on the circuit substrate.

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