Dynamic matching module, chip and system

Abstract

The utility model discloses a dynamic matching module, a chip and a system, communication abnormity is prevented by introducing a waveform optimization unit between two coding output ends of a coding module, and the waveform optimization unit is connected between the two coding output ends of the coding module by conducting an MOS (Metal Oxide Semiconductor) tube. The voltage difference between the two coding output ends can be rapidly pulled to 0V, the communication quality is further improved, and the effect is better.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, in particular to a dynamic matching module, a chip and a system. Background Art

[0002] In the prior art, when the encoding module is normally sending and receiving signals, the input signal sent by the MCU is received through the encoding input terminal, and the differential signal is output through the two encoding output terminals OUT (A) and OUT (B) after being encoded internally by the encoding module, and transmitted to the bus. Finally, the two signal acquisition terminals of the encoding module acquire the differential signal on the bus, determine the difference range of the differential signal on the bus, and decode it to 0 or 1 (i.e., determine the OUTA-OUTB waveform range) to obtain the decoded signal, thereby achieving the effect of signal restoration and successful communication between devices. However, in actual applications, due to factors such as long communication distance, many nodes, and complex node structure, the waveform of the OUT (A)-OUT (B) signal when it changes from "low level to middle level" or "high level to middle level" is not "steep" enough or even oscillates, which will cause the "1" pulse width of the decoded signal DATA OUT to be insufficient or mis-decoding, resulting in abnormal communication. Utility Model Content

[0003] The utility model aims to overcome the problem of miscoding caused by abnormal communication in existing communication lines, and provides a dynamic matching module, chip and system.

[0004] In order to achieve the above object, the utility model provides a dynamic matching module for use with an external encoding module, wherein the encoding module is used to receive an input signal through an encoding input terminal, encode the input signal and output a differential signal through two encoding output terminals, and the two encoding output terminals of the encoding module are respectively connected to a first bus and a second bus;

[0005] It includes: a first delay unit, a MOS tube and a waveform optimization unit;

[0006] The first delay unit is used for, when the input signal switches from the first level to the second level, starting delay based on the second level and turning on the power supply to the MOS tube so as to turn on the MOS tube, and ending the delay and stopping the power supply to the MOS tube when the first predetermined time interval is reached so as to turn off the MOS tube;

[0007] The MOS tube is used to connect the waveform optimization unit to the two encoding output terminals after being turned on, and disconnect the connection between the waveform optimization unit and the two encoding output terminals after being turned off;

[0008] The waveform optimization unit is used to quickly switch the voltage difference between the two encoding output ends from a preset voltage difference to 0V.

[0009] As an implementation method, the MOS tube includes a first MOS tube Q4 and a second MOS tube Q5, the waveform optimization unit includes a first waveform optimization unit and a second waveform optimization unit, the source S of the first MOS tube Q4 is connected to the first coding output end through the first waveform optimization unit, the drain D of the second MOS tube Q5 is connected to the first coding output end, the gate G of the first MOS tube Q4 and the gate G of the second MOS tube Q5 are connected to the first delay unit, the drain D of the first MOS tube Q4 is connected to the second coding output end, and the source S of the second MOS tube Q5 is connected to the second coding output end through the second waveform optimization unit.

[0010] As an implementation method, it also includes a first charging unit and a first discharging unit;

[0011] The first charging unit is used to charge the parasitic capacitor Cgs of the MOS tube to form a charging loop when the input signal is at the second level and the power supply to the MOS tube is turned on, so as to quickly turn on the MOS tube;

[0012] The first discharge unit is used to form a discharge loop for discharging the parasitic capacitance Cgs of the MOS tube when the input signal is at the second level and the delay ends and the power supply to the MOS tube stops when the first predetermined time interval is reached, so as to quickly shut down the MOS tube.

[0013] As an implementable embodiment, the dynamic matching module further includes a second discharge unit;

[0014] The second discharge unit is used to start delaying based on the second level when the input signal switches from the first level to the second level, and discharge the MOS tube when a second predetermined time interval is reached, so as to quickly turn off the MOS tube, wherein the second predetermined time interval is greater than the first predetermined time interval.

[0015] As an implementable embodiment, the second discharge unit includes a second delay unit, a first discharge sub-unit and a second discharge sub-unit;

[0016] The second delay unit is used for starting delay based on the second level when the input signal switches from the first level to the second level, and ending the delay when the second predetermined time interval is reached and turning on the first discharge sub-unit; wherein the second predetermined time interval is greater than the first predetermined time interval;

[0017] The first discharge sub-unit is used to discharge the parasitic capacitance Cgs of the MOS tube after being turned on, so as to quickly turn off the MOS tube;

[0018] The second discharge sub-unit is used for discharging the second delay unit so as to disconnect the first discharge sub-unit when the input signal is subsequently switched from the second level to the first level.

[0019] As an implementation method, the first discharge sub-unit includes a third triode Q3 and a stabilization unit; the collector of the third triode Q3 is connected to the base of the third triode Q3, the collector of the third triode Q3 is connected to the gate of the MOS tube, the collector of the third triode Q3 is also connected to the input signal terminal V1 through the stabilization unit, and the input signal terminal V1 is connected to the base of the third triode Q3;

[0020] The third transistor Q3 is used to discharge the MOS tube;

[0021] The stabilization unit is used to isolate the third transistor Q3 and the input signal terminal V1 during the process of the third transistor Q3 discharging the MOS tube, so as to prevent the first discharge sub-unit from interfering with the input signal inputted by the input signal terminal V1.

[0022] As an implementation method, the second delay unit includes a second capacitor C2 and a sixth resistor R6, the second discharge sub-unit includes a first diode D1, the stabilization unit includes a first transistor Q1 and a second transistor Q2, one end of the second capacitor C2 is connected to the base of the third transistor Q3 through the seventh resistor R7, and is connected to the input signal terminal V1 through the sixth resistor R6, the input signal terminal V1 is used to receive an input signal, the other end of the second capacitor C2 is connected to the ground terminal, the collector of the third transistor Q3 is connected to the gate of the MOS tube and the collector of the first transistor Q1, the emitter of the third transistor Q3 is connected to the ground terminal, and the first transistor The emitter of Q1 is connected to the input signal terminal V1, the base of the first transistor Q1 is connected to the input signal terminal V1 through the second resistor R2, the base of the first transistor Q1 is connected to the collector of the second transistor Q2 through the fourth resistor R4, the base of the second transistor Q2 is connected to the first delay unit, the base of the second transistor Q2 is connected to the emitter of the second transistor Q2 through the third resistor R3, the emitter of the second transistor Q2 is connected to the ground terminal, the cathode of the first diode D1 is connected to the input signal terminal V1, and the anode of the first diode is connected to one end of the second capacitor C2 and the seventh resistor R7, and is connected to the ground terminal through the fifth resistor R5.

[0023] As an implementation method, it also includes: an anti-backflow unit located between the MOS tube and the waveform optimization unit, which is used to prevent current backflow from occurring in the dynamic matching module when the two encoding output terminals stop outputting signals.

[0024] As an implementation method, the anti-backflow unit is an anti-backflow diode, the positive electrode of the anti-backflow diode is connected to the source of the MOS tube, and the negative electrode of the anti-backflow diode is connected to one end of the waveform optimization unit. Accordingly, the utility model also provides a chip, including the above-mentioned dynamic matching module.

[0025] Correspondingly, the utility model also provides a system, including the aforementioned chip.

[0026] Beneficial effects of the utility model:

[0027] The utility model discloses a dynamic matching module, chip and system. By introducing a waveform optimization unit between the two encoding output terminals of the encoding module, communication abnormalities are prevented. By turning on the MOS tube to connect the waveform optimization unit between the two encoding output terminals of the encoding module, the voltage difference between the two encoding output terminals can be pulled to 0V more quickly, further improving the communication quality and achieving better results. The MOS tube can be quickly turned on and off by the first charging unit and the first discharging unit; the discharge abnormality can be prevented by the second discharging unit. The anti-backflow unit can prevent the signal on the bus from backflowing into the dynamic matching module when the two encoding output terminals of the encoding module do not output differential signals, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of an encoding module provided for some embodiments of the present utility model;

[0029] Figure 2 A schematic diagram of a dynamic matching module provided in some embodiments of the utility model;

[0030] Figure 3 A schematic diagram of changes in the signal waveform diagrams provided in some embodiments of the present utility model under an ideal state;

[0031] Figure 4 A schematic diagram of the change of the signal waveform diagram provided in some embodiments of the utility model when OUT (A) - OUT (B) produces an oscillation state in actual application;

[0032] Figure 5 A schematic diagram of the change of OUT (A)-OUT (B) of the signal waveform diagram provided in some embodiments of the present invention after the waveform optimization unit is introduced;

[0033] Figure 6 A schematic diagram of an active inductor module provided in some embodiments of the utility model;

[0034] Figure 7 A schematic diagram of a chip of an integrated active inductor module provided in some embodiments of the utility model;

[0035] Figure 8 A schematic diagram of a chip integrating a dynamic matching module and an active inductor module provided in some embodiments of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0037] The technical terms or scientific terms used in this application should be understood by those skilled in the art in general. The terms "first", "second", "third", "fourth" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Therefore, the features defined as "first", "second", "third" and "fourth" may explicitly or implicitly include one or more of the features. "One end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which include not only the endpoints, and the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. Unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0038] After research, see Figure 1 The coding module 40 is a schematic diagram of a communication chip, see Figure 3The following is a signal waveform diagram of each input and output terminal of the coding module 40 under ideal conditions when normally transmitting and receiving signals. When RESET is set to low, the coding module 40 can normally transmit and receive signals. DATA IN (TXD) is a schematic diagram of the level change corresponding to the input signal TXD, which is directly given to the coding module 40 by the MCU. After being encoded as a differential signal inside the coding module 40, the differential signal is output from the two encoding output terminals OUT (A) and OUT (B) and sent to the first bus A and the second bus B. Finally, the coding module 40 obtains the differential signal through the two acquisition terminals IN1 and IN2, judges the difference range of the differential signal on the transmission bus, decodes 0 or 1 (that is, judges the waveform range shown as OUTA-OUTB in the figure) to obtain the decoded signal RXD, and outputs the decoded signal RXD through the output terminal DATA OUT, achieving the effect of signal restoration and successful communication between devices. However, in actual applications, due to many factors such as long communication distance, many nodes, and complex node structure, the parasitic parameters on the transmission bus have a greater adverse effect on communication, see Figure 4 This is the "communication chip signal timing diagram under complex working conditions". The waveform of the OUT (A)-OUT (B) signal on the transmission line is not "steep" enough and even oscillates when it changes from "low level to middle level" or "high level to middle level" ( Figure 4 OUT(A)-OUT(B) in the decoded signal DATA OUT), which will cause the "1" pulse width of the decoded signal DATA OUT to be insufficient or cause miscoding ( Figure 4 The DATA OUT in the transmission line causes abnormal communication; while the two stages of the OUT (A) and OUT (B) signals on the transmission line from "intermediate level to high level" or "intermediate level to low level" are realized by the internal transistor of the encoding module 40 quickly pulling up to the preset voltage or quickly pulling down to 0V, which is basically not affected by the parasitic parameters on the transmission line.

[0039] Therefore, in order to further improve the communication quality, the problem of the waveform of the OUT (A) - OUT (B) signal on the transmission line turning from "low level to middle level" or "high level to middle level" is not "steep" enough or even oscillates when it changes from "low level to middle level", which will cause the "1" pulse width of the decoding signal DATA OUT to be insufficient or misinterpretation to occur, leading to communication abnormalities.

[0040] See also Figure 2Some embodiments of the present invention provide a dynamic matching module 30 for use with an external encoding module 40, wherein the encoding module 40 is used to receive an input signal through an encoding input terminal DATA IN, encode the input signal and output a differential signal through two encoding output terminals, namely OUT (A) and OUT (B), wherein the two encoding output terminals, namely OUT (A) and OUT (B), of the encoding module are respectively connected to a first bus and a second bus; the dynamic matching module 30 comprises: a first delay unit, a MOS tube and a waveform optimization unit; the first delay unit is used to start delaying and turning on the power supply to the MOS tube based on the second level when the input signal switches from a first level to a second level, so as to turn on the MOS tube, and to end the delay and stop the power supply to the MOS tube when a first predetermined time interval is reached, so as to turn off the MOS tube; the MOS tube is used to connect the waveform optimization unit between the two encoding output terminals after being turned on, and to disconnect the connection between the waveform optimization unit and the two encoding output terminals after being turned off; the waveform optimization unit is used to quickly switch the voltage difference between the two encoding output terminals from a preset voltage difference to 0V. Specifically, the gate of the MOS tube is connected to the first delay unit, the drain of the MOS tube is connected to one encoding output terminal of the encoding module 40, and the source of the MOS tube is connected to another encoding output terminal of the encoding module 40 through the waveform optimization unit. Through the circuit design based on MOS tubes, a corresponding number of MOS tubes can be selected for combination to achieve the expected effect.

[0041] In some embodiments of the present invention, the dynamic matching module 30 is used to connect a waveform optimization unit between the two encoding output terminals OUT (A) and OUT (B) of the encoding module 40 when the input signal switches from the first level to the second level. Figure 5 By introducing a high level brought by the waveform optimization unit between the two encoding output terminals within the first predetermined time interval t1 after the input signal switches from the first level to the second level, the voltage difference between the two encoding output terminals, OUT (A) and OUT (B), is quickly switched from a preset voltage, such as 5V, to 0V, thereby preventing miscoding caused by insufficiently steep waveforms. Figure 5It can be seen that by introducing the waveform optimization unit, the encoding module 40 outputs the decoding signal RXD through the output terminal DATA OUT to achieve the effect of signal restoration and improve the communication quality. In other words, the purpose of the utility model to set the dynamic matching module is to quickly pull the two encoding output terminals to an equal voltage when the input signal TXD switches from the first level to the second level. Theoretically, it is best if there is no voltage drop. However, the conduction voltage drop of the transistor is much larger than that of the MOS, which will cause the bus signal OUTA-OUTB to still have a voltage difference when it should be 0V, thereby affecting the judgment of the two signal acquisition terminals IN1 and IN2 of the communication chip and causing miscoding. Therefore, in the utility model, the switching unit is a MOS tube, the conduction voltage drop of the MOS tube is much smaller than that of the transistor, and the current capacity of the MOS is also greater than that of the transistor, which can more quickly pull the voltage difference between the two encoding output terminals OUT (A) and OUT (B) to 0V, further improving the communication quality and achieving better results.

[0042] Specifically, when the input signal TXD switches from the first level to the second level, the first delay unit starts the delay and turns on the MOS tube, and the waveform optimization unit is connected to the two encoding output terminals, namely OUT (A) and OUT (B) through the MOS tube; then the first delay unit delays the first predetermined time interval t1 to achieve the rapid switching of OUT (A)-OUT (B) from the high / low level to the intermediate level, and then turns off the MOS tube, so as to disconnect the connection between the waveform optimization unit and the two encoding output terminals. In addition, since in some DC power line carrier communication schemes, only one device is sending a signal at the same time, there will be no situation where multiple dynamic matching modules are incorporated into the bus at the same time to reduce the impedance between the buses.

[0043] In some embodiments, the first level is one of a high level and a low level, and the second level is the other of the high level and the low level. In the following text, the first level is understood as a low level and the second level is a high level. In some embodiments, the preset voltage difference between the two encoding output terminals, OUT (A) and OUT (B), is a high level voltage value of OUT (A) - OUT (B), and the high level voltage value can be set according to actual needs, for example, it can be set to 5V.

[0044] In some embodiments, the first delay unit includes a delay capacitor, specifically, the first delay unit includes a first capacitor C1 and a first resistor R1, and the delay time of the first delay unit is determined according to the capacity of the first capacitor C1 and the resistance value of the first resistor R1, that is, the first predetermined time interval t1 can be set by setting the capacity of the first capacitor C1 and the resistance value of the first resistor R1. When charging the first capacitor C1 based on the second level, the right end of the first capacitor C1 is a high level, thereby turning on the second transistor Q2 and the first transistor Q1 in turn, achieving the expected goal. When the first predetermined time interval t1 passes during the second level, the voltage on the right side of the first capacitor C1 is finally reduced to a low level, and the second transistor Q2 and the first transistor Q1 are turned off, achieving the expected effect. Figure 5 The t1 waveform in the figure shows the time point and duration of the dynamic matching module. When the TXD signal changes from 0 to 1, the dynamic matching module takes effect and lasts for t1 time. Figure 1 Actually, it is equivalent to connecting the waveform optimization unit between the buses during this time period.

[0045] In some embodiments, the MOS transistor includes a first MOS transistor Q4 and a second MOS transistor Q5, and the waveform optimization unit may be a matching resistor. The waveform optimization unit includes a first waveform optimization unit and a second waveform optimization unit. The first waveform optimization unit and the second waveform optimization unit may be a first matching resistor R10 and a second matching resistor R11, respectively. Matching resistors may be connected to the two encoding output terminals, so that the voltage difference between the two encoding output terminals OUT (A) and OUT (B) may be pulled to 0V more quickly to improve the signal quality. When the OUT (A) and OUT (B) signals are quickly pulled to the intermediate level through the matching resistor, there is no voltage difference in the transmission line, and no current will flow through the matching resistor to generate additional power consumption. In the solution based on the HBS communication protocol, only one device sends a signal at the same time, and there will be no situation where multiple matching resistors are incorporated into the bus to reduce the impedance between the buses. Specifically, when the MOS transistor includes a first MOS transistor Q4 and a second MOS transistor Q5, the waveform optimization unit includes a first waveform optimization unit and a second waveform optimization unit, the source S of the first MOS transistor Q4 is connected to the first coding output terminal through the first waveform optimization unit, the drain D of the second MOS transistor Q5 is connected to the first coding output terminal, the gate G of the first MOS transistor Q4 and the gate G of the second MOS transistor Q5 are connected to the first delay unit, the drain D of the first MOS transistor Q4 is connected to the second coding output terminal, and the source S of the second MOS transistor Q5 is connected to the second coding output terminal through the second waveform optimization unit. In some embodiments, the first coding output terminal may be the coding output terminal OUT (A) or the coding output terminal OUT (B), and the second coding output terminal may be the corresponding coding output terminal OUT (B) or the coding output terminal OUT (A).Exemplarily, the first end of the first delay unit is connected to the signal input terminal V1, the second end of the first delay unit is connected to the gate G of the first MOS tube Q4 and the source S of the first MOS tube Q4, the source S of the first MOS tube Q4 is connected to the first end of the first waveform optimization element R10, the second end of the first waveform optimization unit R10 is connected to the first waveform optimization signal output terminal V3, the first waveform optimization signal output terminal V3 is connected to the encoding output terminal OUT (A) of the encoding module, the drain D of the first MOS tube Q4 is connected to the second waveform optimization signal output terminal V2, and the second waveform optimization signal output terminal V2 is connected to the second waveform optimization signal output terminal V3. The first delay unit is connected to the encoding output terminal OUT (B), the second end of the first delay unit is also connected to the gate G of the second MOS tube Q5 and the source S of the second MOS tube Q5, the drain D of the second MOS tube Q5 is connected to the first waveform optimization signal output terminal V3, the first waveform optimization signal output terminal V3 is connected to the encoding output terminal OUT (A) of the encoding module, the source S of the second MOS tube Q5 is connected to the first end of the second waveform optimization unit R11, the second end of the second waveform optimization unit R11 is connected to the second waveform optimization signal output terminal V2, and the second waveform optimization signal output terminal V2 is connected to the encoding output terminal OUT (B).

[0046] In some embodiments, due to the presence of parasitic capacitance between the gate and source of the MOS tube, the dynamic matching module further includes a first charging unit and a first discharging unit; the first charging unit is used to form a charging loop for charging the parasitic capacitance Cgs of the MOS tube when the input signal is at the second level and the power supply to the MOS tube is turned on, so as to quickly turn on the MOS tube; the first discharging unit is used to form a discharging loop for discharging the parasitic capacitance Cgs of the MOS tube when the input signal is at the second level and the delay ends and the power supply to the MOS tube is stopped when the first predetermined time interval t1 is reached, so as to quickly turn off the MOS tube.

[0047] In some embodiments, the first charging unit includes a first charging subunit and a second charging subunit; the first charging subunit is used for, when the input signal is at the second level and the power supply to the first MOS tube Q4 is turned on, to form a first charging loop for charging the parasitic capacitance Cgs of the first MOS tube Q4, so as to quickly turn on the first MOS tube Q4; the second charging subunit is used for, when the input signal is at the second level and the power supply to the second MOS tube Q5 is turned on, to form a second charging loop for charging the parasitic capacitance Cgs of the second MOS tube Q5, so as to quickly turn on the second MOS tube Q5. Specifically, the first charging subunit includes a second diode D2, the positive electrode of the second diode D2 is connected to the source of the first MOS tube Q4 and the gate of the first MOS tube Q4, and the negative electrode of the second diode D2 is connected to the ground terminal; the positive electrode of the second diode D2 is connected to the gate of the first MOS tube Q4, specifically, the positive electrode of the second diode D2 is connected to the gate of the first MOS tube Q4 through the eighth resistor R8. The second charging subunit includes a third diode D3, the anode of the third diode D3 is connected to the source of the second MOS transistor Q5 and the gate of the second MOS transistor Q5, and the cathode of the third diode D3 is connected to the ground terminal. The anode of the third diode D3 is connected to the gate of the second MOS transistor Q5, specifically, the anode of the third diode D3 is connected to the gate of the second MOS transistor Q5 through the ninth resistor R9.

[0048] In some embodiments, the first discharge unit includes a third discharge subunit and a fourth discharge subunit; the third discharge subunit is used to form a first discharge loop for discharging the parasitic capacitance Cgs of the first MOS tube Q4 when the input signal is a second level and the delay ends and the power supply to the first MOS tube Q4 stops when the input signal reaches a first predetermined time interval t1, so as to realize rapid shutdown of the first MOS tube Q4; the fourth discharge subunit is used to form a second discharge loop for discharging the parasitic capacitance Cgs of the second MOS tube Q5 when the input signal is a second level and the delay ends and the power supply to the second MOS tube Q5 stops when the input signal reaches a first predetermined time interval t1, so as to realize rapid shutdown of the second MOS tube Q5. Specifically, the third discharge subunit includes an eighth resistor R8, one end of the eighth resistor R8 is connected to the source of the first MOS tube Q4, and the other end of the eighth resistor R8 is connected to the gate of the first MOS tube Q4. The fourth discharge subunit includes a ninth resistor R9, one end of the ninth resistor R9 is connected to the source of the second MOS tube Q5, and the other end of the ninth resistor R9 is connected to the gate of the second MOS tube Q5.

[0049] In some embodiments, generally speaking, since the conduction time of the first MOS tube Q4 and the second MOS tube Q5 is much less than 104us (for example, in the communication scheme of the HBS protocol with a DC 9600bps communication rate, the minimum high-level pulse width of the signal is 104uS), there is no problem that the first MOS tube Q4 and the second MOS tube Q5 are turned off slowly, because Q4 and Q5 start to turn off after being turned on for tens of uS, that is, they will be turned off during the period when the input signal TXD is at the second level. Under normal circumstances, they will not be mis-converted when the indoor unit does not send a signal or receives a signal. However, in order to prevent abnormal situations, the present embodiment further provides a second discharge unit, which is used to start delaying based on the second level when the input signal switches from the first level to the second level, and discharge the parasitic capacitance Cgs of the MOS tube when the second predetermined time interval t2 is reached, so as to quickly turn off the MOS tube; wherein the second predetermined time interval t2 is greater than the first predetermined time interval t1.

[0050] In some embodiments, the second discharge unit includes a second delay unit, a first discharge sub-unit, and a second discharge sub-unit; the second delay unit is used to start delaying based on the second level when the input signal switches from the first level to the second level, and the delay ends and the first discharge sub-unit is turned on when the second predetermined time interval is reached; wherein the second predetermined time interval t2 is greater than the first predetermined time interval t1; the first discharge sub-unit is used to discharge the parasitic capacitance Cgs of the MOS tube after being turned on, so as to quickly turn off the MOS tube; the second discharge sub-unit is used to discharge the second delay unit when the input signal switches from the second level to the first level according to the normal switching cycle, so as to turn off the first discharge sub-unit. In one embodiment, the second delay unit can be discharged faster by the second discharge sub-unit.

[0051] In some embodiments, the first discharge sub-unit includes a third triode Q3 and a stabilization unit, the collector of the third triode is connected to the base of the third triode Q3, the collector of the third triode Q3 is connected to the gate of the MOS tube, the collector of the third triode Q3 is also connected to the input signal terminal through the stabilization unit, and the input signal terminal is connected to the base of the third triode Q3. The third triode Q3 is used to discharge the MOS tube; the stabilization unit is used to isolate the third triode Q3 and the input signal terminal V1 during the process of the third triode Q3 discharging the MOS tube, so as to prevent the discharge sub-unit from interfering with the input signal inputted by the input signal terminal V1. Specifically, when the stabilization unit does not exist, the collector of the third transistor Q3 is connected to the gate of the MOS tube, the emitter of the third transistor Q3 is connected to the ground terminal, the base of the third transistor Q3 is connected to the collector of the third transistor, the base of the third transistor Q3 is also connected to the input signal terminal and one end of the second delay unit, and the other end of the second delay unit is connected to the ground terminal. The input signal TXD of the input signal terminal will be pulled low when the third transistor Q3 is turned on. When the stabilization unit is set, the connection between the collector of the third transistor and the input signal terminal V1 is disconnected by the stabilization unit, thereby avoiding interference caused by the input signal TXD of the input signal terminal.

[0052] Specifically: when the input signal switches from the first level to the second level, the second delay unit starts the delay, and the delay ends when the second predetermined time interval t2 is delayed and the first discharge sub-unit is turned on, the first discharge sub-unit discharges the MOS tube, so that the MOS tube is quickly turned off, and the stabilization unit is used to prevent the first discharge sub-unit from pulling down the input signal TXD in the process of discharging the MOS tube, thereby affecting the normal switching of the input signal TXD; when the input signal switches from the second level to the first level, the second discharge unit discharges the second delay unit and disconnects the first discharge sub-unit; wherein, in order to ensure that no logic abnormality occurs, the first predetermined time interval t1 is less than the second predetermined time interval t2, and after introducing a high level of the first predetermined time interval t1 to the two encoding output ends of the encoding module, the MOS tube is discharged by the first discharge sub-unit, so that the MOS tube is quickly disconnected to prevent abnormalities.

[0053] In some embodiments, the second delay unit includes a delay capacitor. Specifically, the second delay unit includes a second capacitor C2 and a sixth resistor R6, and the delay time of the second delay unit is determined according to the capacity of the delay capacitor and the resistance value of the sixth resistor R6, that is, the second predetermined time interval t2 can be set by setting the capacity of the second capacitor C2 and the resistance value of the second resistor R6. Exemplarily, the first discharge sub-unit includes a third transistor Q3, the second discharge sub-unit includes a first diode D1, the stabilization unit includes a first transistor Q1 and a second transistor Q2, one end of the second capacitor C2 is connected to the base of the third transistor Q3 through a seventh resistor R7, and is connected to the input signal terminal V1 through a sixth resistor R6, and the input signal terminal V1 is used to receive an input signal, the other end of the second capacitor C2 is connected to the ground terminal, the collector of the third transistor Q3 is connected to the gate of the MOS tube and the collector of the first transistor Q1, the emitter of the third transistor Q3 is connected to the ground terminal, the emitter of the first transistor Q1 is connected to the input signal terminal V1, and the first The base of a transistor Q1 is connected to the input signal terminal V1 through a second resistor R2, the base of the first transistor Q1 is connected to the collector of the second transistor Q2 through a fourth resistor R4, the base of the second transistor Q2 is connected to the first delay unit, specifically connected to the other end of the first capacitor C1 through the first resistor R1, the base of the second transistor Q2 is connected to the emitter of the second transistor Q2 through a third resistor R3, the emitter of the second transistor Q2 is connected to the ground terminal, the cathode of the first diode D1 is connected to the input signal terminal V1, the anode of the first diode is connected to one end of the second capacitor C2 and the seventh resistor R7, and is connected to the ground terminal through a fifth resistor R5.

[0054] Specifically, the operation process of the entire circuit is as follows: when the input signal TXD is at the second level, the first capacitor C1 and the second capacitor C2 are charged, the first capacitor turns on the second transistor Q2, the second transistor Q2 turns on the first transistor Q1, the first transistor Q1 turns on the MOS tube, and after the MOS tube is turned on, the waveform optimization unit is introduced between the two encoding output terminals of the encoding module, namely, OUT (A) and OUT (B). At a first predetermined time interval t1 after the first capacitor C1 starts to charge, the first capacitor C1 is fully charged, that is, the delay ends, and the second transistor Q2 and the first transistor Q1 are turned off, thereby stopping the power supply to the MOS tube; at a second predetermined time interval t2 after the second capacitor C2 starts to charge, the second capacitor C2 is fully charged, that is, the delay ends. The second capacitor C2 turns on the third triode Q3, and the third triode Q3 quickly discharges the MOS tube, thereby quickly turning off the MOS tube. In this process, the base of the third triode Q3 is connected to the input signal terminal V1 through the seventh resistor R7 and the sixth resistor R6, and the collector of the third triode Q3 is connected to the base of the third triode Q3 through the sixth resistor R6 and the seventh resistor R7, while the input signal TXD input by the signal input terminal V1 is still at a high level. Therefore, in order to prevent the third triode Q3 from pulling down the input signal TXD input by the signal input terminal V1, this embodiment blocks the circuit between the third triode Q3 and the signal input terminal V1 by introducing the first triode Q1 and the second triode Q2, thereby avoiding abnormal switching of the input signal TXD. After that, when the input signal TXD switches to a low level according to the normal switching cycle, the first diode D1 starts discharging the second capacitor C2 and turns off the third transistor Q3, and the voltage at the left end of the first capacitor C1 is pulled to 0V, and the right end becomes negative. It should be noted that the first diode D1 is additionally provided in this embodiment to accelerate the discharge of the second capacitor C2. The second discharge unit enables the entire circuit to operate normally when the input signal TXD is then switched to a high level according to the normal switching cycle, thereby ensuring that the dynamic matching module can normally cooperate with the transceiver signal of the encoding module 40 during the entire waveform period of the input signal TXD.

[0055] In some embodiments, the dynamic matching module further includes an anti-backflow unit located between the MOS tube and the waveform optimization unit, which is used to prevent the signal on the bus from backflowing into the dynamic matching module to cause power consumption when the two encoding output terminals stop outputting signals. Figure 4 If there is no backflow prevention unit, when the input signal of the second waveform optimization signal output terminal V2 is high level, the high level signal will pass through the second waveform optimization unit and the second MOS tube Q5 to reach the first waveform optimization signal output terminal V3, thereby generating power consumption. In this embodiment, the circuit is disconnected by the backflow prevention unit, thereby reducing power consumption.

[0056] In some embodiments, the anti-backflow unit is an anti-backflow diode, the positive electrode of the anti-backflow diode is connected to the source electrode of the MOS tube, and the negative electrode of the anti-backflow diode is connected to one end of the waveform optimization unit. Specifically, the anti-backflow unit includes a first anti-backflow unit corresponding to the first MOS tube Q4 and a second anti-backflow unit corresponding to the second MOS tube Q5, the first anti-backflow unit is a fourth diode D4, and the second anti-backflow unit is a fifth diode D5. Specifically, the drain electrode D of the first MOS tube Q4 is connected to the second waveform optimization signal output terminal V2, and the source electrode S of the first MOS tube Q4 is connected to the first waveform optimization signal output terminal V3 through the fourth diode D4, the first waveform optimization unit R10 and the first waveform optimization signal output terminal V3 in sequence. Specifically, the source electrode S of the first MOS tube Q4 is connected to the positive electrode of the fourth diode D4, the negative electrode of the fourth diode D4 is connected to one end of the first waveform optimization unit R10, and the other end of the first waveform optimization unit R10 is connected to the first waveform optimization signal output terminal V3. The drain D of the second MOS tube is connected to the first waveform optimization signal output terminal V3, and the source S of the second MOS tube is connected to the second waveform optimization signal output terminal V2 through the fifth diode D5, the second waveform optimization unit R11 and the second waveform optimization signal output terminal V2 in sequence. Specifically, the source S of the second MOS tube Q5 is connected to the anode of the fifth diode D5, the cathode of the fifth diode D5 is connected to one end of the second waveform optimization unit R11, and the other end of the second waveform optimization unit R11 is connected to the second waveform optimization signal output terminal V2.

[0057] In some embodiments, see Figure 6 The utility model also provides an active inductor module 10, comprising: a rectifier bridge 200 and an active inductor unit 100; the active inductor unit 100 is connected to an external first bus and a second bus through the rectifier bridge 200; the first input end of the rectifier bridge 200 and the second input end of the rectifier bridge 200 can be connected to a first signal input end DA and a second signal input end DB respectively, the first signal input end DA and the second signal input end DB are respectively used to connect the first bus and the second bus, the first output end of the rectifier bridge 200 and the second output end of the rectifier bridge 200 are respectively connected to the first input end of the active inductor unit 100 and the second input end of the active inductor unit 100, the first output end of the active inductor unit 100 is connected to a DC power signal output end VDD, and the DC power signal output end VDD is used to output a DC power signal; the second output end of the active inductor unit 100 is connected to a ground end GND. The active inductor unit 100 is used to isolate the AC differential signal input from the first bus and the second bus, and output a DC power signal; the rectifier bridge 200 is used to achieve a non-polarity connection between the active inductor unit 100 and the first bus and the second bus.

[0058] In some embodiments, see Figure 7 When the rectifier bridge 200 and the active inductor unit 100 are integrated into a chip and then packaged on a PCB board, the first signal input terminal DA, the second signal input terminal DB, the DC power signal output terminal VDD and the ground terminal GND can be four pins of the chip. In some embodiments, when the active inductor module 10 including a rectifier bridge and an active inductor unit is integrated into a chip, and then the chip is packaged on a PCB board, a DC power signal on the transmission bus can be obtained through the rectifier bridge and the active inductor unit inside the chip, and the DC power is output from the DC power signal output terminal VDD. The output voltage value at the DC power signal output terminal VDD = the DC power supply voltage on the transmission bus - the voltage drop lost on the transmission bus - the voltage drop inside the chip. Generally, a variety of DC voltages (such as 5.0V, 3.3V, 1.5V, etc.) may be required on a PCB board to make the chip or circuit work normally. Therefore, power can be taken from the transmission bus through the DC power signal output terminal VDD. Other suitable power modules 20 are externally connected to the DC power signal output terminal VDD to output other required DC voltage values. The power module 20 can be a DC-DC power chip.

[0059] In some embodiments, the active inductor unit 100 includes a first active inductor and a second active inductor; one end of the first active inductor 100 is connected to the first signal input terminal DA through the rectifier bridge 200, and the other end of the first active inductor 100 is connected to the DC power signal output terminal VDD; one end of the second active inductor is connected to the second signal input terminal DB through the rectifier bridge 200, and the other end of the second active inductor 100 is connected to the ground terminal GND.

[0060] The active inductor module 10 provided by the utility model generates a certain equivalent inductive reactance by using an active inductor unit, and can be increased with the increase of the communication rate, and has the same effect as using a differential mode inductor, preventing the communication signal on the transmission line from being absorbed by the capacitor of the power supply part and obtaining the direct current on the transmission line, and achieving the effect of taking power from the transmission bus and outputting a stable voltage to the slave side circuit. By integrating the rectifier bridge and the active inductor unit together, the active inductor unit can achieve a non-polarity connection between the first bus and the second bus, which is more suitable for long-distance communication and consumes less power. Moreover, since the communication line bus has a long transmission distance, the rectifier bridge circuit of the utility model uses a MOS tube as a rectifier bridge, which has a small on-resistance and a forward voltage drop that can be much lower than that of an ordinary diode, so the power consumption of the power supply is reduced, and it is used in long-distance communication to reduce power consumption.

[0061] In some embodiments, the active inductor module 10 also includes an overcurrent protection unit 400; the first control end of the overcurrent protection unit 400 is connected to the active inductor unit 100, and the overcurrent protection unit 200 is used to control the active inductor unit 100 to implement overcurrent protection, so that when the output end is short-circuited, the voltage on the transmission bus can be lowered to avoid affecting the communication of other devices.

[0062] In some embodiments, the active inductor module 10 further includes an over-temperature protection unit 500; a first control end of the over-temperature protection unit 500 is connected to the active inductor unit 100, and the over-temperature protection unit 500 is used to control the active inductor unit 100 to implement over-temperature protection, so that when the temperature is abnormal, the active inductor unit 100 is turned off.

[0063] The active inductor module 10 of this embodiment integrates protection functions such as over-current protection and over-temperature protection, so that when integrated into a chip, the chip is shut down when the chip temperature is abnormal or the output is short-circuited without affecting the communication of other nodes on the transmission line.

[0064] In some embodiments, the active inductor module 10 further includes a power supply unit 300; the first input end of the power supply unit 300 is connected to the DC power signal output end VDD, and the first output end of the power supply unit 300 is connected to the constant voltage output end VO; the constant voltage output end VO is used to output a constant voltage. The second input end of the power supply unit 300 is connected to the enable end EN, and the power on / off function of the power supply unit 300 can be realized through the enable end EN. The power supply unit 300 is used to step down the DC power signal output by the active inductor unit 100 and output a constant voltage, which can ensure that the differential signal of the transmission bus is not absorbed by the power supply part capacitor, and obtain the DC power on the transmission bus. For example, the power supply unit 300 can directly control the output voltage of 5V, which is simple to apply and easy to apply to more scenarios of slave devices. In some embodiments, the power supply unit 300 can be implemented by LDO or charge pump principle. By using LDO, the circuit is simple, there is no electromagnetic interference, and the cost is low; by using a charge pump, the conversion efficiency is better and the performance is better. This slave device takes the wire controller product in the air-conditioning field as an example. A single wire controller usually only needs to draw a current of less than 200mA, and the power is relatively small, so the power supply unit can be designed using either LDO or charge pump.

[0065] The active inductor module 10 provided in this embodiment can be used in more scenarios by directly obtaining a low voltage fixed voltage value. If other voltage values ​​are to be obtained, the DC power signal output terminal VDD of the chip can be further connected to the power supply module 20 for power conversion.

[0066] Accordingly, see Figure 1 The present invention further provides a coding module 40 used in conjunction with the dynamic impedance module. The coding module 40 is used to receive an input signal TXD through a coding input terminal DATA IN, encode the input signal TXD, and output a differential signal through two coding output terminals, namely OUT (A) and OUT (B). The two coding output terminals, namely OUT (A) and OUT (B), of the coding module 40 are respectively connected to a first bus A and a second bus B. In other embodiments, the coding module 40 may be a separate chip, such as a communication chip.

[0067] Accordingly, the present invention further provides a chip, on which the dynamic matching module described above is integrated, and a coding module may also be integrated. Figure 7 , the chip can integrate a rectifier bridge, an active inductor unit, and a DC-DC power supply unit. Figure 8 The chip can also integrate the dynamic matching module with the rectifier bridge, active inductor unit, and DC-DC power supply unit. This greatly saves the solution cost, makes the solution design simpler, and the overall integration is higher than the traditional solution, and the communication effect is more stable.

[0068] Correspondingly, the utility model also provides a system, including the chip mentioned above.

[0069] Although the utility model has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.

Claims

1. A dynamic matching module, characterized in that: Used in conjunction with an external encoding module, the encoding module is used to receive an input signal through an encoding input terminal, encode the input signal and output a differential signal through two encoding output terminals, the two encoding output terminals of the encoding module are respectively connected to a first bus and a second bus; It includes: a first delay unit, a MOS tube and a waveform optimization unit; The first delay unit is used for, when the input signal switches from the first level to the second level, starting delay based on the second level and turning on the power supply to the MOS tube so as to turn on the MOS tube, and ending the delay and stopping the power supply to the MOS tube when the first predetermined time interval is reached so as to turn off the MOS tube; The MOS tube is used to connect the waveform optimization unit to the two encoding output terminals after being turned on, and disconnect the connection between the waveform optimization unit and the two encoding output terminals after being turned off; The waveform optimization unit is used to quickly switch the voltage difference between the two encoding output ends from a preset voltage difference to 0V.

2. The dynamic matching module according to claim 1, characterized in that: The MOS transistor includes a first MOS transistor Q4 and a second MOS transistor Q5, and the waveform optimization unit includes a first waveform optimization unit and a second waveform optimization unit. The source S of the first MOS transistor Q4 is connected to the first coding output end through the first waveform optimization unit, the drain D of the second MOS transistor Q5 is connected to the first coding output end, the gate G of the first MOS transistor Q4 and the gate G of the second MOS transistor Q5 are connected to the first delay unit, the drain D of the first MOS transistor Q4 is connected to the second coding output end, and the source S of the second MOS transistor Q5 is connected to the second coding output end through the second waveform optimization unit.

3. The dynamic matching module according to claim 1, characterized in that: Also includes a first charging unit and a first discharging unit; The first charging unit is used to charge the parasitic capacitor Cgs of the MOS tube to form a charging loop when the input signal is at the second level and the power supply to the MOS tube is turned on, so as to quickly turn on the MOS tube; The first discharge unit is used to form a discharge loop for discharging the parasitic capacitance Cgs of the MOS tube when the input signal is at the second level and the delay ends and the power supply to the MOS tube stops when the first predetermined time interval is reached, so as to quickly shut down the MOS tube.

4. The dynamic matching module according to claim 1, characterized in that: The dynamic matching module also includes a second discharge unit; The second discharge unit is used to start delaying based on the second level when the input signal switches from the first level to the second level, and discharge the MOS tube when a second predetermined time interval is reached, so as to quickly turn off the MOS tube, wherein the second predetermined time interval is greater than the first predetermined time interval.

5. The dynamic matching module according to claim 4, characterized in that: The second discharge unit includes a second delay unit, a first discharge sub-unit and a second discharge sub-unit; The second delay unit is used for starting delay based on the second level when the input signal switches from the first level to the second level, and ending the delay when the second predetermined time interval is reached and turning on the first discharge sub-unit; wherein the second predetermined time interval is greater than the first predetermined time interval; The first discharge sub-unit is used to discharge the parasitic capacitance Cgs of the MOS tube after being turned on, so as to quickly turn off the MOS tube; The second discharge sub-unit is used for discharging the second delay unit based on the first level to disconnect the first discharge sub-unit when the input signal switches from the second level to the first level according to a normal switching cycle.

6. The dynamic matching module according to claim 5, characterized in that: The first discharge electronic unit includes a third triode Q3 and a stabilizing unit; the collector of the third triode Q3 is connected to the base of the third triode Q3, the collector of the third triode Q3 is connected to the gate of the MOS tube, the collector of the third triode Q3 is also connected to the input signal terminal V1 through the stabilizing unit, and the input signal terminal V1 is connected to the base of the third triode Q3; The third transistor Q3 is used to discharge the MOS tube; The stabilization unit is used to isolate the third transistor Q3 and the input signal terminal V1 during the process of the third transistor Q3 discharging the MOS tube, so as to prevent the first discharge sub-unit from interfering with the input signal inputted by the input signal terminal V1.

7. The dynamic matching module according to claim 6, characterized in that: The second delay unit includes a second capacitor C2 and a sixth resistor R6, the second discharge sub-unit includes a first diode D1, the stabilization unit includes a first transistor Q1 and a second transistor Q2, one end of the second capacitor C2 is connected to the base of the third transistor Q3 through the seventh resistor R7, and is connected to the input signal terminal V1 through the sixth resistor R6, the input signal terminal V1 is used to receive an input signal, the other end of the second capacitor C2 is connected to the ground terminal, the collector of the third transistor Q3 is connected to the gate of the MOS tube and the collector of the first transistor Q1, the emitter of the third transistor Q3 is connected to the ground terminal, and the emitter of the first transistor Q1 is connected to the input signal terminal V1. The base of the first transistor Q1 is connected to the input signal terminal V1 through the second resistor R2, the base of the first transistor Q1 is connected to the collector of the second transistor Q2 through the fourth resistor R4, the base of the second transistor Q2 is connected to the first delay unit through the first resistor R1, the base of the second transistor Q2 is connected to the emitter of the second transistor Q2 through the third resistor R3, the emitter of the second transistor Q2 is connected to the ground terminal, the cathode of the first diode D1 is connected to the input signal terminal V1, and the anode of the first diode D1 is connected to one end of the second capacitor C2 and the seventh resistor R7, and is connected to the ground terminal through the fifth resistor R5.

8. The dynamic matching module according to claim 1, characterized in that: Also includes: The anti-backflow unit located between the MOS tube and the waveform optimization unit is used to prevent the dynamic matching module from having current backflow when the two encoding output ends stop outputting signals.

9. The dynamic matching module according to claim 8, characterized in that: The anti-backflow unit is an anti-backflow diode, the positive electrode of the anti-backflow diode is connected to the source of the MOS tube, and the negative electrode of the anti-backflow diode is connected to one end of the waveform optimization unit.

10. A chip, characterized in that: Comprising a dynamic matching module according to any one of claims 1-9.

11. A system, characterized in that: Comprising the chip according to claim 10.

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