Multipath frequency multiplier

Abstract

A first LC filter is connected with an amplifier, the amplifier is connected with a first power divider, the first power divider is connected with a second power divider, the second power divider is connected with a third power divider, the third power divider is connected with a fifth power divider and a sixth power divider, and the fifth power divider is connected with the first amplifier and the second amplifier. The sixth power divider is connected with the third amplifier and the fourth amplifier, the first amplifier is connected with the first band-pass filter, the second amplifier is connected with the second band-pass filter, the third amplifier is connected with the third band-pass filter, and the fourth amplifier is connected with the fourth band-pass filter. According to the multi-path frequency multiplier provided by the utility model, after XXMHz high-stability low-phase noise input signals are subjected to power division, amplification and filtering, four groups of XXMHz + / -XXMHz intermediate frequencies have an independent control switching function; all the components in the device can be domestic components, so that the manufacturing cost is low.

Description

Technical Field

[0001] The utility model relates to a multi-channel frequency multiplier, belonging to the technical field of frequency multipliers. Background Art

[0002] Frequency multiplier is a circuit that makes the output signal frequency equal to an integer multiple of the input signal frequency. If the input frequency is f1, the output frequency is f0=nf1, and the coefficient n is any positive integer, which is called the frequency multiplication number. Frequency multipliers are widely used. For example, the transmitter can make the master oscillator oscillate at a lower frequency to improve the frequency stability after using the frequency multiplier; the frequency modulation equipment uses the frequency multiplier to increase the frequency deviation; in the phase keying communication machine, the frequency multiplier is an important component of the carrier recovery circuit.

[0003] The frequency multiplier in conventional technology has a complex structure and mostly uses foreign components, which has a high manufacturing cost and is in urgent need of improvement. Utility Model Content

[0004] The technical problem to be solved by the utility model is to overcome the defects of the prior art and provide a multi-channel frequency multiplier. The multi-channel frequency multiplier provided by the utility model performs power division, amplification and filtering on the XXMHz high-stable and low-phase-noise input signal to output eight-channel XXMHz reference signals XS1, XS2, XS3, XS4, XS5, XS6, XS7 and XS8; performs power division, frequency multiplication, amplification and filtering on the XXMHz high-stable and low-phase-noise input signal to generate four-channel XXMHz signal outputs XS9, XS10, XS11 and XS 12; after switching and filtering, the eight-channel XXM±XXM reference signals XS13, XS14, XS16, XS17, XS18, XS19, XS20 and XS21 generate four XXMHz±XXMHz signal outputs XS22, XS23, XS24 and XS25; the four groups of XXMHz±XXMHz intermediate frequencies have a separate control switching function; the components in this device can all be domestically produced components, and the manufacturing cost is lower than that of the frequency multiplier using foreign components, saving the production cost of the enterprise.

[0005] In a first aspect, the utility model provides a multi-channel frequency multiplier, comprising a first LC filter, an amplifier, a first power divider, a second power divider, a third power divider, a fifth power divider, a sixth power divider, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first band-pass filter, a second band-pass filter, a third band-pass filter and a fourth band-pass filter, wherein the output end of the first LC filter is connected to the input end of the amplifier, the output end of the amplifier is connected to the input end of the first power divider, the output end of the first power divider is connected to the input end of the second power divider, the output end of the second power divider is connected to the input end of the third power divider, the output end of the third power divider is connected to the input end of the fifth power divider and the input end of the sixth power divider, the output end of the fifth power divider is connected to the input end of the first amplifier and the input end of the second amplifier, the output end of the sixth power divider is connected to the input end of the third amplifier and the input end of the fourth amplifier, the output end of the first amplifier is connected to the input end of the first band-pass filter, the output end of the second amplifier is connected to the input end of the second band-pass filter, the output end of the third amplifier is connected to the input end of the third band-pass filter, and the output end of the fourth amplifier is connected to the input end of the fourth band-pass filter.

[0006] Preferentially, it includes a fourth power divider, a seventh power divider, an eighth power divider, a fifth amplifier, a sixth amplifier, a seventh amplifier, an eighth amplifier, a fifth band-pass filter, a sixth band-pass filter, a seventh band-pass filter and an eighth band-pass filter, the output end of the second power divider is connected to the input end of the fourth power divider, the output end of the fourth power divider is connected to the input end of the seventh power divider and the input end of the eighth power divider, the output end of the seventh power divider is connected to the input end of the fifth amplifier and the input end of the sixth amplifier, the output end of the eighth power divider is connected to the input end of the seventh amplifier and the input end of the eighth amplifier, the output end of the fifth amplifier is connected to the input end of the fifth band-pass filter, the output end of the sixth amplifier is connected to the input end of the sixth band-pass filter, the output end of the seventh amplifier is connected to the input end of the seventh band-pass filter, and the output end of the eighth amplifier is connected to the input end of the eighth band-pass filter.

[0007] Preferably, it includes a first AND operation chip and a second AND operation chip, the output end of the first amplifier, the output end of the second amplifier, the output end of the third amplifier, the output end of the fourth amplifier, the output end of the fifth amplifier, the output end of the sixth amplifier, the output end of the seventh amplifier and the output end of the eighth amplifier are connected to the input end of the first AND operation chip, and the output end of the first AND operation chip and the input end of the first LC filter are connected to the input end of the second AND operation chip.

[0008] Preferentially, it includes a ninth amplifier, a frequency doubling filter, a ninth power divider, a tenth power divider, an eleventh power divider, a ninth amplifier, a tenth amplifier, an eleventh amplifier, a twelfth amplifier, a fifth LC filter, a sixth LC filter, a seventh LC filter and an eighth LC filter, the output end of the first power divider is connected to the input end of the ninth amplifier, the output end of the ninth amplifier is connected to the input end of the frequency doubling filter, the output end of the frequency doubling filter is connected to the input end of the ninth power divider, the output end of the ninth power divider is connected to the input end of the tenth power divider and the input end of the eleventh power divider, the output end of the tenth power divider is connected to the input end of the ninth amplifier and the input end of the tenth amplifier, the output end of the eleventh power divider is connected to the input end of the eleventh amplifier and the input end of the twelfth amplifier, the output end of the ninth amplifier is connected to the input end of the fifth LC filter, the output end of the tenth amplifier is connected to the input end of the sixth LC filter, the output end of the eleventh amplifier is connected to the input end of the seventh LC filter, and the output end of the twelfth amplifier is connected to the input end of the eighth LC filter.

[0009] Preferably, a third AND operation chip and a fourth AND operation chip are included, the output end of the ninth amplifier and the output end of the tenth amplifier are connected to the input end of the third AND operation chip, the output end of the eleventh amplifier and the output end of the twelfth amplifier are connected to the input end of the fourth AND operation chip, and the output end of the third AND operation chip and the output end of the fourth AND operation chip are connected to the input end of the second AND operation chip.

[0010] Preferably, the method comprises a controller, a switch 1, a switch 2, a switch 3, a switch 4, a switch 5, a switch 6, a switch 7, a switch 8, a switch 9, a switch 10, a switch 11, a switch 12, a first LC filter, a second LC filter, a third LC filter and a fourth LC filter, wherein the output end of the controller is connected to the input end of the switch 1, the input end of the switch 2, the input end of the switch 4, the input end of the switch 5, the input end of the switch 7, the input end of the switch 8, the input end of the switch 10 and the input end of the switch 11, the output end of the switch 1 and the output end of the switch 2 are connected to the input end of the switch 3, the output end of the switch 4 and the output end of the switch 5 are connected to the input end of the switch 6, the output end of the switch 7 and the output end of the switch 8 are connected to the input end of the switch 9, the output end of the switch 10 and the output end of the switch 11 are connected to the input end of the switch 12, the output end of the switch 3 is connected to the input end of the first LC filter, the output end of the switch 6 is connected to the input end of the second LC filter, the output end of the switch 9 is connected to the input end of the third LC filter, and the output end of the switch 12 is connected to the input end of the first LC filter.

[0011] Preferentially, the first diode, the second diode, the third diode, the fourth diode, the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are included, the detected signal BIT5 is connected in series with the first diode and the resistor R1 and then grounded, the detected signal BIT6 is connected in series with the second diode and the resistor R2 and then grounded, the detected signal BIT7 is connected in series with the third diode and the resistor R3 and then grounded, and the detected signal BIT8 is connected in series with the fourth diode and the resistor R4 and then grounded.

[0012] Beneficial effects achieved by the utility model:

[0013] The multi-channel frequency multiplier provided by the utility model performs power division, amplification and filtering on the XXMHz high-stable and low-phase-noise input signal, and outputs eight-channel XXMHz reference signals XS1, XS2, XS3, XS4, XS5, XS6, XS7 and XS8; performs power division, frequency multiplication, amplification and filtering on the XXMHz high-stable and low-phase-noise input signal, and generates four-channel XXMHz signal outputs XS9, XS10, XS11 and XS12; and performs eight-channel XXM±XXM reference signals After switching and filtering, XS13, XS14, XS16, XS17, XS18, XS19, XS20 and XS21 generate four XXMHz±XXMHz signal outputs XS22, XS23, XS24 and XS25; the four groups of XXMHz±XXMHz intermediate frequencies have the function of independent control and switching; the components in this device can all be domestically produced, and the manufacturing cost is lower than that of the frequency multiplier using foreign components, saving the production cost of the enterprise.

[0014] The maximum output power of this device depends on the gain and P-1 of the final amplifier. The maximum insertion loss of the filter and coupler at the output of the amplifier is 2.2dB, so the final output power can reach 16.8dBm, which can meet the output power requirements. This device has four intermediate frequency links with independent channels. The isolation index is deteriorated mainly due to port signal leakage. Therefore, in order to avoid the problem of signal leakage between ports, the component structure adopts a cavity design and uses low-frequency absorbing materials to suppress channel interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 It is a structural diagram of some embodiments of the present application. DETAILED DESCRIPTION

[0017] To facilitate the technical solution of the application, some concepts involved in the application are first explained below.

[0018] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention, they are only used to explain the relative position relationship and movement status of the various components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0019] In addition, if the descriptions of "first" and "second" etc. are involved in the present utility model, they are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0020] See also Figure 1The utility model provides a multi-channel frequency multiplier, comprising a first LC filter, an amplifier, a first power divider, a second power divider, a third power divider, a fifth power divider, a sixth power divider, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first band-pass filter, a second band-pass filter, a third band-pass filter and a fourth band-pass filter, the output end of the first LC filter is connected to the input end of the amplifier, the output end of the amplifier is connected to the input end of the first power divider, the output end of the first power divider is connected to the input end of the second power divider, the output end of the second power divider is connected to the input end of the third power divider, the output end of the third power divider is connected to the input end of the fifth power divider and the input end of the sixth power divider, the output end of the fifth power divider is connected to the input end of the first amplifier and the input end of the second amplifier, the output end of the sixth power divider is connected to the input end of the third amplifier and the input end of the fourth amplifier, the output end of the first amplifier is connected to the input end of the first band-pass filter, the output end of the second amplifier is connected to the input end of the second band-pass filter, the output end of the third amplifier is connected to the input end of the third band-pass filter, and the output end of the fourth amplifier is connected to the input end of the fourth band-pass filter. The multi-channel frequency multiplier outputs eight XXMHz reference signals XS1, XS2, XS3, XS4, XS5, XS6, XS7 and XS8 after power division, frequency multiplication and filtering of the XXMHz high-stable and low-phase-noise input signal; generates four XXMHz signal outputs XS9, XS10, XS11 and XS12 after power division, frequency multiplication, amplification and filtering of the XXMHz high-stable and low-phase-noise input signal; generates four XXMHz±XXMHz signal outputs XS22, XS23, XS24 and XS25 after switching and filtering the eight-channel XXM±XXM reference signals XS13, XS14, XS16, XS17, XS18, XS19, XS20 and XS21; and the four groups of XXMHz±XXMHz intermediate frequencies have separate control and switching functions.

[0021] Among them, ①XXMHz input signal is input to BIT0; ②XXMHz signals (BTT1a, BTT1b, BTT1c, BTT1d, BTT1e, BTT1f, BTT1g, BTT1h) are ANDed and output to BIT1. Specifically, BTT1a, BTT1b, BTT1c, BTT1d, BTT1e, BTT1f, BTT1g, BTT1h have the same frequency, and eight channels are BIT-detected, namely BIT1a-BIT1h. These eight BITs are ANDed and BIT1 is obtained; ③XXMHz signals (BTT2a, BTT2b) are ANDed and output to BIT2; ④XXMHz signals (BTT3a, BTT3b ) are ANDed and output BIT3; ⑤ The reference signals BIT0, BIT1, BIT2 and BIT3 are ANDed and output BIT4; ⑥ The first intermediate frequency (signal input ports are XS13 and XS14, and the signal output port is XS22) is detected by signal after switching BIT5; ⑦ The second intermediate frequency (signal input ports are XS16 and XS17, and the signal output port is XS23) is detected by signal after switching BIT6; ⑧ The third intermediate frequency (signal input ports are XS18 and XS19, and the signal output port is XS24) is detected by signal after switching BIT7; ⑨ The fourth intermediate frequency (signal input ports are XS20 and XS21, and the signal output port is XS25) is detected by signal after switching BIT8.

[0022] This device provides fault detection for all input RF signals and output RF signals, 1-normal, 0-fault, when the power drops by more than 10dB from the normal value, it is judged as a fault. Among them, BIT0~BIT4 (the detected signal is a continuous wave), BIT5~BIT8 (the detected signal is a modulated pulse or a continuous wave).

[0023] In the embodiment of the present application, a fourth power divider, a seventh power divider, an eighth power divider, a fifth amplifier, a sixth amplifier, a seventh amplifier, an eighth amplifier, a fifth band-pass filter, a sixth band-pass filter, a seventh band-pass filter and an eighth band-pass filter are included, the output end of the second power divider is connected to the input end of the fourth power divider, the output end of the fourth power divider is connected to the input end of the seventh power divider and the input end of the eighth power divider, the output end of the seventh power divider is connected to the input end of the fifth amplifier and the input end of the sixth amplifier, the output end of the eighth power divider is connected to the input end of the seventh amplifier and the input end of the eighth amplifier, the output end of the fifth amplifier is connected to the input end of the fifth band-pass filter, the output end of the sixth amplifier is connected to the input end of the sixth band-pass filter, the output end of the seventh amplifier is connected to the input end of the seventh band-pass filter, and the output end of the eighth amplifier is connected to the input end of the eighth band-pass filter.

[0024] In an embodiment of the present application, a first AND operation chip and a second AND operation chip are included, and the output end of the first amplifier, the output end of the second amplifier, the output end of the third amplifier, the output end of the fourth amplifier, the output end of the fifth amplifier, the output end of the sixth amplifier, the output end of the seventh amplifier and the output end of the eighth amplifier are connected to the input end of the first AND operation chip, and the output end of the first AND operation chip and the input end of the first LC filter are connected to the input end of the second AND operation chip.

[0025] In the embodiment of the present application, a ninth amplifier, a frequency doubling filter, a ninth power divider, a tenth power divider, an eleventh power divider, a ninth amplifier, a tenth amplifier, an eleventh amplifier, a twelfth amplifier, a fifth LC filter, a sixth LC filter, a seventh LC filter and an eighth LC filter are included. The output end of the first power divider is connected to the input end of the ninth amplifier, the output end of the ninth amplifier is connected to the input end of the frequency doubling filter, the output end of the frequency doubling filter is connected to the input end of the ninth power divider, the output end of the ninth power divider is connected to the input end of the tenth power divider and the input end of the eleventh power divider, the output end of the tenth power divider is connected to the input end of the ninth amplifier and the input end of the tenth amplifier, the output end of the eleventh power divider is connected to the input end of the eleventh amplifier and the input end of the twelfth amplifier, the output end of the ninth amplifier is connected to the input end of the fifth LC filter, the output end of the tenth amplifier is connected to the input end of the sixth LC filter, the output end of the eleventh amplifier is connected to the input end of the seventh LC filter, and the output end of the twelfth amplifier is connected to the input end of the eighth LC filter.

[0026] In an embodiment of the present application, a third AND operation chip and a fourth AND operation chip are included, the output end of the ninth amplifier and the output end of the tenth amplifier are connected to the input end of the third AND operation chip, the output end of the eleventh amplifier and the output end of the twelfth amplifier are connected to the input end of the fourth AND operation chip, and the output end of the third AND operation chip and the output end of the fourth AND operation chip are connected to the input end of the second AND operation chip.

[0027] In the embodiment of the present application, a controller, a switch 1, a switch 2, a switch 3, a switch 4, a switch 5, a switch 6, a switch 7, a switch 8, a switch 9, a switch 10, a switch 11, a switch 12, a first LC filter, a second LC filter, a third LC filter and a fourth LC filter are included. The output end of the controller is connected to the input end of the switch 1, the input end of the switch 2, the input end of the switch 4, the input end of the switch 5, the input end of the switch 7, the input end of the switch 8, the input end of the switch 10 and the input end of the switch 11. The output end of the switch 1 and the output end of the switch 2 are connected to the input end of the switch 3. The output end of the switch 4 and the output end of the switch 5 are connected to the input end of the switch 6. The output end of the switch 7 and the output end of the switch 8 are connected to the input end of the switch 9. The output end of the switch 10 and the output end of the switch 11 are connected to the input end of the switch 12. The output end of the switch 3 is connected to the input end of the first LC filter, the output end of the switch 6 is connected to the input end of the second LC filter, the output end of the switch 9 is connected to the input end of the third LC filter, and the output end of the switch 12 is connected to the input end of the first LC filter.

[0028] In the embodiment of the present application, a first diode, a second diode, a third diode, a fourth diode, a resistor R1, a resistor R2, a resistor R3 and a resistor R4 are included. The detected signal BIT5 is connected in series with the first diode and the resistor R1 and then grounded. The detected signal BIT6 is connected in series with the second diode and the resistor R2 and then grounded. The detected signal BIT7 is connected in series with the third diode and the resistor R3 and then grounded. The detected signal BIT8 is connected in series with the fourth diode and the resistor R4 and then grounded.

[0029] The device's input / output signal requirements include:

[0030] a.XS1~XS8 output frequency and power: XXMHz / 13±1dBm;

[0031] b.XS9~XS10 output frequency and power: XXMHz / 13±1dBm;

[0032] c.XS11~XS12 output frequency and power: XXMHz / 13±1dBm;

[0033] d.XS13~XS14 input frequency and power: XXMHz / 0±2dBm;

[0034] e.XS16~XS17 input frequency and power: XXMHz / 0±2dBm;

[0035] f.XS18~XS19 input frequency and power: XXMHz / 0±2dBm;

[0036] g.XS20~XS21 input frequency and power: XXMHz / 0±2dBm;

[0037] h.XS22~XS25 output frequency and power: XXMHz / -2.5±3dBm;

[0038] i.XS15 input frequency and power: XXMHz / 10±2dBm;

[0039] The index requirements that this device can achieve are:

[0040] a. Spurious: ≤-85dBc;

[0041] b. Harmonics: ≤-40dBc;

[0042] c. Same channel isolation (XXMHz): ≤-50dBc;

[0043] d. Output phase noise (XXMHz): ≤-159dBc / Hz / 1kHz;

[0044] e. Output phase noise (XXMHz): ≤-145dBc / Hz / 1kHz;

[0045] f. Switch isolation: ≤-90dBc;

[0046] g. Four-way intermediate frequency output isolation (XXMHz): ≤-90dBc;

[0047] h. Input and output standing wave ratio: ≤1.5;

[0048] i. Switching speed: 200ns;

[0049] j. Phase consistency: -5°~5°.

[0050] The device has control code requirements: Input control code: C1, C2, C3, C4.

[0051] C1: 0---XS13, 1---XS14; C2: 0---XS16, 1---XS17; C3: 0---XS18, 1---XS19; C4: 0---XS20, 1---XS21. This device consists of three groups of radio frequency links with different frequencies: the first XXMHz radio frequency link, the second XXMHz radio frequency link, and XXM±XXMHz. Therefore, a segmented power level simulation calculation is performed to reasonably distribute the gains of each part in the link to achieve the ideal output.

[0052] First XXMHz RF link: The component input power is 10±2dBm. Based on the flow analysis of the RF signal, the RF link power level is calculated with Pin=10dBm as the reference power. The XXMHz RF link is simulated and calculated using simulation software. The simulation result is: the link output port power is 13.32dBm, which can meet the XXMHz output power technical indicator requirement (13±1dBm).

[0053] Second XXMHz RF link: The component input power is 10±2dBm. The RF link power level is calculated based on the flow of the RF signal and Pin=10dBm is used as the reference power. In this link, the device uses the frequency multiplier IGB-003B-S89 from Hefei Core Valley, a domestic manufacturer. Through actual measurement of the test board of the frequency multiplier (measured data see Table 3), the reference signal 6dBm is finally selected as the input power value of the frequency multiplier, and the output power after frequency multiplication is 0dBm.

[0054] XXM±XXMHz RF link: The component input power is 0±2dBm. The RF link power level is calculated based on the flow of the RF signal and Pin=0dBm is used as the reference power. The XXM±XXMHz RF link is simulated using simulation software. The simulation result is: the link output port power is -3.8dBm, which can meet the XXM±XXMHz output power technical indicator requirements (-2.5±3dBm).

[0055] The simulation software can be used to simulate and calculate the first XXMHz radio frequency link or the second XXMHz radio frequency link. The simulation result is: the output port power of the link is 12.65dBm, which can meet the XXMHz output power technical indicator requirement (13±1dBm).

[0056] The maximum output power of this device depends on the gain and P-1 of the final amplifier. The IGB-030F-S89 amplifier from the domestic manufacturer Hefei XinGu is selected as the final amplifier. P-1 is 19dBm, and the maximum total insertion loss of the filter and coupler at the output end of the amplifier is 2.2dB, so the final output power can reach 16.8dBm, thus meeting the output power requirements.

[0057] The clutter is mainly generated by amplifiers and frequency multipliers. In this device, an attenuator matching is added at the amplifier cascade to prevent the generation of clutter signals caused by standing wave mismatch in the amplifier cascade. The structure of this device adopts a split cavity design, which effectively avoids the phenomenon of self-excitation of components caused by excessive gain in the cavity.

[0058] The XXMHz input reference signal is effectively filtered by the LC filter EB120 / P-SMD37, so that the input signal has good out-of-band suppression;

[0059] The harmonics of the eight-channel XXMHz output chain are mainly generated by the RF amplifier IGB-030F-S89, which is effectively filtered out by the low-pass filter LLP-100-B of the 43rd Institute, and its suppression of the second harmonic (XXMHz) is 34dBc;

[0060] The harmonics of the XXMHz reference signal obtained by the frequency multiplier IGB-003B-S89 are filtered by the LC filter EB480 / P-5CC81. The harmonics of the four-channel XXMHz output link are mainly generated by the RF amplifier IGB-030F-S89, and are effectively filtered out by the low-pass filter LLP-500-B of the 43rd Institute, with a suppression degree of 32dBc for the second harmonic (XXMHz).

[0061] The harmonics of the four-channel XXM±XXMHz output link are effectively filtered out by the LC filter BL-145 / U60-7C, and its out-of-band suppression is 20dBc@DC-XXMHz&XX-XXMHz. The same-channel isolation (XXMHz) of this device can reach about -60dBc, which can meet the technical index requirements. This device has four-channel intermediate frequency links with independent channels. The isolation index is deteriorated mainly due to port signal leakage. Therefore, in order to avoid the problem of signal leakage between ports, the component structure adopts a cavity design, and low-frequency absorbing materials are used to suppress channel interference.

[0062] The switch isolation in this device depends on the isolation of the RF switch. Chengdu Shixin's high-isolation single-pole double-throw switch SIS108SP4B is selected. The switch isolation of the two channels at XXMHz can reach 65dB. After cascading, the switch isolation of the component can reach 130dB, which can meet the index requirements.

[0063] The switching response time of the component depends on the maximum switching time of the selected RF switch. The switching response time of the single-pole double-throw switch (SIS108SP4B) is 150ns, so it can meet the technical index requirements.

[0064] Phase noise refers to the phase shift of the signal caused by noise. The phase shift of the signal will interfere with the adjacent channel signal. Therefore, low phase noise plays an important role in improving the performance of the circuit system. It is very important to select a suitable filter to filter out the sideband signal generated by the phase shift of the signal. High vibration environment will also cause the phase noise to deteriorate. Therefore, it is necessary to ensure the firmness and stability of the device. At this time, the assembly process is also very important, especially the firmness of the inductor coil.

[0065] The index requirements of this device are:

[0066] ①Input phase noise (XXMHz): -160dBc / Hz / 1kHz;

[0067] ②Output phase noise (XXMHz): -159dBc / Hz / 1kHz;

[0068] ③Output phase noise (XXMHz): -145dBc / Hz / 1kHz

[0069] For the XXMHz signal chain, the system only involves filters, amplifiers, power dividers, couplers, and attenuators. The output phase noise will not deteriorate and can meet the technical indicators. The technical indicators of this device allow the output phase noise to deteriorate by 15dBc, so this design can meet the output phase noise technical indicator requirements.

[0070] In order to ensure a good standing wave ratio at the input and output ends, the impedance of the input and output ends must be matched, and the impedance of the devices must be matched. Therefore, ensuring the firmness of the port welding and installation and selecting devices with a good standing wave ratio can generally meet the technical index requirements.

[0071] The input port (XXMHz) standing wave ratio depends on the standing wave index of the LC filter EB120 / P-SMD37. The input / output standing wave of the filter is ≤1.5, so it can meet the technical index requirements.

[0072] The input port (XXM±XXMHz) standing wave ratio depends on the standing wave index of the RF switch SIS108SP4B. The input / output standing wave of the RF switch is ≤1.2, so it can meet the technical index requirements.

[0073] The standing wave ratios of the output port (XXMHz), output port (XXMHz), and output port (XXMHz) all depend on the standing wave index of the coupler C0083. The typical value of the input / output standing wave of the coupler is 1.3, so it can meet the technical index requirements.

[0074] The external power supply of this device is +5.5V, which is stabilized to +5V by the voltage regulator block HLW1816P, mainly providing the required voltage for the internal switch, amplifier, and control circuit. The voltage regulator block HLW1816P can achieve efficient power conversion, with a maximum conversion efficiency of more than 90%, and can carry a maximum current of 3A. Its output voltage VOUT can be adjusted by a resistor.

[0075] The first LC filter, the amplifier, the first power divider, the second power divider, the third power divider, the fifth power divider, the sixth power divider, the first amplifier, the second amplifier, the third amplifier, the fourth amplifier, the first band-pass filter, the second band-pass filter, the third band-pass filter, the fourth band-pass filter, the fourth power divider, the seventh power divider, the eighth power divider, the fifth amplifier, the sixth amplifier, the seventh amplifier, the eighth amplifier, the fifth band-pass filter, the sixth band-pass filter, the seventh band-pass filter, the eighth band-pass filter, the first AND operation chip, the second AND operation chip, the ninth amplifier, the frequency doubling filter, the ninth power divider, the tenth power divider, the eleventh power divider, the ninth amplifier, the tenth amplifier, the first There are many models of the eleventh amplifier, the twelfth amplifier, the fifth LC filter, the sixth LC filter, the seventh LC filter, the eighth LC filter, the third AND operation chip, the fourth AND operation chip, the controller, the switch one, the switch two, the switch three, the switch four, the switch five, the switch six, the switch seven, the switch eight, the switch nine, the switch ten, the switch eleven, the switch twelve, the first LC filter, the second LC filter, the third LC filter, the fourth LC filter, the first diode, the second diode, the third diode, the fourth diode, the resistor R1, the resistor R2, the resistor R3 and the resistor R4 that can be used in the prior art. Those skilled in the art can select them according to actual needs, and no examples are given in this embodiment. All domestic original components can be used in this device, among which the amplifier can adopt model IGB-003B-S89, the coupler can adopt model C0083, the power regulator can adopt model HLW1816P, the power divider can adopt model S0154, the switch can adopt model SIS108SP4B, the AND gate can adopt model RS1G08XC5 and RS4G00, the low-pass filter can adopt model LLP-100-B, the PCB board can adopt model RA300+FR4 mixed pressure, the LC filter can adopt model EB480 / P-5CC81, the insulator can adopt model JYZ-2020-16-0.7, and the RF connector can adopt model SMP-JFD7.

[0076] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0077] Those skilled in the art will readily come up with other embodiments of the present invention after considering the specification and practicing the utility model herein. This application is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art that are not invented by the present invention. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0078] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above are only specific implementation methods of the present application and are not used to limit the protection scope of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application should be included in the protection scope of the present application.

Claims

1. A multi-channel frequency multiplier, characterized in that: The invention comprises a first LC filter, an amplifier, a first power divider, a second power divider, a third power divider, a fifth power divider, a sixth power divider, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first band-pass filter, a second band-pass filter, a third band-pass filter and a fourth band-pass filter, wherein the output end of the first LC filter is connected to the input end of the amplifier, the output end of the amplifier is connected to the input end of the first power divider, the output end of the first power divider is connected to the input end of the second power divider, the output end of the second power divider is connected to the input end of the third power divider, the output end of the third power divider is connected to the input end of the fifth power divider and the input end of the sixth power divider, the output end of the fifth power divider is connected to the input end of the first amplifier and the input end of the second amplifier, the output end of the sixth power divider is connected to the input end of the third amplifier and the input end of the fourth amplifier, the output end of the first amplifier is connected to the input end of the first band-pass filter, the output end of the second amplifier is connected to the input end of the second band-pass filter, the output end of the third amplifier is connected to the input end of the third band-pass filter, and the output end of the fourth amplifier is connected to the input end of the fourth band-pass filter.

2. A multi-channel frequency multiplier according to claim 1, characterized in that: The invention comprises a fourth power divider, a seventh power divider, an eighth power divider, a fifth amplifier, a sixth amplifier, a seventh amplifier, an eighth amplifier, a fifth band-pass filter, a sixth band-pass filter, a seventh band-pass filter and an eighth band-pass filter, wherein the output end of the second power divider is connected to the input end of the fourth power divider, the output end of the fourth power divider is connected to the input end of the seventh power divider and the input end of the eighth power divider, the output end of the seventh power divider is connected to the input end of the fifth amplifier and the input end of the sixth amplifier, the output end of the eighth power divider is connected to the input end of the seventh amplifier and the input end of the eighth amplifier, the output end of the fifth amplifier is connected to the input end of the fifth band-pass filter, the output end of the sixth amplifier is connected to the input end of the sixth band-pass filter, the output end of the seventh amplifier is connected to the input end of the seventh band-pass filter, and the output end of the eighth amplifier is connected to the input end of the eighth band-pass filter.

3. A multi-channel frequency multiplier according to claim 2, characterized in that: The invention comprises a first AND operation chip and a second AND operation chip, wherein the output end of the first amplifier, the output end of the second amplifier, the output end of the third amplifier, the output end of the fourth amplifier, the output end of the fifth amplifier, the output end of the sixth amplifier, the output end of the seventh amplifier and the output end of the eighth amplifier are connected to the input end of the first AND operation chip, and the output end of the first AND operation chip and the input end of the first LC filter are connected to the input end of the second AND operation chip.

4. A multi-channel frequency multiplier according to claim 3, characterized in that: The invention comprises a ninth amplifier, a frequency doubling filter, a ninth power divider, a tenth power divider, an eleventh power divider, a ninth amplifier, a tenth amplifier, an eleventh amplifier, a twelfth amplifier, a fifth LC filter, a sixth LC filter, a seventh LC filter and an eighth LC filter, wherein the output end of the first power divider is connected to the input end of the ninth amplifier, the output end of the ninth amplifier is connected to the input end of the frequency doubling filter, the output end of the frequency doubling filter is connected to the input end of the ninth power divider, the output end of the ninth power divider is connected to the input end of the tenth power divider and the input end of the eleventh power divider, the output end of the tenth power divider is connected to the input end of the ninth amplifier and the input end of the tenth amplifier, the output end of the eleventh power divider is connected to the input end of the eleventh amplifier and the input end of the twelfth amplifier, the output end of the ninth amplifier is connected to the input end of the fifth LC filter, the output end of the tenth amplifier is connected to the input end of the sixth LC filter, the output end of the eleventh amplifier is connected to the input end of the seventh LC filter, and the output end of the twelfth amplifier is connected to the input end of the eighth LC filter.

5. A multi-channel frequency multiplier according to claim 4, characterized in that: It includes a third AND operation chip and a fourth AND operation chip, the output end of the ninth amplifier and the output end of the tenth amplifier are connected to the input end of the third AND operation chip, the output end of the eleventh amplifier and the output end of the twelfth amplifier are connected to the input end of the fourth AND operation chip, and the output end of the third AND operation chip and the output end of the fourth AND operation chip are connected to the input end of the second AND operation chip.

6. A multi-channel frequency multiplier according to claim 1, characterized in that: The invention comprises a controller, a switch 1, a switch 2, a switch 3, a switch 4, a switch 5, a switch 6, a switch 7, a switch 8, a switch 9, a switch 10, a switch 11, a switch 12, a first LC filter, a second LC filter, a third LC filter and a fourth LC filter, wherein the output end of the controller is connected to the input end of the switch 1, the input end of the switch 2, the input end of the switch 4, the input end of the switch 5, the input end of the switch 7, the input end of the switch 8, the input end of the switch 10 and the input end of the switch 11, the output end of the switch 1 and the output end of the switch 2 are connected to the input end of the switch 3, the output end of the switch 4 and the output end of the switch 5 are connected to the input end of the switch 6, the output end of the switch 7 and the output end of the switch 8 are connected to the input end of the switch 9, the output end of the switch 10 and the output end of the switch 11 are connected to the input end of the switch 12, the output end of the switch 3 is connected to the input end of the first LC filter, the output end of the switch 6 is connected to the input end of the second LC filter, the output end of the switch 9 is connected to the input end of the third LC filter, and the output end of the switch 12 is connected to the input end of the first LC filter.

7. A multi-channel frequency multiplier according to claim 6, characterized in that: It includes a first diode, a second diode, a third diode, a fourth diode, a resistor R1, a resistor R2, a resistor R3 and a resistor R4. The detected signal BIT5 is connected in series with the first diode and the resistor R1 and then grounded. The detected signal BIT6 is connected in series with the second diode and the resistor R2 and then grounded. The detected signal BIT7 is connected in series with the third diode and the resistor R3 and then grounded. The detected signal BIT8 is connected in series with the fourth diode and the resistor R4 and then grounded.

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