Control circuit based on FPGA SOC architecture and liquid crystal screen

Abstract

The utility model provides a control circuit based on FPGA SOC architecture and a liquid crystal screen, and relates to the electronic circuit field, the control circuit comprises an SOC, an FPGA, an SD NAND, an SDRAM, and a video encoder, the SOC, the FPGA, the video encoder and the liquid crystal screen are connected in sequence, the FPGA is respectively connected with the SD NAND and the SDRAM, and the SOC and the SD NAND are connected with a bus driver. The FPGA + SOC architecture is adopted, when the SOC crashes due to various reasons, picture file indication information before the SOC crashes can be displayed on the liquid crystal screen, and the maintainability of the whole machine and the system is improved.

Description

Technical Field

[0001] The utility model relates to the field of electronic circuits, in particular to a control circuit and a liquid crystal screen based on an FPGA SOC architecture. Background Art

[0002] The general airborne (special) display is implemented with FPGA+SOC architecture. The SOC generates graphic images and sends them to the FPGA for processing, and then outputs them to the LCD screen for display. Due to the complex processing tasks of the SOC, it cannot completely avoid the occurrence of system crashes. When the SOC crashes, the FPGA generally outputs a simple and fixed character screen display, from which no explanation of the cause of the crash can be obtained, and the maintainability is low. Utility Model Content

[0003] The utility model provides a control circuit, a liquid crystal screen and a picture control method based on an FPGA SOC architecture. When the SOC crashes due to various reasons, a custom picture with key information before the crash can be displayed on the liquid crystal screen, thereby increasing the maintainability of the whole machine and the system.

[0004] On the one hand, an embodiment of the present invention provides a control circuit based on an FPGA SOC architecture, further comprising: a SOC, an FPGA, an SD NAND, an SDRAM, and a video encoder, wherein the SOC, the FPGA, the video encoder, and the LCD screen are connected in sequence, the FPGA is connected to the SD NAND and the SDRAM, respectively, and the SOC and the SD NAND are connected via a bus driver.

[0005] Preferably, the FPGA also includes: an SD NAND / SDRAM parameter calculation module, an SD NAND picture reading control module and an SDRAM controller, the SD NAND / SDRAM parameter calculation module, the SD NAND picture reading control module and the SDRAM controller, the video output module and the video encoder are connected in sequence; the SDRAM controller is connected to the SDRAM; the SDNAND controller is connected between the SD NAND picture reading control module and the SD NAND.

[0006] Preferably, the FPGA further comprises: a clock module, wherein the clock module is respectively connected to the SD NAND / SDRAM parameter calculation module, the SD NAND image reading control module, the SDRAM controller, and the video output module.

[0007] On the other hand, an embodiment of the present invention further provides a method for performing screen control using the above-mentioned control circuit based on FPGA SOC architecture, comprising:

[0008] When the SOC is in standby or downtime, the FPGA does not detect the video signal output by the SOC, and turns off the control signal OE of the bus driver, and the FPGA mounts the SD NAND;

[0009] The image file is read from the SD NAND through the SD IO bus and output to the LCD screen through the video encoder.

[0010] When the SOC is in standby or downtime, the FPGA does not detect the video signal output by the SOC, and turns off the control signal OE of the bus driver. Before the FPGA mounts the SD NAND, the following steps are also included:

[0011] When the SOC is in operation, it normally outputs the video signal to the FPGA, and after the FPGA completes the processing, it outputs it to the LCD screen through the video encoder;

[0012] At the same time, FPGA turns on the control signal OE of the bus driver and sets the SDIO bus to a high-impedance state. At this time, the SOC mounts the SD NAND and the SOC saves the image file to the SD NAND at a regular interval.

[0013] On the other hand, an embodiment of the present invention further provides a liquid crystal screen, wherein the liquid crystal screen is provided with the aforementioned control circuit based on FPGA SOC architecture.

[0014] The utility model provides a control circuit and a liquid crystal screen based on an FPGA SOC architecture. When the SOC is stuck due to abnormal operation, the FPGA outputs the indication information of the picture file saved before the SOC is stuck and displays it on the liquid crystal screen, thereby increasing the maintainability of the system and having great flexibility to meet various needs of customers for standby and downtime screens. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 This is a schematic diagram of the hardware circuit described in the embodiment of the utility model.

[0017] Figure 2 This is a logic block diagram of mounting SD NAND on FPGA according to an embodiment of the utility model.

[0018] Figure 3 This is a flow chart of a method for performing screen control based on a control circuit of FPGA SOC architecture according to an embodiment of the utility model.

[0019] Figure 4 This is another flow chart of the screen control method based on the control circuit of FPGA SOC architecture described in an embodiment of the utility model. DETAILED DESCRIPTION

[0020] The following describes in detail a method, a processing device and a server for processing user operation data according to an embodiment of the utility model in conjunction with the accompanying drawings.

[0021] It should be clear that the described embodiments are only part of the embodiments of the utility model, not all of them. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0022] like Figure 1 As shown, a control circuit based on FPGA SOC architecture also includes: SOC1, FPGA2, SD NAND3, SDRAM44, video encoder 5, the SOC1, FPGA2, video encoder 5 and LCD screen are connected in sequence, the FPGA2 is connected to SD NAND3 and SDRAM4 respectively, and the SOC1 and SD NAND3 are connected with a bus driver. SOC1 can adopt any mainstream platform such as NXP, HiSilicon, Rockchip, etc. FPGA2 can adopt any mainstream model of Altera or Xinlinx. SDRAM4 and video encoder 5 can also adopt any mainstream model in the market. SD NAND3 uses CSNP4GCR01-AMW from Shenzhen Leilong Development Co., Ltd., which does not require driver writing. It has NAND Flash (chip-type TF card) with built-in bad block management, small size, easy to use, strong compatibility, stable and reliable, customizable firmware, LGA-8 package, standard SDIO interface, compatible with SPI / SD interface, compatible with major MCU platforms, can replace ordinary TF card / SD card, size 6x8mm, built-in SLC wafer erase life of 100,000 times, and passed 10,000 random power-off tests. The bus driver uses TI's SN74AVC16T245DGGR, which has 16-way bidirectional signal control, uses 3.3V power supply, is compatible with TTL and CMOS levels, and has an enable control pin.

[0023] When SOC1 is stuck due to abnormal operation, FPGA2 outputs the key information saved before SOC1 is stuck and displays it on the LCD screen, which increases the maintainability of the system. It is flexible and can meet the various needs of customers for standby downtime screens. This method has wider adaptability and high maintainability, can meet the various needs of customers for standby downtime screens, and can be promoted and used in the field of vehicle-mounted displays to achieve better economic benefits.

[0024] like Figure 2 As shown, the FPGA2 also includes: an SD NAND / SDRAM parameter calculation module 21, an SD NAND read image control module 22 and an SDRAM controller 23, the SD NAND / SDRAM parameter calculation module 21, the SD NAND read image control module 22 and the SDRAM controller 23, the video output module 24 and the video encoder 5 are connected in sequence; the SDRAM controller 23 is connected to SDRAM4; the SD NAND controller 24 is connected between the SD NAND read image control module 22 and SD NAND3.

[0025] The FPGA2 further includes: a clock module 25, which is connected to the SD NAND / SDRAM parameter calculation module 21, the SD NAND read picture control module 22, the SDRAM controller 23, and the video output module 24. The clock module 25 provides a driving clock for other modules; the SD NAND / SDRAM parameter calculation module 21 provides parameters for the SDNAND read picture control module 22 and the SDRAM controller 23 according to information such as picture resolution; the SD NAND read picture control module 22 controls the read interface of the SD NAND controller 24, and converts the RGB888 format data read from the SD NAND3 into RGB565 format data, and writes it into the SDRAM controller 23; finally, the video output module 24 reads the picture data from the SDRAM controller 23 and displays it on the LCD screen.

[0026] like Figure 3 As shown, the embodiment of the utility model also provides a method for performing screen control using the above-mentioned control circuit based on FPGA SOC architecture, including:

[0027] S310, when the SOC is in standby or downtime, the FPGA does not detect the video signal output by the SOC, and turns off the control signal OE of the bus driver, and the FPGA mounts the SD NAND;

[0028] S320, start reading the picture file indication information from the SD NAND through the SDIO bus and output it to the LCD screen through the video encoder; the picture file indication information includes the information generated by the SOC drawing, which may include custom key information such as product Logo information, time information, data information received by the SoC before the crash (voltage, oil pressure, oil volume, speed, etc.); the picture file includes BMP picture information, and the BMP picture includes the standby (crash) screen.

[0029] like Figure 4 As shown, when the SOC is in standby or downtime, the FPGA does not detect the video signal output by the SOC, and turns off the control signal OE of the bus driver. Before the FPGA mounts the SD NAND, the following steps are also included:

[0030] S410, when the SOC is in operation, the video signal is normally output to the FPGA, and after the FPGA completes the processing, the video signal is output to the LCD screen through the video encoder;

[0031] S420, at the same time, the FPGA turns on the control signal OE of the bus driver and sets the SDIO bus to a high impedance state. At this time, the SOC mounts the SD NAND, and the SOC periodically saves the image file indication information to the SD NAND.

[0032] The embodiment of the utility model further provides a liquid crystal screen, wherein the liquid crystal screen is provided with the aforementioned control circuit based on FPGA SOC architecture.

[0033] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the utility model should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A control circuit based on FPGA SOC architecture, characterized in that: include: SOC, FPGA, SD NAND, SDRAM, video encoder, the SOC, FPGA, video encoder and LCD are connected in sequence, the SOC sends a signal to the FPGA, and the FPGA and SOC are mounted on the SD NAND respectively, the FPGA is connected to the SD NAND and SDRAM respectively, and the SOC and SD NAND are connected with a bus driver, The bus driver, the FPGA is connected to the output end of the SOC, and the bus driver controls the SOC to save the picture file to the SDNAND at a regular time, or controls the FPGA to read the picture file from the SDNAND; A clock module is also included, and the clock module provides clocks for the SOC and the SDRAM controller.

2. The control circuit based on FPGA SOC architecture according to claim 1, characterized in that: The FPGA also includes: an SD NAND / SDRAM parameter calculation module, an SD NAND picture reading control module and an SDRAM controller. The SDNAND / SDRAM parameter calculation module, the SD NAND picture reading control module and the SDRAM controller, the video output module and the video encoder are connected in sequence; the SDRAM controller is connected to the SDRAM; and the SD NAND controller is connected between the SDNAND picture reading control module and the SD NAND.

3. The control circuit based on FPGA SOC architecture according to claim 1, characterized in that: The FPGA also includes: a clock module, which is respectively connected to the SD NAND / SDRAM parameter calculation module, the SD NAND picture reading control module, the SDRAM controller, and the video output module.

4. A liquid crystal screen, characterized in that: The liquid crystal screen is provided with a control circuit based on FPGASOC architecture as claimed in any one of claims 1 to 3.

Images