Double-branch target buffer and branch target processing system and processing method

Abstract

The invention discloses a double-branch target buffer which comprises a first branch target buffer and a second branch target buffer, wherein the first branch target buffer comprises a first instruction caching units which has a connection structure of a plurality of channel units, the first instruction caching unit is used for temporarily storing prefetched instructions, and each of the channel units consists of a first storage and a second storage; the second branch target buffer comprises a second instruction caching units which has a connection structure of a plurality of channel units, the second instruction caching unit is used for temporarily storing prefetched instructions, and each of the channel units consists of a third storage and a fourth storage. The double-branch target buffer has two branch target buffers, so that the possibilities that different orders log in the same index can be reduced, the correct prediction accuracy of the branch target buffers is improved, and the speed of a central processing unit can be effectively increased.

Description

technical field [0001] The present invention relates to a processor with a branch prediction unit, in particular to a branch target buffer (Branch target buffer, BTB) in the branch prediction unit. Background technique [0002] Existing calculators are often pipelined, and "pipelining" (or also "speculative execution") is a term that usually refers to a method of operation in which a sequence of instructions is processed using a series of functional steps or processing stages, each processing Stages are usually completed in a single clock cycle. Each processing stage typically completes one or more of its constituent operations within a single clock cycle. [0003] Unlike non-pipelined processors, which process each instruction to completion before starting the next instruction, pipelined processors process several instructions simultaneously at different processing stages in the pipeline. The pipeline stage can be arbitrarily specified by the designer, but usually include...

AI Technical Summary

Problems solved by technology

[0009] The problem with the above BTB is that different commands may be registered in the same index, which will cause the branch target buffer to be unable to predict correctly

[0010] Some literature (J. K. F. Lee and A. J. Smith, "Branch prediction strategies and branch target buffer design," IEEE Comput. Mag. pp. 6-22, Jan. 1984) discloses such as figure 2 The BTB structure shown, although this method can alleviate the errors of BTB, there are still a lot of errors

Different commands may be registered in the same index, which will cause the branch target buffer to be incorrectly predicted

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