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Finite Field Square Calculation Circuit

A computing circuit and circuit technology, applied in the field of error correction and decoding circuits, can solve problems such as slower speed, increased delay, and low delay

Active Publication Date: 2016-09-28
MEMBLAZE TECH BEIJING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The invention discloses a high-speed, low-delay BM (Berlekamp-Massey) iterative decoding circuit, aiming to solve the BM iterative decoding link in the traditional BCH decoder. When the number of error correction bits increases, the speed becomes slow , the problem of increased delay

Method used

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  • Finite Field Square Calculation Circuit
  • Finite Field Square Calculation Circuit
  • Finite Field Square Calculation Circuit

Examples

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Embodiment Construction

[0060] figure 1 is a schematic diagram showing the basic structure of the Berlekamp-Massey iterative decoding circuit of the present invention. The iterative circuit designed in the present invention mainly includes three parts, odd syndrome calculation circuit 102 , even syndrome sequential calculation and syndrome sorting circuit 104 , and parallel iterative decoding circuit 106 .

[0061] When the binary BCH coded data 101 carrying multi-bit parity information was input to the iterative decoding circuit, at first the odd syndrome 103 of the BCH coded data was calculated by the odd syndrome calculation circuit 102, when there was no error bit in the data, All odd syndromes are 0, jumping out of iterative decoding. When there is an error bit in the data, the odd syndrome is not all 0, at this time, the odd syndrome is input to the even syndrome sequential calculation and syndrome sorting circuit 104, the even syndrome is obtained, and the syndrome 105 is output in parallel i...

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Abstract

The invention discloses a square calculation circuit of a generator field 213(GF 213), and provides a finite field square calculation circuit which comprises a plurality of exclusive-or gates, thirteen signal input ends and thirteen signal output ends.

Description

technical field [0001] The present invention generally relates to an error correction decoding circuit. More specifically, the present invention indicates a Berlekamp-Massey (BM) iterative decoding circuit with low delay characteristics, which is used to realize the BCH error correction decoder of high-speed NandFlash storage devices, and can also be applied to BCH in communication systems Error Correction Decoder. Background technique [0002] BCH code is a cyclic code that can correct multiple random errors independently proposed by Hocquenghem in 1959 and Bose and Chandhari in 1960; BCH code is a good class of linear error correction codes discovered so far. It has strong error correction ability and is widely used in the field of electronic communication information. [0003] In recent years, with the advancement of technology, the line width has decreased, the storage density of Nand Flash has continued to increase, and the probability of errors has also increased. A...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/15
Inventor 殷雪冰
Owner MEMBLAZE TECH BEIJING
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